2026-03-05 01:32:03.893 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.201.20:5700'
2026-03-05 01:32:03.893 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.201.20:5802)
2026-03-05 01:32:03.893 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.201.20:5801)
2026-03-05 01:32:03.893 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.201.22:6700'
2026-03-05 01:32:03.893 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.201.22:6802)
2026-03-05 01:32:03.893 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.201.22:6801)
2026-03-05 01:32:03.893 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.201.20:5700/1'
2026-03-05 01:32:03.894 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.201.20:5804)
2026-03-05 01:32:03.894 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.201.20:5803)
2026-03-05 01:32:03.894 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.201.20:5700/2'
2026-03-05 01:32:03.894 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.201.20:5806)
2026-03-05 01:32:03.894 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.201.20:5805)
2026-03-05 01:32:03.894 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.201.20:5700/3'
2026-03-05 01:32:03.894 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.201.20:5808)
2026-03-05 01:32:03.894 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.201.20:5807)
2026-03-05 01:32:03.894 [INFO] fake_trx.py:429 Init complete
2026-03-05 01:32:03.894 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-03-05 01:32:05.342 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:32:05.342 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:32:05.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:05.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:05.344 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:05.345 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:08.362 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:08.364 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:32:08.364 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:08.364 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:32:08.364 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 0 -> 1
2026-03-05 01:32:08.367 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:32:08.368 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:32:08.368 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:32:08.368 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:08.368 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:08.368 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:32:08.368 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:32:08.368 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 0 -> 1
2026-03-05 01:32:08.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:08.370 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:32:08.370 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:32:08.371 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:32:08.371 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:08.371 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:08.371 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:32:08.371 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:32:08.371 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 0 -> 1
2026-03-05 01:32:08.371 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:08.373 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:32:08.373 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:32:08.374 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:32:08.374 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:08.374 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:08.374 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:32:08.374 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:32:08.374 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 0 -> 1
2026-03-05 01:32:08.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:08.375 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:32:08.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:32:08.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:32:08.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:32:08.375 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:32:08.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:32:08.375 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:32:08.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:08.375 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:32:08.375 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:32:08.375 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:32:08.376 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:08.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:08.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:08.381 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:32:08.863 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:32:08.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:08.912 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:32:08.913 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:32:08.913 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:32:08.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:08.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:08.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:08.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:08.947 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:08.947 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:08.947 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:08.947 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:08.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:09.135 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:09.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:09.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:09.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:09.340 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:32:09.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:09.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:09.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:09.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:09.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:09.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:09.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:09.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:09.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:09.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:09.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:09.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:09.561 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:09.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:09.561 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:09.561 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:09.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:09.639 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:09.640 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:09.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:09.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:09.818 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:32:10.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:10.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:10.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:10.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:10.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:10.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:10.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:10.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:10.061 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:10.061 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:10.061 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:10.062 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:10.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:10.295 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:32:10.331 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:10.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:10.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:10.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:10.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:10.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:10.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:10.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:10.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:10.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:10.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:10.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:10.753 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:10.753 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:10.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:10.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:10.755 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:10.755 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:10.755 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:10.755 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:10.773 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:32:10.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:10.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:10.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:10.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:10.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:11.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:11.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:11.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:11.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:11.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:11.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:11.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:11.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:11.242 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:11.242 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:11.242 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:11.242 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:11.251 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:32:11.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:11.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:11.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:11.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:11.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:11.523 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:11.523 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:11.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:11.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:11.729 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:32:12.207 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:32:12.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:12.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:12.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:12.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:12.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:12.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:12.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:12.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:12.293 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:12.293 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:12.293 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:12.293 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:12.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:12.382 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:12.382 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:12.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:12.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:12.481 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:12.481 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:12.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:12.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:12.685 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:32:13.163 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:32:13.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:13.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:13.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:13.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:13.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:13.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:13.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:13.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:13.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:13.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:13.328 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:13.328 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:13.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:13.435 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:13.435 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:13.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:13.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:13.641 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:32:13.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:13.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:13.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:13.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:13.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:13.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:13.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:13.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:13.873 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:13.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:13.874 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:13.874 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:13.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:13.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:14.118 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:32:14.154 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:14.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:14.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:14.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:14.597 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:32:14.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:14.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:14.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:14.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:14.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:14.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:14.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:14.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:14.910 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:14.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:14.910 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:14.910 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:14.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:15.074 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:32:15.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:15.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:15.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:15.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:15.552 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:32:15.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:15.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:15.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:15.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:15.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:15.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:15.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:15.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:15.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:15.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:15.943 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:15.943 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:15.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:15.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:16.030 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:32:16.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:16.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:16.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:16.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:16.508 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:32:16.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:16.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:16.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:16.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:16.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:16.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:16.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:16.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:16.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:16.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:16.857 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:16.857 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:16.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:16.985 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:32:17.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:17.022 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:17.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:17.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:17.463 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:32:17.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:17.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:17.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:17.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:17.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:17.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:17.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:17.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:17.830 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:17.830 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:17.830 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:17.831 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:17.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:17.941 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:32:17.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:17.979 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:17.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:17.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:18.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:18.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:18.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:18.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:18.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:18.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:18.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:18.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:18.379 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:18.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:18.379 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:18.379 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:18.419 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:32:18.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:18.482 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:18.483 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:18.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:18.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:18.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:18.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:18.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:18.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:18.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:18.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:18.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:18.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:18.598 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:18.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:18.599 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:18.599 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:18.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:18.691 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:18.691 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:18.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:18.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:18.896 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:32:19.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:19.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:19.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:19.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:19.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:19.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:19.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:19.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:19.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:19.085 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:19.085 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:19.085 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:19.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:19.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:19.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:19.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:19.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:19.374 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:32:19.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:19.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:19.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:19.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:19.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:19.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:19.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:19.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:19.591 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:19.591 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:19.591 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:19.591 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:19.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:19.673 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:19.673 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:19.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:19.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:19.852 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:32:20.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:20.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:20.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:20.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:20.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:20.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:20.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:20.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:20.088 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:20.088 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:20.088 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:20.088 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:20.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:20.330 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:32:20.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:20.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:20.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:20.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:20.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:20.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:20.725 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:20.725 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:20.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:20.742 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:20.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:20.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:20.743 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:20.743 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:20.743 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:20.743 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:20.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:20.808 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:32:20.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:20.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:20.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:20.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:21.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:21.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:21.221 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:21.221 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:21.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:21.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:21.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:21.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:21.242 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:21.242 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:21.242 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:21.242 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:21.285 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:32:21.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:21.349 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:21.349 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:21.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:21.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:21.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:21.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:21.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:21.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:21.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:21.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:21.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:21.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:21.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:21.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:21.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:21.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:21.763 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:32:21.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:21.845 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:21.845 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:21.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:21.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:22.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:22.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:22.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:22.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:22.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:22.225 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:22.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:22.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:22.229 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:22.229 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:22.229 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:22.229 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:22.229 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:32:22.229 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:32:22.229 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:32:22.229 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2958 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:22.229 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2958 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:22.229 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2958 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:22.229 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2958 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:22.229 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2958 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:22.229 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2958 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:22.229 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2958 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:27.227 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:32:27.227 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:32:27.228 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:27.228 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:27.228 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:27.229 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:27.239 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:27.240 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:32:27.240 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:27.240 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:32:27.240 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:32:27.243 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:32:27.243 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:32:27.244 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:32:27.244 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:27.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:27.244 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:32:27.245 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:32:27.245 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:32:27.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:27.246 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:32:27.246 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:32:27.246 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:32:27.246 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:27.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:27.246 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:32:27.246 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:32:27.246 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:32:27.246 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:27.248 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:32:27.248 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:32:27.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:32:27.248 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:27.248 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:27.248 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:32:27.249 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:32:27.249 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:32:27.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:27.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:32:27.252 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:32:27.252 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:32:27.252 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:27.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:27.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:27.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:27.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:27.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:27.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:27.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:27.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:27.257 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:32:27.741 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:32:27.781 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:32:27.784 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:32:27.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.786 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:32:27.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:27.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:27.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:27.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:27.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.213 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:32:28.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.254 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:28.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:28.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:28.258 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:28.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.684 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:32:28.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:28.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.154 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:32:29.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:29.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:29.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:29.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:29.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.624 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:32:29.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:29.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:30.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:30.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:30.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:30.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:30.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:30.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:30.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:30.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:30.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:30.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:30.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:30.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:30.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:30.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:30.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:30.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:30.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:30.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:30.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:30.031 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:32:30.031 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:32:30.031 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:32:30.031 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:30.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=601 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:30.032 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=601 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:30.032 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=601 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:30.032 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=601 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:30.032 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=601 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:30.032 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=601 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:30.032 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=601 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:30.032 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=601 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:35.029 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:32:35.030 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:32:35.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:35.032 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:35.032 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:35.033 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:35.037 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:35.037 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:32:35.037 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:35.038 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:32:35.038 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:32:35.040 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:32:35.040 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:32:35.040 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:32:35.040 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:35.040 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:35.041 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:32:35.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:32:35.041 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:32:35.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:35.042 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:32:35.042 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:32:35.042 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:32:35.043 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:35.043 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:35.043 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:32:35.043 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:32:35.043 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:32:35.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:35.045 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:32:35.045 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:32:35.045 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:32:35.045 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:35.045 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:35.045 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:32:35.045 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:32:35.045 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:32:35.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:35.047 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:35.048 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:32:35.048 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:32:35.048 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:32:35.048 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:35.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:35.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:35.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:35.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:35.053 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:32:35.538 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:32:35.572 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:32:35.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:35.575 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:32:35.577 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:32:35.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:35.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:35.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:35.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:35.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:35.623 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:35.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:35.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:35.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:35.627 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:35.627 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:35.627 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:35.627 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:32:35.627 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:32:35.627 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:32:35.627 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:35.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:35.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:35.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:35.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:35.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:35.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:35.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:35.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:40.627 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:32:40.627 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:32:40.628 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:40.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:40.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:40.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:40.635 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:40.637 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:32:40.637 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:40.637 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:32:40.638 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:32:40.640 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:32:40.641 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:32:40.641 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:32:40.641 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:40.642 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:40.642 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:32:40.642 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:32:40.643 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:32:40.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:40.644 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:32:40.644 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:32:40.644 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:32:40.644 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:40.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:40.645 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:32:40.645 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:32:40.645 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:32:40.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:40.647 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:32:40.647 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:32:40.647 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:32:40.647 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:40.648 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:40.648 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:32:40.648 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:32:40.648 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:32:40.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:40.650 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:32:40.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:32:40.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:40.651 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:32:40.651 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:32:40.651 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:32:40.651 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:40.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:40.656 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:32:41.137 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:32:41.180 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:32:41.181 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:32:41.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:41.184 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:32:41.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:41.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:41.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:41.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:41.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:41.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:41.230 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:41.234 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:41.234 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:41.234 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:32:41.234 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:32:41.234 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:32:41.234 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:41.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:41.235 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:41.235 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:41.235 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:41.235 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:41.235 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:41.235 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:41.235 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:32:46.234 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:32:46.234 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:32:46.236 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:46.236 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:46.236 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:46.236 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:46.244 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:46.245 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:32:46.245 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:46.246 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:32:46.246 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:32:46.248 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:32:46.249 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:32:46.249 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:32:46.249 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:46.250 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:46.250 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:32:46.251 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:32:46.251 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:32:46.251 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:46.251 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:32:46.251 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:32:46.252 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:32:46.252 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:46.252 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:46.252 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:32:46.252 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:32:46.252 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:32:46.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:46.254 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:32:46.254 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:32:46.254 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:32:46.254 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:46.254 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:46.254 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:32:46.254 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:32:46.254 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:32:46.255 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:46.257 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:32:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:32:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:32:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:32:46.257 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:32:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:32:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:32:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:32:46.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:32:46.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:32:46.258 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:32:46.258 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:32:46.258 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:46.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:46.263 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:32:46.746 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:32:46.788 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:32:46.790 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:32:46.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:46.791 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:32:46.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:46.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:46.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:46.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:46.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:46.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:46.843 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:46.843 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:46.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:46.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:46.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:46.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:46.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:46.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:46.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:46.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:46.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:46.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:46.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:46.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:46.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:46.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:46.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:46.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:46.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:46.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:46.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:46.897 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:46.897 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:46.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:46.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:46.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:46.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:46.912 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:46.912 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:46.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:46.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:46.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:46.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:46.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:46.924 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:46.924 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:46.924 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:46.925 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:46.925 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:46.925 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:46.925 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:46.925 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:32:46.925 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:32:46.925 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:32:51.931 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:32:51.931 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:32:51.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:51.932 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:51.932 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:51.932 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:51.940 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:32:51.942 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:32:51.942 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:51.943 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:32:51.943 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:32:51.947 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:32:51.948 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:32:51.948 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:32:51.948 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:51.949 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:32:51.949 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:32:51.949 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:32:51.950 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:32:51.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:51.950 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:32:51.950 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:32:51.951 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:32:51.951 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:51.951 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:32:51.951 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:32:51.951 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:32:51.951 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:32:51.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:51.953 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:32:51.953 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:32:51.953 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:32:51.953 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:32:51.953 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:32:51.953 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:32:51.953 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:32:51.953 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:32:51.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:51.956 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:32:51.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:32:51.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:32:51.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:32:51.956 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:32:51.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:32:51.957 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:32:51.957 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:32:51.957 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:51.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:51.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:51.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:51.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:32:51.962 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:32:52.447 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:32:52.485 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:32:52.487 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:32:52.489 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:32:52.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:52.511 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:52.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:52.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:52.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:52.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:52.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:52.518 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:52.518 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:52.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:52.551 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:52.551 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:52.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:52.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:52.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:52.924 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:32:52.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:52.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:52.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:52.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:53.402 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:32:53.879 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:32:53.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:53.962 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:53.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:53.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:54.358 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:32:54.836 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:32:54.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:54.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:54.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:54.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:55.313 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:32:55.791 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:32:55.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:55.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:55.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:55.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:56.269 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:32:56.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:56.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:56.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:56.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:56.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:32:56.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:32:56.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:32:56.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:56.673 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:56.673 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:56.673 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:32:56.673 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:32:56.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:56.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:32:56.693 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:32:56.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:56.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:32:56.748 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:32:56.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:32:56.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:32:56.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:32:56.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:32:56.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:32:57.225 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:32:57.704 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:32:58.182 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:32:58.660 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:32:59.138 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:32:59.615 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:33:00.093 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:33:00.571 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:33:00.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:00.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:00.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:00.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:00.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:00.990 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:00.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:00.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:00.991 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:00.991 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:00.991 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:00.991 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:01.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:01.049 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:33:01.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:01.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:01.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:01.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:01.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:01.526 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:33:02.004 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:33:02.482 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:33:02.960 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:33:03.438 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:33:03.916 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:33:04.395 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:33:04.873 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:33:05.351 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:33:05.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:05.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:05.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:05.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:05.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:05.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:05.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:05.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:05.511 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:05.511 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:05.511 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:05.511 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:05.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:05.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:05.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:05.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:05.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:05.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:05.828 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:33:06.306 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:33:06.784 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:33:07.262 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:33:07.740 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:33:08.218 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:33:08.695 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:33:09.173 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:33:09.651 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:33:09.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:09.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:09.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:09.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:09.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:09.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:09.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:09.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:09.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:09.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:09.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:09.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:09.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:09.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:09.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:09.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:09.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:10.128 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:33:10.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:10.605 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:33:11.083 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:33:11.562 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:33:12.040 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:33:12.518 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:33:12.995 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:33:13.474 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:33:13.952 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:33:14.429 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:33:14.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:14.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:14.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:14.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:14.495 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:14.495 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:14.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:14.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:14.496 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:14.496 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:14.496 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:14.496 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:14.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:14.530 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:14.530 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:14.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:14.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:14.908 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:33:14.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:15.385 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:33:15.864 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:33:16.342 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:33:16.819 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:33:17.298 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:33:17.775 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:33:18.253 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:33:18.731 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:33:18.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:18.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:18.927 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:18.927 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:18.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:18.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:18.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:18.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:18.939 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:18.939 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:18.939 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:18.939 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:18.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:18.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:18.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:18.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:18.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:19.208 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:33:19.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:19.686 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:33:20.164 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 01:33:20.642 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 01:33:21.120 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 01:33:21.598 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 01:33:22.076 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 01:33:22.554 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 01:33:23.032 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 01:33:23.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:23.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:23.369 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:23.369 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:23.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:23.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:23.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:23.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:23.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:23.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:23.384 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:23.384 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:23.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:33:23.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:23.407 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:23.407 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:23.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:23.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:23.509 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 01:33:23.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:23.987 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 01:33:24.465 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 01:33:24.944 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 01:33:25.422 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 01:33:25.900 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 01:33:26.378 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 01:33:26.856 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 01:33:27.333 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 01:33:27.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:27.811 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 01:33:27.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:27.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:27.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:27.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:27.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:27.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:27.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:27.834 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:27.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:27.834 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:27.834 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:27.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:27.864 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:27.865 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:27.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:27.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:28.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:28.289 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 01:33:28.767 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 01:33:29.245 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 01:33:29.723 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 01:33:30.201 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 01:33:30.680 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 01:33:31.158 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 01:33:31.636 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 01:33:32.115 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 01:33:32.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:32.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:32.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:32.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:32.259 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=8601 tn=1 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:33:32.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:32.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:32.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:32.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:32.280 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:32.280 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:32.280 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:32.280 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:32.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:33:32.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:32.302 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:32.302 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:32.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:32.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:32.592 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 01:33:33.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:33.070 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 01:33:33.549 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 01:33:34.027 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 01:33:34.505 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 01:33:34.983 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 01:33:35.461 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 01:33:35.939 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 01:33:36.417 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 01:33:36.895 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 01:33:37.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:37.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:37.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:37.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:37.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:37.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:37.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:37.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:37.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:37.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:37.093 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:37.093 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:37.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:37.139 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:37.139 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:37.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:37.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:37.371 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 01:33:37.849 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 01:33:37.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:38.328 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 01:33:38.806 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 01:33:39.284 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 01:33:39.762 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 01:33:40.241 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 01:33:40.718 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 01:33:41.196 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 01:33:41.675 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 01:33:41.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:41.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:41.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:41.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:41.970 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:41.971 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:41.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:41.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:41.972 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:41.972 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:41.972 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:41.972 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:42.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:42.013 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:42.013 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:42.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:42.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:42.152 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 01:33:42.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:42.630 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 01:33:43.109 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 01:33:43.587 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 01:33:44.065 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 01:33:44.544 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 01:33:45.022 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 01:33:45.499 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 01:33:45.977 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 01:33:46.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:46.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:46.398 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:46.398 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:46.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:46.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:46.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:46.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:46.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:46.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:46.418 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:46.418 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:46.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:46.455 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 01:33:46.457 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:46.457 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:46.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:46.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:46.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:46.933 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 01:33:47.411 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 01:33:47.889 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 01:33:48.367 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 01:33:48.845 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 01:33:49.323 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 01:33:49.801 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 01:33:50.278 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 01:33:50.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:50.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:50.616 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:50.616 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:50.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:50.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:50.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:50.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:50.628 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:50.628 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:50.628 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:50.628 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:50.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:50.659 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:50.660 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:50.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:50.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:50.756 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 01:33:50.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:51.234 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 01:33:51.712 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 01:33:52.190 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 01:33:52.668 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-05 01:33:53.146 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-05 01:33:53.623 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-05 01:33:54.102 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-05 01:33:54.580 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-05 01:33:54.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:54.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:54.937 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:54.937 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:54.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:54.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:54.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:54.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:54.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:54.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:54.958 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:54.958 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:55.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:55.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:55.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:55.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:55.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:55.057 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-05 01:33:55.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:55.535 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-05 01:33:56.013 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-05 01:33:56.490 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-05 01:33:56.968 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-05 01:33:57.446 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-05 01:33:57.923 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-05 01:33:58.401 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-05 01:33:58.879 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-05 01:33:59.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:59.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:59.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:59.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:59.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:33:59.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:33:59.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:33:59.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:59.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:59.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:59.264 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:33:59.264 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:33:59.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:59.310 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:33:59.310 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:33:59.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:59.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:33:59.356 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-05 01:33:59.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:33:59.834 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-05 01:34:00.312 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-05 01:34:00.790 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-05 01:34:01.267 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-05 01:34:01.745 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-05 01:34:02.222 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-05 01:34:02.699 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-05 01:34:03.176 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-05 01:34:03.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:03.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:03.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:03.573 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:03.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:03.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:03.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:03.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:03.594 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:03.594 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:03.595 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:03.595 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:03.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:03.654 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-05 01:34:03.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:03.659 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:03.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:03.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:04.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:04.131 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-05 01:34:04.609 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-05 01:34:05.087 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-05 01:34:05.565 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-05 01:34:06.043 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-05 01:34:06.522 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-05 01:34:07.000 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-05 01:34:07.478 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-05 01:34:07.956 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-05 01:34:08.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:08.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:08.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:08.052 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:08.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:08.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:08.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:08.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:08.069 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:08.069 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:08.069 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:08.069 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:08.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:08.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:08.104 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:08.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:08.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:08.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:08.434 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-05 01:34:08.912 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-05 01:34:09.390 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-05 01:34:09.868 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-05 01:34:10.346 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-05 01:34:10.824 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-05 01:34:11.302 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-05 01:34:11.779 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-05 01:34:12.257 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-05 01:34:12.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:12.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:12.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:12.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:12.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:12.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:12.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:12.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:12.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:12.393 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:12.393 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:12.393 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:12.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:12.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:12.445 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:12.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:12.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:12.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:12.735 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-05 01:34:13.213 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-05 01:34:13.691 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-05 01:34:14.169 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-05 01:34:14.647 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-05 01:34:15.125 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-05 01:34:15.603 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-05 01:34:16.081 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-05 01:34:16.559 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-05 01:34:16.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:16.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:16.691 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:16.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:16.704 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:16.704 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:16.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:16.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:16.706 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:16.706 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:16.706 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:16.706 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:16.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:16.750 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:16.751 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:16.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:16.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:17.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:17.034 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-05 01:34:17.512 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-05 01:34:17.990 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-05 01:34:18.468 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-05 01:34:18.945 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-05 01:34:19.423 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-05 01:34:19.901 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-05 01:34:20.378 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-05 01:34:20.856 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-05 01:34:21.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:21.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:21.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:21.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:21.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:21.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:21.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:21.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:21.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:34:21.019 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:34:21.019 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:34:21.019 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:34:21.019 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:34:21.019 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:34:21.019 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:34:26.022 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:34:26.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:34:26.024 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:34:26.025 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:34:26.026 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:34:26.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:34:26.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:34:26.037 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:34:26.037 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:34:26.037 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:34:26.037 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:34:26.041 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:34:26.041 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:34:26.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:34:26.041 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:34:26.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:34:26.042 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:34:26.042 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:34:26.042 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:34:26.042 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:26.044 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:34:26.044 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:34:26.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:34:26.044 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:34:26.044 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:34:26.044 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:34:26.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:34:26.044 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:34:26.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:26.046 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:34:26.046 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:34:26.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:34:26.046 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:34:26.047 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:34:26.047 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:34:26.047 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:34:26.047 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:34:26.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:26.050 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:34:26.050 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:34:26.050 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:34:26.051 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:34:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:26.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:34:26.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:26.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:26.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:26.052 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:34:26.052 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:34:26.052 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:34:26.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:26.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:26.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:31.056 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:34:31.056 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:34:31.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:34:31.059 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:34:31.059 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:34:31.060 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:34:31.069 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:34:31.071 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:34:31.071 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:34:31.072 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:34:31.072 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:34:31.077 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:34:31.077 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:34:31.078 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:34:31.078 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:34:31.078 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:34:31.079 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:34:31.079 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:34:31.079 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:34:31.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:31.080 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:34:31.081 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:34:31.081 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:34:31.081 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:34:31.081 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:34:31.081 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:34:31.081 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:34:31.081 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:34:31.082 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:31.083 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:34:31.083 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:34:31.084 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:34:31.084 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:34:31.084 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:34:31.084 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:34:31.084 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:34:31.084 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:34:31.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:31.086 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:34:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:34:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:34:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:34:31.086 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:34:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:34:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:34:31.087 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:34:31.087 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:34:31.087 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:31.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:31.092 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:34:31.576 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:34:31.612 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:34:31.613 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:34:31.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:31.615 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:34:31.639 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:31.639 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:31.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:31.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:31.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:31.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:31.644 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:31.644 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:31.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:31.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:31.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:31.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:31.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:31.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:31.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:31.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:31.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:31.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:31.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:31.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:31.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:31.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:31.804 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:31.804 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:31.804 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:31.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:31.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:31.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:31.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:31.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:32.051 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:34:32.089 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:32.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:32.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:32.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:32.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:32.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:32.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:32.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:32.290 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:32.290 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:32.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:32.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:32.292 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:32.292 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:32.292 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:32.292 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:32.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:32.346 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:32.346 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:32.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:32.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:32.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:32.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:32.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:32.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:32.506 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:32.506 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:32.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:32.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:32.507 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:32.507 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:32.507 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:32.507 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:32.528 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:34:32.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:32.557 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:32.558 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:32.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:32.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:32.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:32.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:33.006 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:33.006 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:34:33.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:33.006 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=407 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:34:33.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:33.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:33.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:33.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:33.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:33.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:33.024 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:33.024 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:33.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:33.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:33.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:33.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:33.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:33.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:33.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:33.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:33.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:33.484 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:34:33.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:33.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:33.524 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:33.524 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:33.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:33.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:33.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:33.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:33.546 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:33.546 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:33.546 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:33.546 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:33.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:33.594 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:33.595 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:33.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:33.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:33.962 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:34:34.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:34.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:34.071 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:34.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:34.089 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:34.089 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:34.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:34.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:34.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:34.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:34.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:34.091 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:34.091 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:34.091 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:34.091 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:34.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:34.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:34.144 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:34.144 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:34.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:34.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:34.440 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:34:34.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:34.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:34.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:34.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:34.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:34.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:34.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:34.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:34.638 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:34.638 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:34.638 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:34.638 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:34.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:34.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:34.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:34.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:34.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:34.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:34.918 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:34:35.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:35.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:35.092 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:35.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:35.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:35.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:35.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:35.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:35.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:35.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:35.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:35.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:35.187 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:35.187 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:35.187 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:35.187 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:35.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:35.237 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:35.238 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:35.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:35.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:35.396 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:34:35.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:35.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:35.712 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:35.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:35.731 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:35.731 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:35.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:35.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:35.733 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:35.733 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:35.733 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:35.733 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:35.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:35.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:35.783 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:35.783 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:35.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:35.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:35.874 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:34:36.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:36.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:36.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:36.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:36.353 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:34:36.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:36.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:36.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:36.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:36.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:36.646 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:36.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:36.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:36.649 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:36.649 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:36.649 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:36.649 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:36.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:36.697 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:36.698 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:36.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:36.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:36.831 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:34:37.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:37.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:37.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:37.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:37.114 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=1287 tn=1 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:34:37.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:37.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:37.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:37.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:37.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:37.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:37.134 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:37.134 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:37.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:37.185 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:37.186 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:37.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:37.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:37.309 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:34:37.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:37.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:37.661 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:37.661 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:37.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:37.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:37.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:37.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:37.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:37.682 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:37.682 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:37.682 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:37.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:37.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:37.737 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:37.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:37.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:37.786 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:34:37.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:37.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:37.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:37.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:37.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:37.956 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:37.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:37.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:37.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:37.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:37.958 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:37.958 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:37.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:38.026 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:38.026 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:38.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:38.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:38.265 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:34:38.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:38.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:38.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:38.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:38.456 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:38.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:38.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:38.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:38.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:38.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:38.459 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:38.459 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:38.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:38.510 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:38.511 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:38.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:38.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:38.742 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:34:38.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:38.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:38.939 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:38.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:38.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:38.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:38.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:38.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:38.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:38.956 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:38.956 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:38.956 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:38.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:39.008 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:39.009 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:39.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:39.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:39.219 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:34:39.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:39.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:39.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:39.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:39.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:39.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:39.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:39.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:39.447 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:39.447 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:39.447 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:39.447 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:39.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:39.498 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:39.498 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:39.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:39.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:39.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:39.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:39.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:39.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:39.630 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:39.630 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:39.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:39.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:39.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:39.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:39.631 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:39.631 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:39.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:39.685 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:39.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:39.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:39.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:39.696 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:34:40.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:40.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:40.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:40.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:40.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:40.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:40.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:40.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:40.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:40.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:40.132 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:40.132 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:40.173 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:34:40.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:40.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:40.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:40.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:40.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:40.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:40.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:40.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:40.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:40.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:40.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:40.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:40.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:40.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:40.625 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:40.625 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:40.625 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:40.651 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:34:40.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:40.674 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:40.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:40.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:40.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:41.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:41.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:41.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:41.102 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:41.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:41.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:41.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:41.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:41.109 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:34:41.109 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:34:41.109 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:34:41.109 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:34:41.109 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:34:41.109 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:34:41.109 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:34:41.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2141 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:34:41.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2141 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:34:41.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2141 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:34:41.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2141 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:34:41.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2141 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:34:41.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2141 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:34:41.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2141 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:34:41.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2141 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:34:46.112 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:34:46.112 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:34:46.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:34:46.116 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:34:46.116 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:34:46.116 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:34:46.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:34:46.128 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:34:46.128 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:34:46.128 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:34:46.129 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:34:46.132 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:34:46.132 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:34:46.133 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:34:46.133 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:34:46.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:34:46.134 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:34:46.134 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:34:46.134 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:34:46.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:46.135 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:34:46.135 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:34:46.135 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:34:46.135 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:34:46.136 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:34:46.136 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:34:46.136 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:34:46.136 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:34:46.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:46.138 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:34:46.138 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:34:46.138 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:34:46.138 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:34:46.138 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:34:46.138 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:34:46.138 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:34:46.138 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:34:46.138 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:46.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:34:46.142 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:34:46.142 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:34:46.142 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:46.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:46.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:46.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:46.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:46.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:46.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:34:46.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:46.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:34:46.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:34:46.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:46.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:46.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:46.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:46.147 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:34:46.629 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:34:46.686 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:34:46.689 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:34:46.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:46.692 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:34:46.715 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:46.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:46.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:46.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:46.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:46.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:46.724 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:46.724 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:46.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:46.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:46.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:46.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:46.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:47.104 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:34:47.146 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:47.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:47.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:47.154 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:47.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:47.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:47.581 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:34:47.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:47.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:47.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:47.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:47.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:47.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:47.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:47.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:47.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:47.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:47.803 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:47.803 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:47.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:47.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:47.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:47.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:47.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:48.056 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:34:48.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:48.149 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:48.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:48.155 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:48.534 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:34:48.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:48.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:49.012 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:34:49.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:49.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:49.151 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:49.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:49.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:49.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:49.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:49.236 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:49.255 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:49.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:49.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:49.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:49.257 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:49.257 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:49.257 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:49.257 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:49.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:49.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:49.306 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:49.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:49.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:49.490 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:34:49.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:49.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:49.968 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:34:50.148 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:50.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:50.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:50.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:50.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:50.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:50.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:50.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:50.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:50.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:50.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:50.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:50.428 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:50.428 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:50.428 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:50.428 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:50.445 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:34:50.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:50.482 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:50.482 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:50.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:50.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:50.922 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:34:51.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:34:51.152 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:34:51.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:34:51.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:34:51.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:51.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:51.400 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:34:51.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:51.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:51.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:51.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:51.868 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:51.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:51.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:51.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:51.870 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:51.870 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:51.870 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:51.870 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:51.878 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:34:51.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:51.932 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:51.933 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:51.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:51.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:52.355 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:34:52.834 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:34:52.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:52.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:53.312 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:34:53.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:53.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:53.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:53.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:53.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:53.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:53.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:53.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:53.451 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:53.451 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:53.451 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:53.451 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:53.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:53.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:53.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:53.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:53.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:53.787 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:34:54.266 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:34:54.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:54.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:54.745 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:34:54.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:54.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:54.965 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:54.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:54.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:54.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:54.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:54.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:54.989 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:54.989 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:54.989 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:54.989 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:55.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:55.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:55.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:55.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:55.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:55.222 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:34:55.700 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:34:55.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:55.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:56.179 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:34:56.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:56.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:56.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:56.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:56.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:56.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:56.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:56.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:56.506 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:56.506 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:56.506 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:56.506 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:56.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:56.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:56.556 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:56.556 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:56.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:56.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:56.657 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:34:57.135 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:34:57.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:57.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:57.614 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:34:58.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:58.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:58.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:58.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:58.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:58.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:58.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:58.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:58.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:58.028 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:58.029 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:58.029 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:58.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:58.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:58.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:58.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:58.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:58.092 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:34:58.571 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:34:59.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:59.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:59.049 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:34:59.528 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:34:59.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:59.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:59.531 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:59.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:59.550 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:34:59.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:34:59.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:34:59.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:59.553 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:59.553 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:59.553 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:34:59.553 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:34:59.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:34:59.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:34:59.604 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:34:59.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:34:59.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:34:59.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:00.005 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:35:00.483 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:35:00.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:00.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:00.961 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:35:01.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:01.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:01.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:01.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:01.438 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:35:01.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:01.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:01.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:01.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:01.441 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:01.441 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:01.441 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:01.441 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:01.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:01.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:01.495 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:01.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:01.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:01.916 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:35:02.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:02.394 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:35:02.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:02.873 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:35:02.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:02.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:02.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:02.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:02.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:02.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:02.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:02.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:02.910 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:02.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:02.910 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:02.910 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:02.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:02.965 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:02.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:02.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:02.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:03.351 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:35:03.829 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:35:03.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:03.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:04.307 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:35:04.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:04.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:04.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:04.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:04.428 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:04.428 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:04.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:04.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:04.430 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:04.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:04.431 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:04.431 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:04.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:04.481 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:04.482 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:04.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:04.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:04.785 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:35:05.262 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:35:05.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:05.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:05.740 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:35:05.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:05.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:05.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:05.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:05.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:05.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:05.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:05.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:05.923 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:05.923 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:05.923 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:05.923 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:05.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:05.981 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:05.982 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:05.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:05.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:06.219 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:35:06.697 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:35:06.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:06.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:07.175 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:35:07.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:07.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:07.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:07.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:07.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:07.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:07.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:07.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:07.364 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:07.364 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:07.364 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:07.364 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:07.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:07.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:07.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:07.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:07.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:07.658 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:35:08.136 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:35:08.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:08.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:08.614 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:35:08.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:08.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:08.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:08.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:08.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:08.819 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:08.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:08.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:08.821 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:08.821 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:08.821 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:08.821 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:08.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:08.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:08.873 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:08.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:08.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:09.091 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:35:09.569 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:35:09.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:09.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:10.047 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:35:10.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:10.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:10.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:10.262 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:10.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:10.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:10.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:10.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:10.272 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:10.272 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:10.272 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:10.272 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:10.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:10.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:10.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:10.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:10.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:10.524 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:35:10.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:10.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:11.002 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:35:11.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:11.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:11.396 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:11.396 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:11.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:11.414 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:11.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:11.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:11.416 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:11.416 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:11.416 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:11.416 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:11.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:11.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:11.466 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:11.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:11.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:11.479 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:35:11.948 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:35:12.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:12.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:12.417 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:35:12.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:12.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:12.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:12.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:12.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:12.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:12.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:12.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:12.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:12.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:12.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:12.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:12.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:12.893 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:35:12.896 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:12.896 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:12.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:12.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:13.371 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:35:13.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:13.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:13.849 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:35:14.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:14.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:14.281 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:14.281 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:14.290 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:14.290 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:14.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:14.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:14.292 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:14.292 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:14.292 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:14.292 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:14.327 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 01:35:14.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:14.347 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:14.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:14.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:14.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:14.805 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 01:35:15.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:15.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:15.282 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 01:35:15.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:15.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:15.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:15.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:15.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:35:15.743 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:35:15.743 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:35:15.743 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:35:15.747 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:35:15.747 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:35:15.747 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:35:15.747 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:35:15.747 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:35:15.747 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:35:15.747 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:35:15.747 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6324 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:35:15.747 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6324 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:35:15.747 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6324 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:35:15.747 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6324 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:35:15.747 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6324 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:35:15.747 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6324 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:35:15.747 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6324 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:35:15.747 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6324 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:35:20.747 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:35:20.747 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:35:20.748 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:35:20.750 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:35:20.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:35:20.751 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:35:20.754 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:35:20.754 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:35:20.754 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:35:20.754 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:35:20.754 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:35:20.756 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:35:20.756 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:35:20.756 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:35:20.756 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:35:20.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:35:20.756 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:35:20.757 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:35:20.757 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:35:20.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:35:20.758 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:35:20.759 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:35:20.759 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:35:20.759 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:35:20.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:35:20.759 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:35:20.759 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:35:20.759 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:35:20.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:35:20.761 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:35:20.761 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:35:20.761 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:35:20.761 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:35:20.761 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:35:20.761 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:35:20.761 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:35:20.761 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:35:20.761 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:35:20.763 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:35:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:35:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:35:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:35:20.763 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:35:20.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:35:20.764 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:35:20.764 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:35:20.764 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:35:20.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:35:20.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:35:20.769 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:35:21.251 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:35:21.292 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:35:21.294 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:35:21.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:21.296 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:35:21.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:21.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:21.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:21.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:21.318 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:21.318 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:21.318 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:21.318 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:21.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:21.354 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:21.354 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:21.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:21.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:21.725 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:35:21.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:35:21.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:35:21.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:35:21.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:35:22.201 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:35:22.678 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:35:22.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:35:22.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:35:22.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:35:22.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:35:23.156 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:35:23.634 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:35:23.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:35:23.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:35:23.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:35:23.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:35:24.111 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:35:24.590 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:35:24.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:35:24.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:35:24.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:35:24.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:35:25.068 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:35:25.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:25.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:25.272 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:25.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:25.290 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:25.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:25.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:25.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:25.293 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:25.293 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:25.293 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:25.293 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:25.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:25.342 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:25.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:25.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:25.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:25.545 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:35:25.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:35:25.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:35:25.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:35:25.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:35:26.022 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:35:26.500 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:35:26.978 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:35:27.456 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:35:27.934 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:35:28.412 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:35:28.890 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:35:29.368 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:35:29.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:29.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:29.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:29.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:29.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:29.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:29.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:29.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:29.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:29.612 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:29.612 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:29.612 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:29.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:29.662 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:29.662 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:29.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:29.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:29.845 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:35:30.323 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:35:30.801 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:35:31.280 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:35:31.758 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:35:32.235 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:35:32.713 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:35:33.191 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:35:33.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:33.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:33.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:33.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:33.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:33.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:33.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:33.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:33.652 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:33.652 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:33.652 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:33.652 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:33.669 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:35:33.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:33.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:33.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:33.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:33.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:34.148 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:35:34.626 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:35:35.103 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:35:35.582 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:35:36.060 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:35:36.538 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:35:37.016 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:35:37.494 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:35:37.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:37.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:37.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:37.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:37.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:37.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:37.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:37.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:37.971 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:35:37.971 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:37.971 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:37.971 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:37.971 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:38.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:38.025 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:38.026 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:38.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:38.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:38.449 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:35:38.927 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:35:39.405 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:35:39.883 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:35:40.361 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:35:40.839 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:35:41.318 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:35:41.796 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:35:42.274 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:35:42.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:42.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:42.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:42.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:42.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:42.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:42.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:42.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:42.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:42.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:42.718 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:42.718 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:42.752 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:35:42.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:42.771 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:42.771 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:42.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:42.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:43.230 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:35:43.708 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:35:44.186 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:35:44.664 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:35:45.143 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:35:45.621 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:35:46.100 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:35:46.578 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:35:47.055 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:35:47.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:47.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:47.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:47.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:47.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:47.152 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:47.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:47.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:47.155 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:47.155 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:47.155 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:47.155 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:47.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:47.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:47.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:47.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:47.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:47.534 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:35:48.012 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:35:48.490 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:35:48.969 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 01:35:49.447 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 01:35:49.925 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 01:35:50.404 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 01:35:50.882 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 01:35:51.360 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 01:35:51.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:51.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:51.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:51.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:51.600 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:51.600 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:51.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:51.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:51.602 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:51.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:51.602 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:51.602 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:51.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:35:51.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:51.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:51.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:51.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:51.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:51.838 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 01:35:52.316 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 01:35:52.795 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 01:35:53.273 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 01:35:53.751 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 01:35:54.229 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 01:35:54.707 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 01:35:55.186 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 01:35:55.664 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 01:35:56.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:56.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:56.031 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:56.031 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:56.048 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:35:56.048 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:35:56.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:35:56.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:56.050 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:56.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:56.051 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:35:56.051 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:35:56.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:35:56.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:35:56.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:35:56.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:56.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:35:56.142 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 01:35:56.619 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 01:35:57.098 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 01:35:57.576 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 01:35:58.055 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 01:35:58.533 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 01:35:59.012 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 01:35:59.490 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 01:35:59.968 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 01:36:00.447 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 01:36:00.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:00.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:00.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:00.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:00.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:00.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:00.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:36:00.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:00.506 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:00.506 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:00.506 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:36:00.506 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:36:00.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:00.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:00.559 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:00.559 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:00.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:00.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:00.924 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 01:36:01.403 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 01:36:01.881 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 01:36:02.359 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 01:36:02.837 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 01:36:03.316 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 01:36:03.794 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 01:36:04.272 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 01:36:04.750 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 01:36:04.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:04.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:04.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:04.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:04.813 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=9399 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:36:04.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:04.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:04.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:36:04.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:04.831 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:04.831 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:04.831 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:36:04.831 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:36:04.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:04.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:04.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:04.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:04.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:05.226 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 01:36:05.703 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 01:36:06.181 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 01:36:06.660 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 01:36:07.138 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 01:36:07.616 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 01:36:08.095 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 01:36:08.572 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 01:36:09.051 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 01:36:09.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:09.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:09.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:09.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:09.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:09.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:09.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:36:09.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:09.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:09.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:09.212 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:36:09.212 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:36:09.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:09.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:09.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:09.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:09.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:09.528 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 01:36:10.006 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 01:36:10.484 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 01:36:10.962 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 01:36:11.441 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 01:36:11.919 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 01:36:12.398 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 01:36:12.876 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 01:36:13.355 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 01:36:13.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:13.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:13.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:13.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:13.661 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:13.661 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:13.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:36:13.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:13.664 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:13.664 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:13.664 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:36:13.664 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:36:13.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:13.716 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:13.716 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:13.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:13.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:13.832 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 01:36:14.310 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 01:36:14.789 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 01:36:15.267 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 01:36:15.745 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 01:36:16.223 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 01:36:16.701 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 01:36:17.180 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 01:36:17.658 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 01:36:17.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:17.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:17.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:17.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:17.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:17.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:17.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:36:17.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:17.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:17.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:17.837 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:36:17.837 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:36:17.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:17.887 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:17.888 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:17.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:17.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:18.136 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 01:36:18.614 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 01:36:19.092 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 01:36:19.570 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 01:36:20.048 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 01:36:20.526 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 01:36:21.005 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 01:36:21.483 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-05 01:36:21.961 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-05 01:36:22.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:22.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:22.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:22.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:22.158 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:22.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:22.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:36:22.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:22.161 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:22.161 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:22.161 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:36:22.161 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:36:22.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:22.234 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:22.234 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:22.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:22.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:22.439 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-05 01:36:22.917 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-05 01:36:23.395 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-05 01:36:23.873 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-05 01:36:24.351 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-05 01:36:24.829 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-05 01:36:25.307 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-05 01:36:25.785 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-05 01:36:26.263 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-05 01:36:26.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:26.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:26.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:26.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:26.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:26.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:26.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:36:26.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:26.481 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:26.481 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:26.481 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:36:26.481 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:36:26.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:26.530 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:26.530 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:26.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:26.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:26.741 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-05 01:36:27.218 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-05 01:36:27.697 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-05 01:36:28.176 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-05 01:36:28.654 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-05 01:36:29.131 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-05 01:36:29.608 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-05 01:36:30.086 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-05 01:36:30.564 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-05 01:36:30.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:30.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:30.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:30.779 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:30.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:30.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:30.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:36:30.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:30.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:30.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:30.793 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:36:30.793 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:36:30.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:30.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:30.842 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:30.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:30.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:31.042 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-05 01:36:31.520 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-05 01:36:31.998 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-05 01:36:32.475 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-05 01:36:32.953 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-05 01:36:33.432 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-05 01:36:33.910 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-05 01:36:34.387 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-05 01:36:34.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:34.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:34.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:34.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:34.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:34.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:34.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:36:34.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:34.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:34.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:34.802 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:36:34.802 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:36:34.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:34.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:34.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:34.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:34.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:34.864 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-05 01:36:35.341 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-05 01:36:35.818 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-05 01:36:36.296 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-05 01:36:36.775 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-05 01:36:37.253 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-05 01:36:37.731 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-05 01:36:38.209 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-05 01:36:38.686 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-05 01:36:39.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:39.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:39.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:39.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:39.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:39.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:39.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:36:39.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:39.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:39.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:39.121 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:36:39.121 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:36:39.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:39.163 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-05 01:36:39.169 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:39.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:39.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:39.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:39.641 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-05 01:36:40.119 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-05 01:36:40.597 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-05 01:36:41.075 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-05 01:36:41.553 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-05 01:36:42.031 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-05 01:36:42.509 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-05 01:36:42.987 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-05 01:36:43.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:43.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:43.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:43.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:43.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:43.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:43.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:36:43.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:43.438 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:43.439 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:43.439 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:36:43.439 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:36:43.464 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-05 01:36:43.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:43.490 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:43.490 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:43.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:43.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:43.942 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-05 01:36:44.419 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-05 01:36:44.897 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-05 01:36:45.375 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-05 01:36:45.853 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-05 01:36:46.331 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-05 01:36:46.808 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-05 01:36:47.286 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-05 01:36:47.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:47.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:47.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:47.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:47.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:36:47.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:36:47.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:36:47.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:36:47.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:36:47.746 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:36:47.746 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:36:47.746 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:36:47.746 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:36:47.746 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:36:47.746 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:36:52.749 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:36:52.749 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:36:52.751 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:36:52.751 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:36:52.751 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:36:52.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:36:52.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:36:52.760 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:36:52.760 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:36:52.761 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:36:52.761 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:36:52.765 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:36:52.766 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:36:52.766 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:36:52.766 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:36:52.766 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:36:52.767 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:36:52.767 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:36:52.767 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:36:52.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:36:52.772 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:36:52.772 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:36:52.772 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:36:52.772 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:36:52.772 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:36:52.773 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:36:52.773 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:36:52.773 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:36:52.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:36:52.775 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:36:52.775 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:36:52.775 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:36:52.775 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:36:52.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:36:52.776 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:36:52.776 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:36:52.776 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:36:52.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:36:52.779 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:36:52.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:36:52.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:36:52.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:36:52.779 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:52.780 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:36:52.780 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:36:52.780 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:36:52.781 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:36:52.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:52.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:52.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:52.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:36:52.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:52.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:52.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:52.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:52.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:52.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:52.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:52.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:52.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:52.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:36:52.783 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:36:52.783 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:36:52.783 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:36:57.785 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:36:57.786 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:36:57.787 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:36:57.788 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:36:57.788 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:36:57.788 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:36:57.795 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:36:57.795 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:36:57.795 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:36:57.796 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:36:57.796 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:36:57.798 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:36:57.799 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:36:57.799 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:36:57.799 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:36:57.800 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:36:57.800 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:36:57.801 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:36:57.801 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:36:57.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:36:57.802 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:36:57.802 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:36:57.802 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:36:57.802 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:36:57.802 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:36:57.802 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:36:57.802 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:36:57.802 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:36:57.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:36:57.804 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:36:57.805 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:36:57.805 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:36:57.805 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:36:57.805 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:36:57.805 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:36:57.805 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:36:57.805 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:36:57.805 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:36:57.808 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:36:57.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:36:57.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:36:57.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:36:57.808 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:36:57.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:36:57.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:36:57.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:36:57.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:36:57.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:57.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:57.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:36:57.809 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:36:57.809 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:36:57.809 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:57.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:57.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:36:57.814 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:36:58.298 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:36:58.340 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:36:58.343 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:36:58.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:58.345 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:36:58.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:36:58.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:36:58.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:36:58.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:58.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:58.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:58.366 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:36:58.366 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:36:58.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:36:58.400 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:36:58.401 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:36:58.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:58.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:36:58.774 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:36:58.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:36:58.814 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:36:58.814 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:36:58.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:36:59.252 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:36:59.730 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:36:59.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:36:59.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:36:59.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:36:59.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:37:00.208 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:37:00.685 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:37:00.814 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:37:00.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:37:00.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:37:00.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:37:01.163 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:37:01.640 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:37:01.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:37:01.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:37:01.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:37:01.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:37:02.118 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:37:02.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:02.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:02.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:02.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:02.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:02.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:02.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:37:02.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:02.475 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:02.475 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:02.475 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:37:02.475 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:37:02.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:02.526 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:02.526 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:02.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:02.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:02.596 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:37:02.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:37:02.817 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:37:02.818 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:37:02.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:37:03.074 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:37:03.552 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:37:04.030 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:37:04.508 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:37:04.986 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:37:05.463 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:37:05.941 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:37:06.419 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:37:06.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:06.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:06.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:06.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:06.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:06.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:06.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:37:06.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:06.797 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:06.797 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:06.797 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:37:06.797 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:37:06.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:06.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:06.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:06.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:06.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:06.896 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:37:07.373 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:37:07.852 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:37:08.330 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:37:08.806 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:37:09.284 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:37:09.762 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:37:10.239 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:37:10.718 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:37:11.196 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:37:11.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:11.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:11.292 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:11.292 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:11.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:11.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:11.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:37:11.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:11.312 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:11.312 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:11.312 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:37:11.312 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:37:11.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:11.361 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:11.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:11.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:11.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:11.674 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:37:12.151 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:37:12.629 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:37:13.107 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:37:13.585 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:37:14.063 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:37:14.541 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:37:15.019 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:37:15.498 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:37:15.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:15.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:15.610 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:15.610 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:15.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:15.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:15.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:37:15.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:15.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:15.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:15.631 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:37:15.631 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:37:15.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:15.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:15.682 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:15.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:15.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:15.976 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:37:16.454 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:37:16.932 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:37:17.410 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:37:17.888 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:37:18.366 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:37:18.844 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:37:19.322 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:37:19.800 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:37:20.278 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:37:20.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:20.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:20.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:20.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:20.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:20.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:20.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:37:20.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:20.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:20.313 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:20.313 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:37:20.313 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:37:20.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:20.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:20.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:20.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:20.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:20.756 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:37:21.234 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:37:21.712 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:37:22.190 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:37:22.668 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:37:23.146 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:37:23.624 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:37:24.102 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:37:24.580 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:37:24.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:24.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:24.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:24.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:24.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:24.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:24.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:37:24.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:24.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:24.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:24.766 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:37:24.766 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:37:24.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:24.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:24.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:24.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:24.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:25.058 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:37:25.536 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:37:26.014 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 01:37:26.492 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 01:37:26.970 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 01:37:27.448 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 01:37:27.926 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 01:37:28.405 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 01:37:28.883 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 01:37:29.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:29.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:29.192 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:29.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:29.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:29.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:29.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:37:29.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:29.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:29.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:29.212 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:37:29.212 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:37:29.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:37:29.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:29.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:29.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:29.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:29.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:29.361 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 01:37:29.839 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 01:37:30.318 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 01:37:30.796 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 01:37:31.274 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 01:37:31.752 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 01:37:32.230 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 01:37:32.709 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 01:37:33.187 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 01:37:33.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:33.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:33.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:33.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:33.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:33.656 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:33.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:37:33.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:33.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:33.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:33.658 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:37:33.658 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:37:33.664 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 01:37:33.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:33.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:33.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:33.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:33.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:34.142 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 01:37:34.618 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 01:37:35.095 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 01:37:35.573 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 01:37:36.052 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 01:37:36.530 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 01:37:37.008 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 01:37:37.486 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 01:37:37.965 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 01:37:38.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:38.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:38.083 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:38.083 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:38.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:38.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:38.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:37:38.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:38.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:38.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:38.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:37:38.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:37:38.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:37:38.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:38.158 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:38.159 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:38.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:38.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:38.440 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 01:37:38.918 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 01:37:39.396 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 01:37:39.874 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 01:37:40.352 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 01:37:40.830 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 01:37:41.309 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 01:37:41.787 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 01:37:42.265 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 01:37:42.740 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 01:37:43.218 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 01:37:43.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:43.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:43.387 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:43.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:43.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:43.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:43.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:37:43.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:43.406 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:43.406 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:43.406 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:37:43.406 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:37:43.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:43.461 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:43.461 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:43.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:43.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:43.696 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 01:37:44.174 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 01:37:44.653 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 01:37:45.131 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 01:37:45.609 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 01:37:46.088 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 01:37:46.566 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 01:37:47.044 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 01:37:47.522 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 01:37:48.001 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 01:37:48.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:48.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:48.258 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:48.258 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:48.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:48.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:48.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:37:48.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:48.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:48.279 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:48.279 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:37:48.280 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:37:48.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:48.336 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:48.336 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:48.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:48.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:48.479 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 01:37:48.958 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 01:37:49.435 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 01:37:49.913 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 01:37:50.392 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 01:37:50.870 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 01:37:51.349 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 01:37:51.827 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 01:37:52.305 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 01:37:52.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:52.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:52.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:52.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:52.712 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:52.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:52.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:37:52.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:52.714 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:52.714 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:52.714 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:37:52.714 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:37:52.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:52.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:52.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:52.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:52.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:52.782 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 01:37:53.260 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 01:37:53.738 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 01:37:54.216 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 01:37:54.694 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 01:37:55.172 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 01:37:55.650 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 01:37:56.129 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 01:37:56.607 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 01:37:56.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:56.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:56.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:56.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:56.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:37:56.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:37:56.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:37:56.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:56.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:56.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:56.916 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:37:56.916 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:37:56.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:37:56.965 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:37:56.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:37:56.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:56.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:37:57.084 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 01:37:57.562 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 01:37:58.040 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 01:37:58.518 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-05 01:37:58.996 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-05 01:37:59.474 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-05 01:37:59.952 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-05 01:38:00.430 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-05 01:38:00.909 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-05 01:38:01.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:01.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:01.219 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:01.219 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:01.219 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=13533 tn=1 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:38:01.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:01.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:01.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:01.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:01.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:01.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:01.239 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:01.239 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:01.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:01.294 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:01.294 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:01.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:01.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:01.386 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-05 01:38:01.864 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-05 01:38:02.342 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-05 01:38:02.819 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-05 01:38:03.297 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-05 01:38:03.774 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-05 01:38:04.252 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-05 01:38:04.730 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-05 01:38:05.208 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-05 01:38:05.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:05.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:05.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:05.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:05.556 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:05.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:05.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:05.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:05.558 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:05.558 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:05.558 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:05.558 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:05.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:05.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:05.612 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:05.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:05.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:05.685 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-05 01:38:06.163 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-05 01:38:06.641 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-05 01:38:07.118 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-05 01:38:07.596 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-05 01:38:08.073 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-05 01:38:08.550 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-05 01:38:09.028 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-05 01:38:09.506 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-05 01:38:09.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:09.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:09.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:09.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:09.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:09.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:09.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:09.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:09.878 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:09.878 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:09.878 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:09.878 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:09.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:09.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:09.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:09.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:09.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:09.983 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-05 01:38:10.462 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-05 01:38:10.940 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-05 01:38:11.418 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-05 01:38:11.897 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-05 01:38:12.374 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-05 01:38:12.852 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-05 01:38:13.331 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-05 01:38:13.808 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-05 01:38:14.286 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-05 01:38:14.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:14.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:14.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:14.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:14.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:14.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:14.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:14.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:14.354 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:14.354 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:14.354 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:14.354 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:14.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:14.407 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:14.408 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:14.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:14.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:14.764 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-05 01:38:15.242 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-05 01:38:15.720 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-05 01:38:16.199 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-05 01:38:16.677 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-05 01:38:17.154 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-05 01:38:17.632 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-05 01:38:18.110 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-05 01:38:18.588 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-05 01:38:18.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:18.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:18.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:18.656 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:18.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:18.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:18.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:18.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:18.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:18.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:18.668 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:18.668 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:18.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:18.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:18.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:18.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:18.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:19.066 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-05 01:38:19.544 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-05 01:38:20.022 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-05 01:38:20.500 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-05 01:38:20.978 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-05 01:38:21.456 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-05 01:38:21.934 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-05 01:38:22.412 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-05 01:38:22.890 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-05 01:38:22.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:22.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:22.977 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:22.977 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:22.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:22.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:22.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:22.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:22.994 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:22.994 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:22.994 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:22.994 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:23.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:23.041 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:23.042 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:23.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:23.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:23.368 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-05 01:38:23.845 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-05 01:38:24.324 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-05 01:38:24.801 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-05 01:38:25.279 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-05 01:38:25.757 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-05 01:38:26.235 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-05 01:38:26.712 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-05 01:38:27.190 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-05 01:38:27.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:27.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:27.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:27.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:27.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:38:27.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:38:27.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:38:27.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:38:27.313 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:38:27.314 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:38:27.314 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:38:27.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:38:27.314 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:38:27.314 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:38:27.314 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:38:27.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19102 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:38:27.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19102 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:38:27.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19102 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:38:27.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19102 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:38:27.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19102 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:38:27.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19102 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:38:27.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19102 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:38:32.313 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:38:32.314 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:38:32.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:38:32.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:38:32.316 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:38:32.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:38:32.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:38:32.324 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:38:32.325 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:38:32.325 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:38:32.325 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:38:32.328 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:38:32.328 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:38:32.328 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:38:32.329 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:38:32.329 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:38:32.329 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:38:32.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:38:32.330 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:38:32.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:38:32.331 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:38:32.331 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:38:32.331 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:38:32.331 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:38:32.331 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:38:32.332 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:38:32.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:38:32.332 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:38:32.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:38:32.333 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:38:32.333 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:38:32.334 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:38:32.334 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:38:32.334 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:38:32.334 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:38:32.334 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:38:32.334 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:38:32.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:38:32.336 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:38:32.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:38:32.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:38:32.337 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:38:32.337 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:38:32.337 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:38:32.337 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:32.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:38:32.339 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:32.339 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:38:32.339 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:38:32.339 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:32.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:37.343 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:38:37.343 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:38:37.344 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:38:37.346 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:38:37.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:38:37.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:38:37.356 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:38:37.358 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:38:37.358 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:38:37.359 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:38:37.359 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:38:37.363 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:38:37.363 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:38:37.364 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:38:37.364 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:38:37.364 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:38:37.365 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:38:37.365 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:38:37.365 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:38:37.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:38:37.366 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:38:37.366 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:38:37.366 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:38:37.366 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:38:37.367 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:38:37.367 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:38:37.367 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:38:37.367 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:38:37.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:38:37.369 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:38:37.369 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:38:37.369 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:38:37.369 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:38:37.369 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:38:37.369 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:38:37.369 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:38:37.370 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:38:37.370 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:38:37.372 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:38:37.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:38:37.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:38:37.373 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:38:37.373 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:38:37.373 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:38:37.374 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:38:37.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:38:37.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:38:37.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:38:37.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:38:37.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:38:37.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:38:37.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:38:37.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:38:37.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:38:37.378 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:38:37.863 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:38:37.909 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:38:37.911 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:38:37.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:37.914 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:38:37.939 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:37.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:37.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:37.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:37.945 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:37.945 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:37.945 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:37.945 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:37.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:37.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:37.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:37.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:37.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:38.339 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:38:38.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:38:38.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:38:38.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:38:38.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:38:38.816 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:38:39.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:39.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:39.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:39.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:39.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:39.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:39.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:39.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:39.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:39.042 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:39.042 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:39.042 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:39.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:39.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:39.096 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:39.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:39.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:39.294 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:38:39.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:38:39.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:38:39.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:38:39.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:38:39.772 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:38:40.249 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:38:40.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:38:40.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:38:40.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:38:40.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:38:40.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:40.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:40.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:40.474 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:40.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:40.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:40.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:40.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:40.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:40.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:40.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:40.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:40.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:40.541 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:40.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:40.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:40.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:40.726 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:38:41.204 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:38:41.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:38:41.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:38:41.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:38:41.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:38:41.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:41.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:41.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:41.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:41.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:41.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:41.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:41.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:41.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:41.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:41.656 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:41.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:41.682 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:38:41.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:41.706 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:41.706 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:41.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:41.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:42.160 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:38:42.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:38:42.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:38:42.384 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:38:42.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:38:42.638 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:38:43.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:43.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:43.097 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:43.097 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:43.097 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=1223 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:38:43.097 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=1223 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:38:43.110 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:43.111 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:43.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:43.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:43.114 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:43.114 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:43.114 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:43.114 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:43.116 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:38:43.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:43.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:43.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:43.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:43.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:43.594 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:38:44.071 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:38:44.549 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:38:44.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:44.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:44.679 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:44.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:44.680 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=1560 tn=2 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:38:44.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:44.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:44.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:44.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:44.694 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:44.694 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:44.694 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:44.694 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:44.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:44.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:44.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:44.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:44.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:45.027 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:38:45.505 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:38:45.983 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:38:46.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:46.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:46.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:46.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:46.218 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:46.218 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:46.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:46.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:46.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:46.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:46.221 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:46.221 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:46.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:46.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:46.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:46.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:46.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:46.460 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:38:46.938 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:38:47.416 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:38:47.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:47.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:47.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:47.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:47.741 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:47.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:47.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:47.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:47.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:47.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:47.744 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:47.744 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:47.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:38:47.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:47.799 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:47.799 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:47.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:47.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:47.894 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:38:48.372 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:38:48.850 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:38:49.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:49.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:49.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:49.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:49.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:49.262 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:49.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:49.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:49.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:49.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:49.265 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:49.265 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:49.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:49.314 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:49.315 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:49.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:49.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:49.327 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:38:49.805 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:38:50.283 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:38:50.761 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:38:50.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:50.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:50.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:50.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:50.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:50.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:50.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:50.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:50.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:50.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:50.785 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:50.786 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:50.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:38:50.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:50.839 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:50.839 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:50.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:50.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:51.239 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:38:51.717 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:38:52.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:52.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:52.167 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:52.167 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:52.184 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:52.184 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:52.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:52.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:52.186 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:52.187 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:52.187 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:52.187 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:52.194 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:38:52.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:52.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:52.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:52.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:52.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:52.672 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:38:53.150 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:38:53.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:53.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:53.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:53.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:53.624 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:38:53.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:53.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:53.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:53.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:53.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:53.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:53.630 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:53.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:53.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:53.672 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:53.672 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:53.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:53.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:54.095 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:38:54.573 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:38:55.052 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:38:55.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:55.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:55.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:55.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:55.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:55.165 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:55.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:55.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:55.167 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:55.168 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:55.168 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:55.168 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:55.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:55.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:55.218 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:55.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:55.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:55.529 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:38:56.006 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:38:56.484 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:38:56.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:56.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:56.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:56.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:56.662 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:56.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:56.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:56.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:56.665 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:56.665 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:56.665 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:56.665 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:56.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:56.723 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:56.723 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:56.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:56.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:56.962 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:38:57.440 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:38:57.918 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:38:58.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:58.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:58.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:58.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:58.116 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:58.116 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:58.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:58.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:58.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:58.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:58.119 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:58.119 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:58.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:58.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:58.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:58.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:58.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:58.395 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:38:58.874 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:38:59.351 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:38:59.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:59.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:59.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:59.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:59.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:38:59.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:38:59.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:38:59.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:59.570 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:59.570 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:59.570 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:38:59.570 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:38:59.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:38:59.618 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:38:59.618 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:38:59.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:59.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:38:59.829 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:39:00.306 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:39:00.784 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:39:00.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:00.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:00.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:00.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:01.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:01.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:01.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:01.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:01.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:01.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:01.010 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:01.010 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:01.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:01.059 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:01.059 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:01.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:01.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:01.259 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:39:01.732 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:39:02.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:02.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:02.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:02.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:02.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:02.152 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:02.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:02.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:02.156 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:02.156 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:02.156 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:02.156 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:02.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:02.210 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:39:02.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:02.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:02.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:02.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:02.688 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:39:03.166 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:39:03.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:03.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:03.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:03.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:03.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:03.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:03.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:03.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:03.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:03.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:03.602 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:03.602 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:03.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:03.644 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:39:03.650 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:03.650 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:03.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:03.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:04.122 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:39:04.600 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:39:05.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:05.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:05.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:05.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:05.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:05.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:05.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:05.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:05.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:05.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:05.054 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:05.054 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:05.077 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:39:05.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:05.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:05.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:05.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:05.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:05.554 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 01:39:06.032 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 01:39:06.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:06.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:06.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:06.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:06.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:06.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:06.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:06.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:06.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:39:06.495 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:39:06.495 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:39:06.495 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:39:06.495 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:39:06.495 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:39:06.495 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:06.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:11.499 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:39:11.499 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:39:11.499 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:39:11.499 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:39:11.499 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:39:11.499 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:39:11.507 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:39:11.509 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:39:11.509 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:39:11.510 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:39:11.510 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:39:11.514 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:39:11.514 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:39:11.514 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:39:11.514 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:39:11.514 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:39:11.514 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:39:11.515 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:39:11.515 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:39:11.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:11.517 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:39:11.517 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:39:11.517 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:39:11.518 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:39:11.518 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:39:11.518 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:39:11.518 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:39:11.518 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:39:11.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:11.520 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:39:11.520 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:39:11.520 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:39:11.520 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:39:11.521 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:39:11.521 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:39:11.521 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:39:11.521 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:39:11.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:11.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:11.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:11.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:11.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:11.525 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:39:11.525 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:39:11.525 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:39:11.525 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:39:11.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:11.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:11.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:11.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:39:11.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:11.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:11.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:11.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:11.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:11.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:11.530 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:39:12.014 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:39:12.055 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:39:12.056 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:39:12.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:12.058 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:39:12.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:12.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:12.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:12.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:12.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:12.085 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:12.085 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:12.085 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:12.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:39:12.116 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:12.116 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:12.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:12.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:12.491 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:39:12.528 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:12.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:12.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:12.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:12.968 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:39:13.446 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:39:13.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:13.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:13.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:13.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:13.924 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:39:14.402 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:39:14.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:14.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:14.531 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:14.537 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:14.880 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:39:15.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:15.358 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:39:15.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:15.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:15.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:15.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:15.836 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:39:15.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:15.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:15.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:15.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:15.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:15.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:15.909 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:15.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:15.910 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:15.910 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:15.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:39:15.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:15.932 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:15.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:15.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:16.314 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:39:16.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:16.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:16.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:16.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:16.792 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:39:17.270 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:39:17.748 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:39:18.227 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:39:18.705 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:39:18.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:19.183 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:39:19.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:19.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:19.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:19.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:19.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:19.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:19.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:19.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:19.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:19.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:19.343 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:19.343 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:19.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:39:19.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:19.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:19.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:19.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:19.660 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:39:20.138 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:39:20.616 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:39:21.094 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:39:21.572 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:39:22.050 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:39:22.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:22.528 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:39:22.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:22.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:22.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:22.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:22.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:22.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:22.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:22.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:22.976 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:22.976 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:22.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:39:23.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:23.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:23.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:23.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:23.006 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:39:23.483 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:39:23.962 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:39:24.440 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:39:24.918 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:39:25.396 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:39:25.874 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:39:26.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:26.352 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:39:26.827 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:39:26.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:26.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:26.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:26.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:26.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:26.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:26.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:26.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:26.891 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:26.891 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:26.891 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:26.891 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:26.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:39:26.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:26.939 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:26.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:26.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:27.305 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:39:27.783 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:39:28.261 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:39:28.739 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:39:29.217 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:39:29.695 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:39:30.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:30.173 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:39:30.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:30.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:30.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:30.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:30.613 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=4075 tn=2 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:30.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:30.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:30.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:30.614 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:30.614 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:30.614 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:30.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:39:30.645 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:30.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:30.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:30.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:30.651 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:39:31.129 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:39:31.606 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:39:32.083 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:39:32.561 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:39:33.039 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:39:33.517 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:39:33.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:33.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:33.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:33.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:33.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:33.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:33.978 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:33.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:33.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:33.981 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:33.981 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:33.981 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:33.981 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:33.994 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:39:34.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:39:34.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:34.028 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:34.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:34.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:34.472 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:39:34.951 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:39:35.428 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:39:35.907 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:39:36.384 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:39:36.862 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:39:37.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:37.340 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:39:37.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:37.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:37.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:37.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:37.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:37.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:37.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:37.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:37.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:37.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:37.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:39:37.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:37.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:37.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:37.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:37.819 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:39:38.296 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:39:38.773 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:39:39.251 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:39:39.729 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 01:39:40.207 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 01:39:40.684 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 01:39:40.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:41.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:41.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:41.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:41.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:41.087 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:41.087 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:41.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:41.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:41.087 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:39:41.087 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:39:41.087 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:39:41.087 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:39:41.087 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:39:41.087 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:39:41.088 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:39:41.088 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6311 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:41.088 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6311 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:41.088 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6311 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:41.088 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6311 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:46.090 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:39:46.091 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:39:46.092 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:39:46.093 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:39:46.093 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:39:46.094 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:39:46.096 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:39:46.097 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:39:46.097 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:39:46.097 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:39:46.097 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:39:46.097 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:39:46.098 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:39:46.098 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:39:46.098 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:39:46.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:39:46.098 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:39:46.098 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:39:46.098 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:39:46.098 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:46.100 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:39:46.100 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:39:46.100 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:39:46.100 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:39:46.100 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:39:46.100 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:39:46.100 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:39:46.100 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:39:46.100 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:46.102 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:39:46.102 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:39:46.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:39:46.102 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:39:46.102 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:39:46.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:39:46.102 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:39:46.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:39:46.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:46.106 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:39:46.106 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:39:46.106 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:39:46.106 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:46.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:39:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:39:46.111 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:39:46.595 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:39:46.640 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:39:46.643 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:39:46.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:46.645 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:39:46.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:46.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:46.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:46.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:46.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:46.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:46.679 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:46.679 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:46.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:39:46.697 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:46.698 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:46.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:46.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:47.072 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:39:47.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:47.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:47.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:47.115 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:47.550 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:39:48.028 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:39:48.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:48.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:48.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:48.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:48.505 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:39:48.983 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:39:49.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:49.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:49.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:49.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:49.461 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:39:49.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:49.939 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:39:50.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:50.112 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:50.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:50.118 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:50.418 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:39:50.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:50.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:50.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:50.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:50.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:50.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:50.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:50.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:50.494 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:50.494 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:50.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:39:50.512 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:50.513 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:50.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:50.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:50.896 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:39:51.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:39:51.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:39:51.114 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:39:51.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:39:51.373 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:39:51.851 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:39:52.329 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:39:52.807 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:39:53.285 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:39:53.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:53.763 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:39:54.241 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:39:54.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:54.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:54.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:54.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:54.390 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=1768 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:54.391 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=1768 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:54.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:54.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:54.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:54.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:54.391 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:54.391 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:54.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:39:54.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:54.428 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:54.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:54.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:54.719 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:39:55.197 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:39:55.675 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:39:56.153 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:39:56.630 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:39:57.108 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:39:57.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:57.586 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:39:58.063 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:39:58.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:58.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:58.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:58.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:58.286 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=2600 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:39:58.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:58.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:58.287 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:58.287 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:58.287 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:58.287 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:58.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:39:58.301 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:58.301 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:58.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:58.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:58.541 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:39:58.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:59.019 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:39:59.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:39:59.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:59.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:59.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:59.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:39:59.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:39:59.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:39:59.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:59.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:59.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:59.283 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:39:59.283 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:39:59.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:39:59.331 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:39:59.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:39:59.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:59.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:39:59.497 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:39:59.976 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:40:00.454 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:40:00.932 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:40:01.410 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:40:01.889 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:40:02.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:02.367 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:40:02.844 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:40:02.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:02.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:02.917 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:02.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:02.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:40:02.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:02.918 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:02.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:02.918 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:40:02.918 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:40:02.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:40:02.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:02.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:02.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:02.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:03.321 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:40:03.799 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:40:04.278 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:40:04.756 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:40:05.235 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:40:05.713 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:40:05.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:06.191 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:40:06.669 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:40:06.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:06.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:06.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:06.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:06.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:40:06.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:06.821 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:06.822 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:06.822 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:40:06.822 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:40:06.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:40:06.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:06.856 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:06.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:06.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:07.147 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:40:07.626 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:40:08.104 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:40:08.582 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:40:09.060 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:40:09.538 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:40:09.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:10.017 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:40:10.494 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:40:10.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:10.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:10.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:10.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:10.718 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=5252 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:40:10.718 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=5252 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:40:10.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:40:10.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:10.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:10.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:10.719 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:40:10.719 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:40:10.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:40:10.731 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:10.731 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:10.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:10.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:10.972 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:40:11.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:11.450 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:40:11.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:11.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:11.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:11.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:11.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:11.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:11.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:40:11.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:11.711 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:11.711 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:11.711 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:40:11.711 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:40:11.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:40:11.764 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:11.764 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:11.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:11.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:11.928 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:40:12.406 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:40:12.884 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:40:13.361 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:40:13.840 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:40:14.318 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 01:40:14.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:14.795 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 01:40:15.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:15.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:15.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:15.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:15.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:40:15.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:15.238 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:15.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:15.239 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:40:15.239 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:40:15.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:40:15.269 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:15.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:15.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:15.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:15.272 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 01:40:15.749 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 01:40:16.227 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 01:40:16.705 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 01:40:17.183 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 01:40:17.661 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 01:40:18.139 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 01:40:18.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:18.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:18.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:18.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:18.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:18.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:40:18.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:18.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:18.581 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:18.581 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:40:18.581 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:40:18.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:40:18.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:18.612 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:18.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:18.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:18.616 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 01:40:19.093 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 01:40:19.571 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 01:40:20.049 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 01:40:20.526 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 01:40:21.004 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 01:40:21.482 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 01:40:21.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:21.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:21.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:21.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:21.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:21.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:40:21.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:21.923 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:21.923 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:21.923 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:40:21.923 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:40:21.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:40:21.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:21.955 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:21.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:21.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:21.958 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 01:40:22.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:22.436 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 01:40:22.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:22.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:22.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:22.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:22.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:22.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:22.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:40:22.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:22.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:22.892 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:22.892 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:40:22.892 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:40:22.913 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 01:40:22.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:40:22.943 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:22.944 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:22.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:22.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:23.390 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 01:40:23.868 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 01:40:24.345 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 01:40:24.822 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 01:40:25.301 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 01:40:25.779 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 01:40:26.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:26.257 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 01:40:26.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:26.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:26.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:26.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:26.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:40:26.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:26.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:26.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:26.653 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:40:26.653 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:40:26.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:40:26.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:26.680 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:26.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:26.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:26.734 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 01:40:27.212 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 01:40:27.689 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 01:40:28.167 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 01:40:28.646 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 01:40:29.124 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 01:40:29.601 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 01:40:29.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:29.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:29.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:29.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:29.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:29.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:40:29.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:29.997 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:29.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:29.997 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:40:29.997 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:40:30.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:40:30.023 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:30.023 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:30.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:30.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:30.079 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 01:40:30.556 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 01:40:31.035 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 01:40:31.513 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 01:40:31.990 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 01:40:32.468 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 01:40:32.946 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 01:40:33.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:33.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:33.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:33.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:33.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:33.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:40:33.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:33.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:33.344 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:33.344 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:40:33.344 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:40:33.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:40:33.367 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:33.367 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:33.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:33.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:33.424 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 01:40:33.902 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 01:40:34.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:34.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:34.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:34.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:34.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:34.305 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:34.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:34.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:34.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:34.305 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:40:34.305 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:40:34.305 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:40:34.306 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:40:34.306 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:40:34.306 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:40:34.306 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:40:39.308 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:40:39.308 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:40:39.310 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:40:39.311 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:40:39.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:40:39.313 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:40:39.321 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:40:39.322 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:40:39.323 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:40:39.323 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:40:39.323 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:40:39.329 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:40:39.329 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:40:39.329 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:40:39.329 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:40:39.330 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:40:39.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:40:39.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:40:39.330 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:40:39.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:39.334 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:40:39.334 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:40:39.334 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:40:39.335 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:40:39.335 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:40:39.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:40:39.335 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:40:39.335 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:40:39.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:39.339 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:40:39.339 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:40:39.339 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:40:39.339 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:40:39.339 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:40:39.339 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:40:39.339 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:40:39.339 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:40:39.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:39.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:39.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:39.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:39.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:39.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:39.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:39.344 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:40:39.344 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:40:39.344 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:40:39.344 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:40:39.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:39.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:39.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:39.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:40:39.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:39.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:39.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:39.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:39.349 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:40:39.833 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:40:39.881 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:40:39.884 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:40:39.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:39.886 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:40:39.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:39.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:39.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:40:39.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:39.896 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:39.896 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:39.897 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:40:39.897 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:40:40.310 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:40:40.347 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:40.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:40.350 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:40.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:40.786 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:40:41.259 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:40:41.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:41.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:41.350 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:41.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:41.729 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:40:42.202 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:40:42.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:42.349 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:42.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:42.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:42.681 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:40:43.156 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:40:43.350 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:43.350 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:43.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:43.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:43.634 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:40:44.106 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:40:44.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:44.351 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:44.352 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:44.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:44.577 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:40:45.048 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:40:45.519 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:40:45.989 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:40:46.460 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:40:46.935 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:40:47.407 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:40:47.881 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:40:48.356 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:40:48.704 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:48.704 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:48.708 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:48.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:48.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:48.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:48.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:40:48.711 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:40:48.711 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:40:48.711 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:40:48.711 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:40:48.711 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:40:48.711 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:40:53.713 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:40:53.713 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:40:53.713 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:40:53.713 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:40:53.713 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:40:53.713 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:40:53.721 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:40:53.721 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:40:53.721 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:40:53.721 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:40:53.721 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:40:53.723 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:40:53.723 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:40:53.724 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:40:53.724 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:40:53.724 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:40:53.724 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:40:53.724 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:40:53.724 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:40:53.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:53.726 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:40:53.726 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:40:53.726 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:40:53.726 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:40:53.726 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:40:53.726 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:40:53.726 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:40:53.727 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:40:53.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:53.728 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:40:53.729 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:40:53.729 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:40:53.729 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:40:53.729 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:40:53.729 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:40:53.729 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:40:53.729 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:40:53.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:53.732 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:40:53.732 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:40:53.732 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:40:53.733 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:53.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:53.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:53.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:53.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:40:53.737 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:40:54.222 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:40:54.265 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:40:54.267 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:40:54.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:40:54.270 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:40:54.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:40:54.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:40:54.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:40:54.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:40:54.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:40:54.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:40:54.274 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:40:54.274 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:40:54.694 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:40:54.737 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:54.737 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:54.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:54.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:55.168 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:40:55.646 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:40:55.737 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:55.738 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:55.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:55.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:56.118 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:40:56.589 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:40:56.738 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:56.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:56.740 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:56.746 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:57.065 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:40:57.540 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:40:57.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:57.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:57.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:57.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:58.010 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:40:58.479 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:40:58.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:40:58.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:40:58.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:40:58.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:40:58.949 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:40:59.425 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:40:59.897 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:41:00.369 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:41:00.839 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:41:01.309 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:41:01.780 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:41:02.251 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:41:02.722 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:41:03.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:03.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:03.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:03.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:03.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:03.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:03.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:03.080 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:03.080 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:03.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:03.080 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:41:03.081 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:41:03.081 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:41:03.081 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2017 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:03.081 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2017 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:03.081 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2017 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:03.081 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2017 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:03.081 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2017 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:03.082 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2017 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:03.082 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:03.082 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:03.082 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:03.082 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:03.082 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:03.082 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:03.082 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:03.082 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:08.083 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:41:08.083 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:41:08.083 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:08.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:08.083 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:08.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:08.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:08.086 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:41:08.086 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:08.086 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:41:08.086 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:41:08.088 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:41:08.088 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:41:08.089 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:41:08.089 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:08.089 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:08.090 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:41:08.090 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:41:08.090 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:41:08.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:08.091 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:41:08.091 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:41:08.091 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:41:08.091 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:08.091 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:08.091 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:41:08.091 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:41:08.091 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:41:08.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:08.093 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:41:08.093 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:41:08.093 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:41:08.093 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:08.093 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:08.093 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:41:08.093 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:41:08.093 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:41:08.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:08.096 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:41:08.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:41:08.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:41:08.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:41:08.096 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:41:08.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:41:08.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:41:08.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:41:08.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:41:08.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:08.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:08.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:08.096 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:41:08.097 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:41:08.097 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:41:08.097 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:08.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:08.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:08.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:08.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:08.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:08.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:08.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:08.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:08.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:08.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:08.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:08.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:08.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:08.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:08.102 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:41:08.583 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:41:08.625 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:41:08.627 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:41:08.630 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:41:08.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:08.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:08.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:08.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:09.060 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:41:09.100 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:09.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:09.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:09.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:09.542 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:41:09.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:09.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:09.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:09.637 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:09.637 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:10.021 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:41:10.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:10.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:10.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:10.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:10.492 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:41:10.970 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:41:11.102 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:11.102 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:11.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:11.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:11.444 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:41:11.914 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:41:12.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:12.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:12.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:12.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:12.384 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:41:12.854 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:41:13.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:13.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:13.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:13.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:13.331 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:41:13.806 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:41:14.275 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:41:14.746 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:41:15.221 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:41:15.693 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:41:16.165 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:41:16.634 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:41:17.110 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:41:17.582 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:41:18.053 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:41:18.523 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:41:19.001 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:41:19.479 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:41:19.956 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:41:20.435 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:41:20.912 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:41:21.390 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:41:21.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:21.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:21.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:21.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:21.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:21.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:21.493 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:21.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:21.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:21.494 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:41:21.494 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:41:21.494 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:41:21.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:21.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2880 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:21.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2880 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:21.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2880 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:21.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2880 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:21.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2880 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:21.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2880 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:21.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2880 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:21.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2880 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:26.497 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:41:26.497 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:41:26.499 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:26.499 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:26.500 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:26.501 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:26.503 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:26.504 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:41:26.504 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:26.504 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:41:26.504 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:41:26.504 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:41:26.505 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:41:26.505 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:41:26.505 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:26.505 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:26.505 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:41:26.505 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:41:26.505 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:41:26.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:26.505 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:41:26.505 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:41:26.506 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:41:26.506 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:26.506 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:26.506 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:41:26.506 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:41:26.506 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:41:26.506 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:26.507 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:41:26.507 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:41:26.507 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:41:26.507 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:26.507 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:26.507 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:41:26.507 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:41:26.507 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:41:26.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:26.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:41:26.510 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:41:26.510 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:41:26.510 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:26.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:26.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:26.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:26.514 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:41:26.997 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:41:27.037 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:41:27.040 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:41:27.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:27.042 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:41:27.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:27.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:27.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:27.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:27.047 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:27.048 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:27.048 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:27.048 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:27.474 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:41:27.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:27.512 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:27.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:27.515 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:27.951 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:41:28.087 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:41:28.429 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:41:28.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:28.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:28.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:28.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:28.633 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:41:28.905 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:41:29.154 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:41:29.382 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:41:29.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:29.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:29.514 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:29.517 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:29.860 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:41:30.338 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:41:30.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:30.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:30.514 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:30.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:30.816 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:41:31.175 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:41:31.294 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:41:31.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:31.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:31.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:31.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:31.682 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:41:31.771 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:41:32.209 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:41:32.249 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:41:32.726 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:41:32.739 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:41:33.204 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:41:33.682 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:41:34.160 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:41:34.637 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:41:34.762 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:41:35.115 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:41:35.593 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:41:36.070 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:41:36.547 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:41:36.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:36.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:36.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:36.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:36.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:36.777 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:36.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:36.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:36.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:36.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:36.780 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:41:36.780 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:41:36.780 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:36.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:41.781 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:41:41.781 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:41:41.782 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:41.783 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:41.784 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:41.784 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:41.791 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:41.792 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:41:41.792 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:41.793 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:41:41.793 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:41:41.796 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:41:41.796 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:41:41.797 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:41:41.797 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:41.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:41.797 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:41:41.798 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:41:41.798 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:41:41.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:41.798 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:41:41.799 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:41:41.799 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:41:41.799 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:41.799 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:41.799 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:41:41.799 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:41:41.799 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:41:41.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:41.801 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:41:41.801 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:41:41.801 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:41:41.801 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:41.801 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:41.801 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:41:41.801 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:41:41.801 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:41:41.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:41.804 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:41:41.804 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:41:41.804 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:41:41.804 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:41.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:41.809 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:41:42.292 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:41:42.334 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:41:42.336 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:41:42.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:42.339 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:41:42.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:42.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:42.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:42.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:42.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:42.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:42.358 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:42.358 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:42.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:42.394 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:42.394 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:42.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:42.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:42.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:42.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:42.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:42.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:42.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:42.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:42.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:42.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:42.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:42.483 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:42.483 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:42.483 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:42.483 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:42.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:42.530 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:42.530 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:42.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:42.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:42.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:42.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:42.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:42.715 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:42.715 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:42.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:42.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:42.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:42.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:42.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:42.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:42.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:42.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:42.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:42.768 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:41:42.770 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:42.770 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:42.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:42.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:42.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:42.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:42.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:42.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:42.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:42.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:42.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:42.984 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:42.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:42.995 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:42.995 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:42.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:42.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:42.997 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:42.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:42.997 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:42.997 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:43.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:43.001 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:43.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.012 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.012 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.012 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:43.012 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:43.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:43.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:43.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.085 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.085 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:43.085 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:43.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:43.094 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.094 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:43.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.110 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.110 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.110 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:43.110 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:43.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:43.146 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.146 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:43.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.163 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.163 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.163 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:43.163 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:43.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:43.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:43.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.221 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.221 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:43.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.223 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:43.223 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:43.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:43.238 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.238 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.241 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:41:43.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:43.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.262 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.262 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.262 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:43.262 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:43.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:43.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:43.290 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.303 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:43.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.317 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.317 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.317 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:43.317 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:43.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:43.329 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.329 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:43.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.353 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.353 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:43.353 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:43.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:43.380 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.381 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:43.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.405 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.405 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.405 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:43.405 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:43.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:43.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:43.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.564 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.564 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.564 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:43.564 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:43.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:43.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.615 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.711 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:41:43.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:43.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.797 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.797 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:43.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:43.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:43.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.807 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.807 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.807 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:43.807 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:43.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:43.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:43.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:43.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:43.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:43.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:43.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:43.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:43.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:44.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:44.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:44.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:44.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:44.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:44.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:44.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.065 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:44.065 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:44.065 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:44.065 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:44.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:44.084 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:44.084 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:44.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.188 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:41:44.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:44.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:44.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:44.313 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:44.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:44.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:44.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:44.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.333 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:44.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:44.333 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:44.333 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:44.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:44.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:44.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:44.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:44.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:44.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:44.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:44.577 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:44.577 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:44.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:44.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.578 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:44.578 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:44.578 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:44.578 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:44.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:44.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:44.617 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:44.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.665 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:41:44.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:44.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:44.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:44.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:44.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:44.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:44.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:44.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:44.840 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:44.840 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:44.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:44.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:44.842 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:44.842 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:44.842 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:44.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:44.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:44.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:44.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:44.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:44.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:44.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:44.862 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:44.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:44.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:44.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.863 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:44.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:44.863 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:44.863 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:44.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:44.908 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:44.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:44.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:44.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:45.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:45.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:45.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:45.098 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:45.098 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:45.107 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:45.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:45.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:45.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:45.110 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:45.110 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:45.110 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:45.110 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:45.110 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:41:45.110 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:41:45.110 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:41:45.110 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=710 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:45.110 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=710 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:45.110 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=710 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:45.110 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=710 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:45.110 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=710 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:45.110 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=710 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:41:50.110 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:41:50.110 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:41:50.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:50.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:50.114 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:50.114 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:50.121 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:50.122 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:41:50.122 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:50.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:41:50.123 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:41:50.126 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:41:50.127 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:41:50.127 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:41:50.127 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:50.128 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:50.128 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:41:50.128 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:41:50.129 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:41:50.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:50.129 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:41:50.129 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:41:50.129 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:41:50.130 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:50.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:50.130 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:41:50.130 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:41:50.130 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:41:50.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:50.132 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:41:50.132 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:41:50.132 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:41:50.132 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:50.132 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:50.132 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:41:50.132 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:41:50.132 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:41:50.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:50.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:41:50.136 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:41:50.136 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:41:50.136 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:50.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:50.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:50.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:50.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:50.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:50.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:50.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:50.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:50.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:50.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:50.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:50.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:50.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:50.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:41:50.141 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:41:50.624 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:41:50.667 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:41:50.669 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:41:50.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:50.671 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:41:50.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:50.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:50.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:41:50.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:50.699 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:50.700 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:50.700 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:41:50.700 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:41:50.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 01:41:50.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:41:50.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:41:50.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:50.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:41:50.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:41:51.102 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:41:51.139 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:51.139 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:51.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:51.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:51.580 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:41:52.058 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:41:52.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:52.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:52.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:52.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:52.535 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:41:52.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:41:52.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:41:52.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:52.789 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:52.789 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:52.789 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:52.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:52.790 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:52.790 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:52.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:52.790 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:41:52.790 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:41:52.790 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:41:57.795 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:41:57.795 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:41:57.795 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:57.795 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:57.795 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:57.796 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:57.802 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:57.803 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:41:57.803 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:57.803 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:41:57.804 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:41:57.807 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:41:57.807 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:41:57.808 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:41:57.808 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:57.808 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:41:57.809 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:41:57.809 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:41:57.810 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:41:57.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:41:57.810 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:41:57.811 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:41:57.811 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:41:57.811 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:57.811 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:41:57.811 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:41:57.812 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:41:57.812 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:41:57.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:41:57.813 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:41:57.814 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:41:57.814 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:41:57.814 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:41:57.814 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:41:57.814 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:41:57.814 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:41:57.814 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:41:57.814 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:41:57.817 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:41:57.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:41:57.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:41:57.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:41:57.817 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:41:57.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:41:57.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:41:57.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:41:57.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:41:57.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:57.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:57.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:57.818 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:41:57.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:57.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:57.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:57.818 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:41:57.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:57.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:57.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:57.818 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:41:57.818 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:41:57.818 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:41:57.818 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:41:57.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:57.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:57.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:57.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:41:57.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:57.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:41:57.819 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:41:57.819 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:41:57.819 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:41:57.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:41:57.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:41:57.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:02.823 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:42:02.823 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:42:02.824 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:02.826 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:02.827 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:02.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:02.834 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:02.834 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:42:02.834 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:02.835 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:42:02.835 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:42:02.836 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:42:02.836 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:42:02.837 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:42:02.837 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:02.837 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:02.837 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:42:02.838 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:42:02.838 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:42:02.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:02.838 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:42:02.838 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:42:02.839 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:42:02.839 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:02.839 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:02.839 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:42:02.839 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:42:02.839 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:42:02.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:02.841 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:42:02.841 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:42:02.841 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:42:02.841 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:02.841 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:02.841 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:42:02.841 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:42:02.841 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:42:02.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:02.843 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:42:02.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:42:02.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:42:02.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:42:02.843 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:42:02.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:42:02.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:42:02.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:42:02.844 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:42:02.844 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:42:02.844 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:02.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:02.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:02.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:02.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:02.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:02.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:02.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:02.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:02.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:02.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:02.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:02.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:02.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:02.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:02.849 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:42:03.330 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:42:03.372 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:42:03.374 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:42:03.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:42:03.376 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:42:03.803 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:42:03.847 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:03.847 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:03.847 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:03.850 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:04.286 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:42:04.768 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:42:04.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:04.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:04.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:04.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:05.248 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:42:05.727 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:42:05.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:05.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:05.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:05.852 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:06.208 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:42:06.689 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:42:06.851 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:06.852 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:06.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:06.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:07.170 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:42:07.652 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:42:07.853 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:07.854 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:07.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:07.855 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:08.133 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:42:08.613 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:42:08.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:08.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:08.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:08.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:08.865 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:08.865 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:08.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:08.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:08.865 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:42:08.865 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:42:08.865 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:42:08.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1280 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:08.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1280 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:08.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1280 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:08.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1280 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:08.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1280 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:08.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1280 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:08.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1280 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:13.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:42:13.868 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:42:13.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:13.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:13.870 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:13.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:13.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:13.878 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:42:13.879 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:13.879 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:42:13.879 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:42:13.881 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:42:13.882 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:42:13.882 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:42:13.882 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:13.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:13.883 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:42:13.883 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:42:13.883 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:42:13.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:13.884 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:42:13.884 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:42:13.884 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:42:13.884 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:13.884 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:13.884 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:42:13.884 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:42:13.885 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:42:13.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:13.886 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:42:13.886 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:42:13.886 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:42:13.886 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:13.886 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:13.886 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:42:13.886 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:42:13.887 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:42:13.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:13.889 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:42:13.889 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:42:13.889 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:42:13.890 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:13.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:13.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:13.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:13.894 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:42:14.378 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:42:14.415 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:42:14.417 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:42:14.419 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:42:14.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:42:14.851 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:42:14.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:14.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:14.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:14.897 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:15.321 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:42:15.803 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:42:15.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:15.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:15.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:15.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:16.285 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:42:16.765 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:42:16.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:16.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:16.897 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:16.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:17.246 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:42:17.728 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:42:17.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:17.897 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:17.899 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:17.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:18.209 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:42:18.690 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:42:18.898 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:18.898 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:18.900 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:18.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:19.172 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:42:19.430 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:19.430 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:19.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:19.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:19.434 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:19.434 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:19.434 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:19.434 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:19.434 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:42:19.434 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:42:19.434 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:42:19.434 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1180 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:19.434 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1180 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:19.434 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1180 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:19.434 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1180 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:19.434 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1180 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:19.434 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1180 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:24.434 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:42:24.434 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:42:24.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:24.437 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:24.438 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:24.438 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:24.446 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:24.446 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:42:24.446 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:24.446 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:42:24.446 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:42:24.447 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:42:24.448 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:42:24.448 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:42:24.448 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:24.448 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:24.448 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:42:24.449 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:42:24.449 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:42:24.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:24.449 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:42:24.449 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:42:24.449 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:42:24.449 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:24.450 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:24.450 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:42:24.450 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:42:24.450 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:42:24.450 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:24.451 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:42:24.451 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:42:24.451 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:42:24.451 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:24.451 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:24.451 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:42:24.451 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:42:24.451 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:42:24.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:24.453 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:42:24.453 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:42:24.453 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:42:24.453 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:42:24.453 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:42:24.453 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:42:24.453 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:42:24.453 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:42:24.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:42:24.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:24.454 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:42:24.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:24.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:24.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:24.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:24.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:24.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:24.454 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:42:24.454 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:42:24.454 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:42:24.454 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:42:24.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:24.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:24.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:24.455 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:24.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:24.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:24.455 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:42:24.455 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:42:24.455 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:42:24.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:24.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:24.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:29.458 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:42:29.459 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:42:29.460 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:29.461 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:29.463 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:29.463 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:29.483 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:29.485 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:42:29.485 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:29.486 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:42:29.486 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:42:29.490 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:42:29.490 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:42:29.491 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:42:29.491 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:29.491 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:29.492 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:42:29.492 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:42:29.493 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:42:29.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:29.494 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:42:29.494 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:42:29.494 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:42:29.494 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:29.495 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:29.495 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:42:29.495 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:42:29.495 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:42:29.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:29.497 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:42:29.497 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:42:29.497 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:42:29.497 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:29.497 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:29.497 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:42:29.498 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:42:29.498 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:42:29.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:29.500 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:42:29.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:29.501 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:42:29.501 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:42:29.501 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:42:29.501 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:29.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:29.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:29.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:29.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:29.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:29.506 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:42:29.989 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:42:30.028 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:42:30.030 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:42:30.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:42:30.033 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:42:30.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:42:30.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:42:30.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:42:30.466 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:42:30.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:30.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:30.506 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:30.510 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:30.944 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:42:31.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:42:31.039 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:42:31.040 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:42:31.040 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:42:31.040 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:42:31.422 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:42:31.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:31.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:31.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:31.511 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:31.901 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:42:32.376 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:42:32.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:32.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:32.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:32.511 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:32.851 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:42:33.323 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:42:33.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:33.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:33.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:33.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:33.795 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:42:34.266 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:42:34.509 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:34.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:34.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:34.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:34.741 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:42:35.219 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:42:35.697 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:42:36.175 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:42:36.649 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:42:37.119 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:42:37.589 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:42:38.059 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:42:38.530 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:42:39.007 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:42:39.485 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:42:39.962 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:42:40.440 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:42:40.918 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:42:41.396 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:42:41.873 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:42:42.350 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:42:42.828 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:42:43.305 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:42:43.783 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:42:44.261 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:42:44.738 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:42:44.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:42:44.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:42:44.879 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:44.880 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:44.880 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:44.880 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:44.882 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:44.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:44.882 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:44.883 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:42:44.883 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:42:44.883 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:42:44.883 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:44.883 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3297 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:44.883 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3297 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:44.883 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3297 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:44.883 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3297 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:44.883 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3297 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:44.883 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3297 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:44.883 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3297 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:49.883 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:42:49.883 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:42:49.884 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:49.886 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:49.887 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:49.887 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:49.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:49.901 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:42:49.901 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:49.901 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:42:49.901 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:42:49.903 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:42:49.904 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:42:49.904 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:42:49.904 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:49.904 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:49.904 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:42:49.905 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:42:49.905 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:42:49.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:49.906 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:42:49.906 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:42:49.906 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:42:49.906 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:49.906 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:42:49.906 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:49.906 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:42:49.906 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:42:49.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:49.907 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:42:49.907 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:42:49.907 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:42:49.907 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:42:49.907 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:42:49.907 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:49.907 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:42:49.907 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:42:49.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:49.909 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:42:49.909 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:42:49.909 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:42:49.910 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:42:49.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:42:49.914 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:42:50.397 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:42:50.434 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:42:50.437 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:42:50.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:42:50.439 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:42:50.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:42:50.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:42:50.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:42:50.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:42:50.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:42:50.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:42:50.474 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:42:50.474 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:42:50.489 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:42:50.492 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:42:50.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:42:50.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:42:50.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:42:50.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:42:50.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:42:50.874 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:42:50.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:50.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:50.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:50.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:51.352 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:42:51.830 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:42:51.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:51.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:51.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:51.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:52.308 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:42:52.786 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:42:52.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:52.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:52.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:52.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:53.263 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:42:53.741 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:42:53.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:53.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:53.917 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:53.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:54.219 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:42:54.697 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:42:54.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:54.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:54.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:54.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:55.174 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:42:55.652 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:42:56.130 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:42:56.608 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:42:57.086 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:42:57.563 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:42:58.041 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:42:58.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:42:58.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:42:58.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:42:58.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:42:58.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:42:58.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:42:58.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:42:58.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:42:58.519 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:42:58.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:42:58.521 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:42:58.522 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:42:58.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:42:58.522 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:42:58.522 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:42:58.522 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:42:58.522 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:58.523 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:58.523 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:58.523 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:58.523 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:58.523 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:58.523 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:58.523 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:58.523 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:58.523 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:58.523 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:58.523 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:58.524 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:42:58.524 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:03.521 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:43:03.522 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:43:03.523 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:43:03.524 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:43:03.524 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:43:03.525 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:43:03.529 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:43:03.530 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:43:03.530 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:43:03.530 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:43:03.530 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:43:03.532 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:43:03.532 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:43:03.533 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:43:03.533 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:43:03.533 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:43:03.533 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:43:03.533 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:43:03.533 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:43:03.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:03.535 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:43:03.535 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:43:03.535 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:43:03.535 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:43:03.535 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:43:03.535 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:43:03.535 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:43:03.535 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:43:03.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:03.537 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:43:03.537 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:43:03.537 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:43:03.537 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:43:03.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:43:03.538 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:43:03.538 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:43:03.538 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:43:03.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:03.540 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:43:03.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:43:03.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:43:03.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:43:03.540 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:43:03.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:43:03.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:43:03.541 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:43:03.541 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:43:03.541 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:03.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:03.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:03.546 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:43:04.030 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:43:04.068 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:43:04.069 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:43:04.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:43:04.070 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:43:04.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:43:04.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:43:04.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:43:04.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:04.099 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:43:04.099 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:43:04.099 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:43:04.099 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:43:04.122 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:43:04.126 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:43:04.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:43:04.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:43:04.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:43:04.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:04.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:04.507 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:43:04.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:04.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:04.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:04.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:04.984 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:43:05.462 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:43:05.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:05.545 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:05.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:05.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:05.940 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:43:06.418 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:43:06.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:06.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:06.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:06.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:06.895 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:43:07.373 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:43:07.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:07.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:07.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:07.551 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:07.851 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:43:08.329 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:43:08.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:08.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:08.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:08.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:08.806 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:43:09.281 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:43:09.756 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:43:10.234 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:43:10.711 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:43:11.188 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:43:11.666 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:43:12.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:43:12.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:12.142 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:43:12.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:43:12.144 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:43:12.150 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:12.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:12.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:12.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:12.152 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:43:12.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:43:12.152 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:43:12.152 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:43:12.152 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:43:12.152 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:43:12.152 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:43:17.154 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:43:17.154 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:43:17.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:43:17.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:43:17.156 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:43:17.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:43:17.164 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:43:17.164 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:43:17.164 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:43:17.165 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:43:17.165 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:43:17.167 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:43:17.168 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:43:17.168 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:43:17.169 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:43:17.169 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:43:17.170 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:43:17.170 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:43:17.170 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:43:17.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:17.171 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:43:17.171 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:43:17.172 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:43:17.172 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:43:17.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:43:17.173 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:43:17.173 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:43:17.173 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:43:17.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:17.174 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:43:17.174 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:43:17.174 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:43:17.174 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:43:17.175 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:43:17.175 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:43:17.175 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:43:17.175 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:43:17.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:17.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:17.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:17.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:17.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:17.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:17.179 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:43:17.179 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:43:17.179 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:43:17.179 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:43:17.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:17.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:17.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:17.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:43:17.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:17.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:17.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:17.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:17.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:17.184 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:43:17.667 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:43:17.714 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:43:17.716 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:43:17.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:43:17.719 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:43:17.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:43:17.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:43:17.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:43:17.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:17.752 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:43:17.752 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:43:17.752 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:43:17.752 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:43:17.759 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:43:17.763 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:43:17.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:43:17.773 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:43:17.773 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:43:17.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:17.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:18.144 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:43:18.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:18.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:18.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:18.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:18.622 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:43:19.100 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:43:19.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:19.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:19.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:19.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:19.578 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:43:20.056 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:43:20.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:20.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:20.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:20.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:20.534 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:43:21.011 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:43:21.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:21.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:21.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:21.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:21.490 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:43:21.967 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:43:22.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:22.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:22.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:22.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:22.445 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:43:22.921 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:43:23.399 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:43:23.877 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:43:24.355 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:43:24.832 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:43:25.310 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:43:25.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:43:25.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:25.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:43:25.779 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:43:25.788 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:43:25.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:43:25.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:43:25.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:43:25.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:25.795 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:43:25.795 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:43:25.795 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:43:25.795 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:43:25.834 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:43:25.838 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:43:25.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:43:25.852 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:43:25.852 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:43:25.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:25.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:26.265 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:43:26.743 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:43:27.222 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:43:27.700 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:43:28.179 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:43:28.657 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:43:29.135 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:43:29.613 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:43:30.091 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:43:30.568 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:43:31.046 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:43:31.524 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:43:32.002 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:43:32.480 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:43:32.958 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:43:33.437 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:43:33.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:43:33.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:33.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:43:33.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:43:33.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:33.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:33.869 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:33.869 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:33.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:43:33.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:43:33.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:43:33.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:43:33.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:43:33.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:43:33.872 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:43:33.872 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:33.872 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:33.872 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:33.872 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:33.872 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:33.872 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:33.872 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:33.872 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:33.872 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:33.872 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:33.872 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:33.873 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:33.873 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:33.873 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:38.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:43:38.873 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:43:38.874 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:43:38.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:43:38.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:43:38.876 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:43:38.882 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:43:38.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:43:38.882 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:43:38.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:43:38.882 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:43:38.883 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:43:38.884 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:43:38.884 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:43:38.884 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:43:38.884 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:43:38.885 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:43:38.885 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:43:38.885 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:43:38.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:38.886 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:43:38.886 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:43:38.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:43:38.886 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:43:38.886 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:43:38.886 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:43:38.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:43:38.886 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:43:38.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:38.888 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:43:38.888 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:43:38.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:43:38.888 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:43:38.888 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:43:38.888 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:43:38.888 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:43:38.888 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:43:38.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:38.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:43:38.891 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:43:38.891 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:43:38.891 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:38.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:38.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:38.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:38.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:43:38.896 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:43:39.379 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:43:39.423 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:43:39.425 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:43:39.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:43:39.425 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:43:39.446 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:43:39.446 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:43:39.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:43:39.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:39.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:43:39.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:43:39.452 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:43:39.452 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:43:39.470 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:43:39.474 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:43:39.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:43:39.486 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:43:39.486 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:43:39.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:39.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:39.855 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:43:39.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:39.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:39.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:39.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:40.333 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:43:40.812 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:43:40.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:40.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:40.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:40.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:41.290 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:43:41.767 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:43:41.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:41.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:41.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:41.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:42.246 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:43:42.724 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:43:42.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:42.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:42.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:42.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:43.202 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:43:43.680 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:43:43.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:43.897 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:43.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:43.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:44.158 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:43:44.636 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:43:45.114 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:43:45.592 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:43:46.070 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:43:46.548 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:43:47.026 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:43:47.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:43:47.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:47.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:43:47.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:43:47.504 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:43:47.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:43:47.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:43:47.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:43:47.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:47.510 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:43:47.510 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:43:47.510 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:43:47.510 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:43:47.550 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:43:47.555 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:43:47.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:43:47.570 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:43:47.570 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:43:47.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:47.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:47.981 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:43:48.460 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:43:48.938 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:43:49.416 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:43:49.894 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:43:50.372 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:43:50.850 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:43:51.328 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:43:51.807 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:43:52.285 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:43:52.763 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:43:53.241 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:43:53.719 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:43:54.197 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:43:54.675 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:43:55.153 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:43:55.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:43:55.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:43:55.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:43:55.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:43:55.585 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:43:55.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:43:55.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:43:55.585 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:43:55.588 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:43:55.588 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:43:55.588 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:43:55.588 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:43:55.588 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:43:55.588 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:43:55.588 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:43:55.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:00.589 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:44:00.589 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:44:00.590 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:44:00.591 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:44:00.592 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:44:00.592 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:44:00.598 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:44:00.599 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:44:00.599 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:44:00.600 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:44:00.600 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:44:00.602 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:44:00.602 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:44:00.603 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:44:00.603 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:44:00.603 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:44:00.603 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:44:00.604 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:44:00.604 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:44:00.604 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:00.604 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:44:00.605 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:44:00.605 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:44:00.605 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:44:00.605 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:44:00.605 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:44:00.605 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:44:00.605 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:44:00.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:00.607 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:44:00.607 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:44:00.607 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:44:00.607 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:44:00.607 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:44:00.607 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:44:00.607 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:44:00.607 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:44:00.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:00.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:00.611 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:00.611 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:00.611 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:00.611 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:00.611 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:44:00.611 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:44:00.611 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:44:00.611 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:44:00.611 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:00.611 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:00.611 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:00.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:44:00.611 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:00.611 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:00.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:00.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:00.616 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:44:01.098 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:44:01.141 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:44:01.142 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:44:01.143 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:44:01.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:01.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:44:01.169 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:44:01.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:44:01.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:01.176 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:44:01.176 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:44:01.176 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:44:01.176 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:44:01.190 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:44:01.194 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:44:01.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:01.202 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:44:01.202 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:44:01.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:01.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:01.575 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:44:01.614 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:01.615 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:01.617 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:01.621 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:02.053 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:44:02.531 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:44:02.615 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:02.616 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:02.618 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:02.622 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:03.010 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:44:03.487 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:44:03.616 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:03.616 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:03.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:03.623 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:03.965 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:44:04.443 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:44:04.617 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:04.617 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:04.621 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:04.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:04.922 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:44:05.400 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:44:05.618 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:05.618 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:05.622 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:05.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:05.878 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:44:06.356 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:44:06.834 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:44:07.313 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:44:07.791 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:44:08.268 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:44:08.743 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:44:09.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:09.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:09.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:44:09.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:44:09.221 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:44:09.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:44:09.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:44:09.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:44:09.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:09.229 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:44:09.229 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:44:09.229 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:44:09.229 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:44:09.268 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:44:09.271 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:44:09.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:09.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:44:09.283 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:44:09.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:09.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:09.699 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:44:10.177 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:44:10.656 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:44:11.134 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:44:11.612 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:44:12.090 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:44:12.568 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:44:13.047 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:44:13.525 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:44:14.003 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:44:14.481 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:44:14.959 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:44:15.437 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:44:15.915 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:44:16.394 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:44:16.872 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:44:17.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:17.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:17.289 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:44:17.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:44:17.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:17.297 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:17.297 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:17.297 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:17.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:44:17.297 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:44:17.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:44:17.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:44:17.297 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:44:17.297 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:44:17.297 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:44:17.297 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3562 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:17.297 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3562 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:17.297 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3562 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:17.298 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3562 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:17.298 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3562 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:17.298 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3562 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:17.298 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3562 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:22.300 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:44:22.301 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:44:22.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:44:22.303 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:44:22.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:44:22.305 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:44:22.311 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:44:22.312 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:44:22.312 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:44:22.312 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:44:22.312 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:44:22.313 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:44:22.314 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:44:22.314 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:44:22.314 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:44:22.315 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:44:22.315 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:44:22.315 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:44:22.315 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:44:22.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:22.316 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:44:22.316 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:44:22.316 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:44:22.316 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:44:22.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:44:22.316 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:44:22.316 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:44:22.316 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:44:22.317 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:22.318 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:44:22.318 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:44:22.318 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:44:22.318 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:44:22.318 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:44:22.318 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:44:22.318 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:44:22.318 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:44:22.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:22.320 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:44:22.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:44:22.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:44:22.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:44:22.320 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:44:22.321 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:44:22.321 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:44:22.321 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:22.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:44:22.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:22.326 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:44:22.809 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:44:22.849 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:44:22.851 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:44:22.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:22.853 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:44:22.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:44:22.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:44:22.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:44:22.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:22.879 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:44:22.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:44:22.879 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:44:22.879 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:44:22.901 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:44:22.904 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:44:22.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:22.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:44:22.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:44:22.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:22.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:23.286 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:44:23.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:23.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:23.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:23.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:23.761 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:44:24.239 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:44:24.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:24.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:24.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:24.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:24.717 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:44:25.195 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:44:25.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:25.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:25.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:25.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:25.673 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:44:26.150 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:44:26.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:26.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:26.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:26.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:26.622 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:44:27.100 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:44:27.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:27.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:27.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:27.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:27.578 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:44:28.052 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:44:28.531 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:44:29.004 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:44:29.482 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:44:29.960 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:44:30.438 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:44:30.916 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:44:30.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:30.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:30.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:44:30.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:44:30.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:44:30.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:44:30.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:44:30.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:30.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:44:30.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:44:30.942 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:44:30.942 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:44:30.960 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:44:30.963 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:44:30.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:30.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:44:30.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:44:30.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:30.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:31.393 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:44:31.871 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:44:32.348 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:44:32.820 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:44:33.292 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:44:33.769 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:44:34.248 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:44:34.725 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:44:35.203 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:44:35.681 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:44:36.158 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:44:36.636 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:44:37.114 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:44:37.592 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:44:38.069 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:44:38.546 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:44:38.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:38.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:38.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:44:38.980 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:44:38.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:44:38.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:44:38.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:44:38.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:38.999 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:44:38.999 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:44:38.999 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:44:38.999 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:44:39.014 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:44:39.016 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:44:39.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:39.024 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:44:39.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:44:39.025 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:44:39.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:39.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:39.501 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:44:39.979 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:44:40.457 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:44:40.934 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:44:41.412 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:44:41.890 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:44:42.368 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:44:42.846 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:44:43.323 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:44:43.801 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:44:44.279 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:44:44.757 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:44:45.235 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:44:45.713 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:44:46.192 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:44:46.669 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:44:47.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:47.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:47.031 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:44:47.031 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:44:47.031 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=5282 tn=2 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:47.031 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=5282 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:47.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:44:47.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:44:47.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:44:47.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:47.047 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:44:47.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:44:47.047 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:44:47.047 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:44:47.089 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:44:47.094 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:44:47.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:44:47.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:47.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:44:47.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:44:47.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:47.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:47.147 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:44:47.625 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:44:48.103 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:44:48.581 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:44:49.059 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:44:49.536 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:44:50.014 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:44:50.492 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 01:44:50.970 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 01:44:51.448 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 01:44:51.925 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 01:44:52.403 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 01:44:52.881 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 01:44:53.359 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 01:44:53.830 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 01:44:54.307 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 01:44:54.784 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 01:44:55.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:44:55.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:44:55.110 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:44:55.110 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:44:55.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:44:55.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:44:55.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:44:55.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:44:55.123 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:44:55.123 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:44:55.123 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:44:55.123 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:44:55.123 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:44:55.123 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:44:55.123 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:44:55.123 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7011 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:55.123 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7011 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:55.123 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7011 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:55.123 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7011 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:55.123 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7011 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:44:55.123 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7011 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:45:00.123 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:45:00.123 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:45:00.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:45:00.126 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:45:00.127 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:45:00.127 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:45:00.135 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:45:00.137 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:45:00.137 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:45:00.137 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:45:00.137 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:45:00.140 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:45:00.141 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:45:00.141 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:45:00.141 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:45:00.141 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:45:00.141 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:45:00.141 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:45:00.141 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:45:00.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:00.143 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:45:00.143 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:45:00.144 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:45:00.144 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:45:00.144 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:45:00.144 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:45:00.144 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:45:00.144 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:45:00.144 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:00.146 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:45:00.146 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:45:00.146 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:45:00.146 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:45:00.146 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:45:00.146 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:45:00.146 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:45:00.146 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:45:00.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:00.148 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:45:00.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:45:00.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:45:00.149 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:45:00.149 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:45:00.149 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:00.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:00.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:00.154 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:45:00.637 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:45:00.680 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:45:00.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:00.683 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:45:00.687 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:45:00.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:45:00.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:45:00.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:45:00.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:00.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:45:00.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:45:00.725 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:45:00.725 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:45:00.728 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:45:00.729 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:45:00.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:00.739 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:45:00.739 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:45:00.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:00.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:01.114 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:45:01.151 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:01.152 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:01.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:01.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:01.592 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:45:02.070 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:45:02.153 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:02.154 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:02.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:02.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:02.548 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:45:03.026 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:45:03.154 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:03.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:03.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:03.159 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:03.504 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:45:03.982 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:45:04.155 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:04.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:04.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:04.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:04.460 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:45:04.938 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:45:05.156 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:05.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:05.157 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:05.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:05.416 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:45:05.895 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:45:06.373 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:45:06.852 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:45:07.330 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:45:07.808 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:45:08.286 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:45:08.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:08.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:08.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:45:08.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:45:08.763 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:45:08.763 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:45:08.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:45:08.764 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:45:08.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:08.765 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:45:08.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:45:08.766 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:45:08.766 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:45:08.809 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:45:08.812 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:45:08.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:08.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:45:08.816 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:45:08.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:08.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:09.241 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:45:09.719 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:45:10.197 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:45:10.675 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:45:11.153 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:45:11.632 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:45:12.110 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:45:12.588 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:45:13.066 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:45:13.543 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:45:14.022 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:45:14.500 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:45:14.978 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:45:15.456 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:45:15.934 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:45:16.413 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:45:16.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:16.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:16.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:45:16.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:45:16.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:16.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:16.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:16.831 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:16.832 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:45:16.832 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:45:16.832 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:45:16.832 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:45:16.832 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:45:16.832 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:45:16.832 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:45:21.834 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:45:21.835 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:45:21.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:45:21.837 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:45:21.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:45:21.839 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:45:21.848 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:45:21.849 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:45:21.850 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:45:21.850 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:45:21.850 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:45:21.855 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:45:21.855 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:45:21.855 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:45:21.855 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:45:21.855 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:45:21.855 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:45:21.855 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:45:21.855 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:45:21.856 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:21.858 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:45:21.859 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:45:21.859 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:45:21.859 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:45:21.859 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:45:21.859 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:45:21.859 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:45:21.859 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:45:21.859 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:21.861 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:45:21.862 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:45:21.862 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:45:21.862 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:45:21.862 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:45:21.862 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:45:21.862 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:45:21.862 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:45:21.862 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:21.865 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:45:21.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:45:21.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:45:21.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:45:21.865 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:45:21.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:45:21.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:45:21.866 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:45:21.866 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:45:21.866 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:21.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:21.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:21.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:21.871 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:45:22.353 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:45:22.391 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:45:22.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:22.392 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:45:22.393 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:45:22.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:45:22.414 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:45:22.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:45:22.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:22.420 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:45:22.420 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:45:22.421 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:45:22.421 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:45:22.445 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:45:22.449 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:45:22.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:22.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:45:22.466 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:45:22.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:22.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:22.830 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:45:22.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:22.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:22.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:22.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:23.308 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:45:23.786 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:45:23.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:23.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:23.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:23.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:24.264 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:45:24.741 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:45:24.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:24.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:24.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:24.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:25.219 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:45:25.697 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:45:25.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:25.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:25.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:25.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:26.175 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:45:26.653 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:45:26.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:26.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:26.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:26.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:27.131 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:45:27.609 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:45:28.087 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:45:28.565 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:45:29.043 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:45:29.521 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:45:29.999 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:45:30.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:30.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:30.471 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:45:30.471 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:45:30.477 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:45:30.489 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:45:30.489 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:45:30.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:45:30.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:30.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:45:30.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:45:30.491 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:45:30.491 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:45:30.522 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:45:30.526 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:45:30.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:30.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:45:30.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:45:30.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:30.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:30.954 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:45:31.432 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:45:31.910 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:45:32.388 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:45:32.866 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:45:33.343 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:45:33.820 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:45:34.298 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:45:34.776 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:45:35.254 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:45:35.732 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:45:36.210 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:45:36.688 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:45:37.166 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:45:37.644 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:45:38.121 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:45:38.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:38.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:38.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:45:38.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:45:38.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:45:38.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:45:38.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:45:38.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:38.563 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:45:38.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:45:38.563 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:45:38.563 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:45:38.590 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:45:38.594 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:45:38.598 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:45:38.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:38.608 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:45:38.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:45:38.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:38.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:39.075 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:45:39.553 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:45:40.031 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:45:40.509 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:45:40.987 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:45:41.465 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:45:41.942 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:45:42.420 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:45:42.897 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:45:43.383 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:45:43.861 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:45:44.339 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:45:44.817 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:45:45.294 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:45:45.772 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:45:46.249 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:45:46.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:46.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:46.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:45:46.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:45:46.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:45:46.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:45:46.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:45:46.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:46.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:45:46.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:45:46.634 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:45:46.634 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:45:46.669 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:45:46.672 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:45:46.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:46.683 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:45:46.684 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:45:46.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:46.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:46.727 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:45:47.205 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:45:47.682 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:45:48.160 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:45:48.637 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:45:49.115 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:45:49.593 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:45:50.071 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 01:45:50.548 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 01:45:51.026 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 01:45:51.504 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 01:45:51.981 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 01:45:52.459 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 01:45:52.937 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 01:45:53.414 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 01:45:53.891 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 01:45:54.369 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 01:45:54.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:45:54.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:45:54.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:45:54.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:45:54.689 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=7007 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:45:54.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:54.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:54.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:54.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:54.695 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:45:54.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:45:54.695 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:45:54.695 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:45:54.695 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:45:54.695 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:45:54.695 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:45:59.698 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:45:59.698 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:45:59.699 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:45:59.701 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:45:59.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:45:59.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:45:59.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:45:59.713 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:45:59.713 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:45:59.713 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:45:59.713 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:45:59.718 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:45:59.718 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:45:59.718 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:45:59.718 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:45:59.718 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:45:59.718 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:45:59.718 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:45:59.718 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:45:59.719 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:45:59.721 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:45:59.721 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:45:59.721 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:45:59.721 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:45:59.721 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:45:59.722 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:45:59.722 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:45:59.722 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:45:59.722 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:45:59.724 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:45:59.724 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:45:59.724 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:45:59.724 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:45:59.724 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:45:59.724 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:45:59.724 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:45:59.724 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:45:59.724 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:45:59.727 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:45:59.728 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:45:59.728 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:45:59.728 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:59.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:59.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:45:59.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:45:59.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:45:59.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:59.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:59.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:59.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:59.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:45:59.733 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:46:00.216 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:46:00.255 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:46:00.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:00.256 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:46:00.257 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:46:00.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:00.271 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:00.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:46:00.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:00.277 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:00.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:00.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:46:00.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:46:00.308 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:46:00.312 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:46:00.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:00.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:00.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:00.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:00.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:00.693 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:46:00.730 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:46:00.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:46:00.732 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:46:00.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:46:01.171 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:46:01.649 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:46:01.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:46:01.732 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:46:01.732 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:46:01.736 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:46:02.128 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:46:02.606 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:46:02.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:46:02.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:46:02.733 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:46:02.737 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:46:03.083 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:46:03.561 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:46:03.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:46:03.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:46:03.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:46:03.738 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:46:04.039 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:46:04.517 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:46:04.734 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:46:04.735 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:46:04.735 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:46:04.738 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:46:04.995 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:46:05.474 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:46:05.952 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:46:06.429 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:46:06.907 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:46:07.386 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:46:07.864 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:46:08.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:08.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:08.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:08.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:08.342 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:46:08.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:08.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:08.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:46:08.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:08.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:08.353 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:08.353 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:46:08.353 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:46:08.387 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:46:08.391 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:46:08.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:08.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:08.401 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:08.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:08.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:08.819 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:46:09.297 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:46:09.774 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:46:10.253 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:46:10.730 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:46:11.208 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:46:11.686 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:46:12.164 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:46:12.642 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:46:13.120 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:46:13.598 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:46:14.076 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:46:14.554 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:46:15.032 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:46:15.510 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:46:15.987 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:46:16.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:16.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:16.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:16.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:16.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:16.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:16.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:46:16.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:16.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:16.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:16.424 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:46:16.424 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:46:16.457 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:46:16.461 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:46:16.464 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:46:16.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:16.472 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:16.472 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:16.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:16.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:16.941 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:46:17.419 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:46:17.896 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:46:18.374 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:46:18.852 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:46:19.329 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:46:19.807 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:46:20.285 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:46:20.763 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:46:21.241 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:46:21.718 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:46:22.196 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:46:22.674 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:46:23.151 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:46:23.628 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:46:24.106 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:46:24.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:24.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:24.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:24.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:24.499 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:24.499 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:24.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:46:24.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:24.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:24.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:24.501 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:46:24.501 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:46:24.524 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:46:24.527 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:46:24.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:24.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:24.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:24.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:24.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:24.583 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:46:25.060 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:46:25.538 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:46:26.016 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:46:26.493 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:46:26.971 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:46:27.449 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:46:27.926 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 01:46:28.404 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 01:46:28.882 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 01:46:29.359 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 01:46:29.836 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 01:46:30.314 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 01:46:30.792 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 01:46:31.270 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 01:46:31.747 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 01:46:32.222 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 01:46:32.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:32.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:32.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:32.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:32.563 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:32.563 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:32.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:46:32.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:32.566 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:32.566 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:32.566 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:46:32.566 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:46:32.591 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:46:32.595 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:46:32.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:32.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:32.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:32.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:32.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:32.699 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 01:46:33.176 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 01:46:33.655 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 01:46:34.132 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 01:46:34.610 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 01:46:35.088 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 01:46:35.565 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 01:46:36.043 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 01:46:36.521 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 01:46:36.999 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 01:46:37.478 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 01:46:37.956 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 01:46:38.434 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 01:46:38.911 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 01:46:39.389 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 01:46:39.867 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 01:46:40.345 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 01:46:40.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:40.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:40.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:40.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:40.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:40.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:40.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:46:40.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:40.628 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:40.628 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:40.628 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:46:40.628 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:46:40.672 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:46:40.676 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:46:40.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:40.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:40.692 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:40.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:40.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:40.822 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 01:46:41.300 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 01:46:41.778 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 01:46:42.256 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 01:46:42.735 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 01:46:43.213 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 01:46:43.691 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 01:46:44.169 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 01:46:44.647 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 01:46:45.125 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 01:46:45.603 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 01:46:46.081 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 01:46:46.559 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 01:46:47.037 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 01:46:47.515 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 01:46:47.994 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 01:46:48.472 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 01:46:48.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:48.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:48.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:48.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:48.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:48.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:48.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:46:48.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:48.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:48.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:48.720 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:46:48.720 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:46:48.753 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:46:48.758 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:46:48.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:48.772 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:48.772 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:48.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:48.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:48.949 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 01:46:49.427 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 01:46:49.905 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 01:46:50.383 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 01:46:50.861 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 01:46:51.339 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 01:46:51.816 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 01:46:52.294 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 01:46:52.772 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 01:46:53.249 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 01:46:53.727 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 01:46:54.205 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 01:46:54.683 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 01:46:55.161 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 01:46:55.639 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 01:46:56.117 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 01:46:56.595 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 01:46:56.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:56.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:56.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:56.779 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:56.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:46:56.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:46:56.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:46:56.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:56.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:56.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:56.793 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:46:56.793 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:46:56.829 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:46:56.833 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:46:56.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:46:56.843 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:46:56.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:46:56.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:56.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:46:57.071 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 01:46:57.548 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 01:46:58.026 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 01:46:58.504 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 01:46:58.981 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 01:46:59.459 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 01:46:59.937 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 01:47:00.414 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-05 01:47:00.892 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-05 01:47:01.370 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-05 01:47:01.847 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-05 01:47:02.325 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-05 01:47:02.803 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-05 01:47:03.280 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-05 01:47:03.758 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-05 01:47:04.236 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-05 01:47:04.713 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-05 01:47:04.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:47:04.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:04.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:47:04.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:47:04.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:04.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:04.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:04.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:04.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:47:04.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:47:04.869 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:47:04.869 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:47:04.870 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:47:04.870 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:47:04.870 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:47:04.870 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13907 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.870 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13907 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.870 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13907 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.870 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13907 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.871 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13907 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.871 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13907 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.871 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13907 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.871 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13908 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.871 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13908 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.871 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13908 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.871 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13908 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.871 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13908 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.871 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13908 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.871 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13908 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:04.871 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13908 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:09.868 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:47:09.869 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:47:09.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:47:09.871 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:47:09.871 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:47:09.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:47:09.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:47:09.879 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:47:09.879 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:09.879 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:47:09.880 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:47:09.883 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:47:09.883 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:47:09.883 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:47:09.883 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:09.883 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:47:09.883 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:47:09.883 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:47:09.883 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:47:09.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:09.885 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:47:09.885 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:47:09.885 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:47:09.885 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:09.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:47:09.885 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:47:09.885 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:47:09.885 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:47:09.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:09.886 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:47:09.886 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:47:09.886 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:47:09.886 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:09.886 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:47:09.886 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:47:09.886 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:47:09.886 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:47:09.886 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:09.888 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:47:09.888 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:47:09.888 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:47:09.889 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:47:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:09.889 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:47:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:09.889 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:47:09.889 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:47:09.889 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:47:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:09.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:14.893 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:47:14.893 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:47:14.896 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:47:14.896 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:47:14.896 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:47:14.896 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:47:14.905 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:47:14.906 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:47:14.907 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:14.907 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:47:14.907 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:47:14.910 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:47:14.911 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:47:14.911 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:47:14.911 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:14.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:47:14.912 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:47:14.912 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:47:14.912 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:47:14.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:14.913 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:47:14.913 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:47:14.914 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:47:14.914 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:14.914 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:47:14.914 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:47:14.914 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:47:14.914 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:47:14.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:14.916 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:47:14.916 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:47:14.916 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:47:14.916 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:14.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:47:14.916 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:47:14.916 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:47:14.916 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:47:14.916 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:14.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:47:14.920 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:47:14.920 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:47:14.920 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:14.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:14.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:14.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:14.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:14.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:14.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:14.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:14.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:14.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:14.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:14.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:14.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:14.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:14.925 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:47:15.405 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:47:15.450 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:47:15.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:47:15.453 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:47:15.456 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:47:15.484 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:47:15.484 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:47:15.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:47:15.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:15.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:47:15.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:47:15.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:47:15.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:47:15.496 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:47:15.498 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:47:15.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:47:15.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:47:15.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:47:15.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:15.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:15.882 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:47:15.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:15.923 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:15.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:15.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:16.360 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:47:16.838 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:47:16.924 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:16.924 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:16.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:16.927 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:17.316 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:47:17.794 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:47:17.925 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:17.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:17.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:17.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:18.273 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:47:18.750 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:47:18.926 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:18.926 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:18.927 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:18.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:19.228 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:47:19.706 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:47:19.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:19.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:19.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:19.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:20.183 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:47:20.661 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:47:21.140 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:47:21.618 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:47:22.096 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:47:22.574 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:47:23.052 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:47:23.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:47:23.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:23.511 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:47:23.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:47:23.529 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:47:23.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:47:23.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:47:23.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:47:23.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:23.532 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:47:23.532 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:47:23.532 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:47:23.532 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:47:23.576 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:47:23.580 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:47:23.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:47:23.591 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:47:23.591 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:47:23.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:23.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:24.004 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:47:24.482 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:47:24.960 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:47:25.438 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:47:25.916 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:47:26.394 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:47:26.872 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:47:27.350 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:47:27.829 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:47:28.306 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:47:28.785 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:47:29.263 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:47:29.741 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:47:30.220 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:47:30.698 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:47:31.176 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:47:31.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:47:31.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:31.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:47:31.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:47:31.609 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:31.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:31.609 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:31.609 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:31.612 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:47:31.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:47:31.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:47:31.613 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:47:31.613 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:47:31.613 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:47:31.613 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:47:31.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:31.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:31.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:31.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:31.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:31.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:31.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:47:36.611 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:47:36.611 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:47:36.612 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:47:36.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:47:36.615 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:47:36.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:47:36.623 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:47:36.624 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:47:36.624 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:36.625 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:47:36.625 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:47:36.628 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:47:36.628 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:47:36.629 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:47:36.629 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:36.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:47:36.629 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:47:36.630 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:47:36.630 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:47:36.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:36.631 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:47:36.631 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:47:36.631 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:47:36.631 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:36.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:47:36.631 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:47:36.631 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:47:36.631 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:47:36.631 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:36.633 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:47:36.633 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:47:36.633 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:47:36.633 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:36.633 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:47:36.633 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:47:36.633 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:47:36.633 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:47:36.633 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:36.635 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:47:36.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:47:36.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:47:36.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:47:36.635 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:47:36.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:47:36.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:47:36.636 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:47:36.636 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:47:36.636 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:36.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:36.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:36.641 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:47:37.121 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:47:37.157 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:47:37.159 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:47:37.160 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:47:37.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:47:37.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:47:37.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:47:37.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:47:37.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:37.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:47:37.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:47:37.182 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:47:37.182 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:47:37.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:47:37.225 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:47:37.225 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:47:37.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:37.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:37.598 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:47:37.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:37.639 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:37.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:37.641 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:38.076 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:47:38.554 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:47:38.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:38.639 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:38.641 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:38.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:39.033 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:47:39.511 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:47:39.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:39.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:39.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:39.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:39.989 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:47:40.466 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:47:40.641 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:40.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:40.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:40.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:40.944 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:47:41.422 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:47:41.642 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:41.642 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:41.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:41.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:41.900 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:47:42.377 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:47:42.855 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:47:43.333 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:47:43.811 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:47:44.289 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:47:44.767 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:47:45.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:47:45.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:45.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:47:45.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:47:45.245 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:47:45.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:45.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:45.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:45.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:45.251 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:47:45.251 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:47:45.251 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:47:45.251 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:47:45.251 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:47:45.252 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:47:45.252 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:47:50.255 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:47:50.255 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:47:50.255 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:47:50.255 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:47:50.255 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:47:50.255 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:47:50.263 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:47:50.265 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:47:50.265 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:50.266 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:47:50.266 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:47:50.269 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:47:50.270 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:47:50.270 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:47:50.271 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:50.271 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:47:50.271 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:47:50.272 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:47:50.272 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:47:50.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:50.273 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:47:50.273 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:47:50.273 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:47:50.274 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:50.274 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:47:50.274 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:47:50.274 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:47:50.274 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:47:50.275 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:50.276 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:47:50.276 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:47:50.276 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:47:50.276 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:47:50.276 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:47:50.276 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:47:50.276 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:47:50.276 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:47:50.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:50.279 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:47:50.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:47:50.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:47:50.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:47:50.279 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:47:50.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:47:50.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:47:50.280 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:47:50.280 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:47:50.280 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:50.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:50.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:47:50.285 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:47:50.768 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:47:50.802 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:47:50.804 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:47:50.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:47:50.806 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:47:50.818 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:47:50.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:47:50.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:47:50.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:50.821 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:47:50.822 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:47:50.822 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:47:50.822 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:47:50.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:47:50.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:47:50.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:47:50.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:50.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:51.245 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:47:51.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:51.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:51.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:51.311 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:51.723 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:47:52.202 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:47:52.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:52.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:52.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:52.311 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:52.680 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:47:53.157 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:47:53.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:53.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:53.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:53.312 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:53.635 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:47:54.113 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:47:54.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:54.312 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:54.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:54.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:54.591 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:47:55.069 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:47:55.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:55.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:55.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:55.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:55.547 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:47:56.026 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:47:56.504 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:47:56.982 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:47:57.459 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:47:57.938 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:47:58.416 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:47:58.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:47:58.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:47:58.880 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:47:58.880 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:47:58.894 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:47:58.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:47:58.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:47:58.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:47:58.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:47:58.896 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:47:58.896 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:47:58.896 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:47:58.896 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:47:58.896 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:47:58.896 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:47:58.896 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:48:03.902 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:48:03.902 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:48:03.902 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:03.902 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:03.902 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:03.902 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:03.910 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:03.911 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:48:03.912 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:03.912 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:48:03.912 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:48:03.916 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:48:03.916 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:48:03.917 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:48:03.917 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:03.917 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:03.918 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:48:03.918 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:48:03.918 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:48:03.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:03.919 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:48:03.920 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:48:03.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:48:03.920 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:03.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:03.920 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:48:03.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:48:03.920 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:48:03.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:03.922 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:48:03.922 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:48:03.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:48:03.923 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:03.923 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:03.923 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:48:03.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:48:03.923 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:48:03.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:03.926 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:48:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:48:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:48:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:48:03.926 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:48:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:48:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:48:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:48:03.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:48:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:48:03.927 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:48:03.927 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:48:03.927 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:03.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:03.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:03.932 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:48:04.415 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:48:04.449 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:48:04.450 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:48:04.451 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:48:04.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:48:04.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:48:04.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:48:04.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:48:04.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:48:04.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:48:04.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:48:04.474 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:48:04.474 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:48:04.892 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:48:04.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:04.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:04.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:04.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:05.370 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:48:05.847 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:48:05.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:05.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:05.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:05.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:06.325 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:48:06.803 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:48:06.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:06.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:06.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:06.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:07.280 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:48:07.758 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:48:07.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:07.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:07.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:07.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:08.235 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:48:08.713 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:48:08.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:08.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:08.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:08.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:09.190 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:48:09.668 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:48:10.146 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:48:10.624 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:48:10.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:48:10.965 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:48:10.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:10.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:10.970 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:10.970 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:10.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:10.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:10.971 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:10.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:10.971 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:48:10.971 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:48:10.971 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:48:15.973 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:48:15.973 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:48:15.975 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:15.976 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:15.976 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:15.976 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:15.981 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:15.981 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:48:15.981 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:15.981 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:48:15.982 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:48:15.983 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:48:15.983 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:48:15.984 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:48:15.984 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:15.984 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:15.985 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:48:15.985 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:48:15.985 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:48:15.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:15.986 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:48:15.986 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:48:15.986 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:48:15.986 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:15.986 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:15.986 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:48:15.986 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:48:15.986 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:48:15.986 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:15.988 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:48:15.988 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:48:15.988 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:48:15.988 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:15.988 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:15.988 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:48:15.988 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:48:15.988 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:48:15.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:15.991 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:48:15.991 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:48:15.991 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:48:15.991 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:15.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:15.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:15.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:15.996 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:48:16.479 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:48:16.515 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:48:16.516 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:48:16.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:48:16.517 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:48:16.531 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:48:16.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:48:16.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:48:16.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:48:16.541 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:48:16.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:48:16.542 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:48:16.542 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:48:16.956 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:48:16.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:16.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:16.995 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:16.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:17.434 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:48:17.912 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:48:17.995 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:17.995 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:17.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:17.999 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:18.390 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:48:18.868 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:48:18.996 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:18.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:18.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:19.000 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:19.346 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:48:19.823 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:48:19.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:19.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:19.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:20.001 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:20.301 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:48:20.778 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:48:20.999 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:20.999 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:20.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:21.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:21.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:21.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:21.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:21.036 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:21.036 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:21.036 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:21.036 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:21.036 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:21.036 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:48:21.036 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:48:21.259 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:48:21.744 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:48:22.230 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:48:22.716 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:48:23.200 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:48:23.683 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:48:24.169 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:48:24.655 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:48:25.140 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:48:25.625 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:48:26.039 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:48:26.039 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:48:26.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:48:26.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:48:26.040 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:48:26.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:26.042 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:26.044 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:26.044 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:26.048 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:26.049 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:48:26.049 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:26.049 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:48:26.049 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:48:26.049 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:48:26.049 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:48:26.049 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:48:26.049 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:26.050 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:26.050 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:48:26.050 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:48:26.050 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:48:26.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:26.051 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:48:26.051 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:48:26.051 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:48:26.051 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:26.051 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:26.051 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:48:26.051 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:48:26.051 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:48:26.051 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:26.052 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:48:26.052 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:48:26.052 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:48:26.052 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:26.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:26.052 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:48:26.052 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:48:26.052 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:48:26.052 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:48:26.054 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:48:26.054 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:48:26.054 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:26.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:26.055 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:48:26.055 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:48:26.055 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:48:31.059 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:48:31.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:48:31.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:31.062 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:31.062 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:31.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:31.070 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:31.070 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:48:31.071 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:31.071 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:48:31.071 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:48:31.073 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:48:31.073 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:48:31.073 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:48:31.073 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:31.074 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:31.074 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:48:31.074 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:48:31.075 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:48:31.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:31.075 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:48:31.075 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:48:31.075 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:48:31.076 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:31.076 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:31.076 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:48:31.076 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:48:31.076 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:48:31.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:31.077 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:48:31.078 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:48:31.078 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:48:31.078 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:31.078 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:31.078 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:48:31.078 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:48:31.078 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:48:31.078 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:31.080 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:48:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:48:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:48:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:48:31.080 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:48:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:48:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:48:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:48:31.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:48:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:48:31.081 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:48:31.081 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:48:31.081 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:31.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:31.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:31.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:31.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:31.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:31.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:31.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:31.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:31.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:31.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:31.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:31.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:31.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:31.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:31.086 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:48:31.570 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:48:31.608 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:48:31.609 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:48:31.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:48:31.611 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:48:31.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:48:31.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:48:31.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:48:31.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:48:31.633 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:48:31.633 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:48:31.633 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:48:31.633 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:48:32.047 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:48:32.084 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:32.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:32.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:32.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:32.525 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:48:33.002 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:48:33.107 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:33.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:33.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:33.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:33.480 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:48:33.958 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:48:34.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:34.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:34.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:34.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:34.435 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:48:34.913 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:48:35.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:35.110 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:35.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:35.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:35.391 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:48:35.869 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:48:36.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:36.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:36.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:36.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:36.346 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:48:36.824 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:48:37.302 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:48:37.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:37.779 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:48:38.257 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:48:38.367 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:38.734 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:48:39.211 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:48:39.368 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:39.688 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:48:40.166 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:48:40.369 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:40.644 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:48:41.121 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:48:41.370 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:41.370 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:41.599 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:48:42.080 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:48:42.562 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:48:43.042 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:48:43.524 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:48:44.005 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:48:44.482 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:48:44.951 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:48:45.371 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:45.420 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:48:45.898 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:48:46.372 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:46.375 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:48:46.853 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:48:47.331 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:48:47.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:47.809 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:48:48.287 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:48:48.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:48.764 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:48:49.242 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:48:49.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:49.720 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:48:50.198 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:48:50.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:50.675 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:48:51.153 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:48:51.631 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:48:52.108 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:48:52.449 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:48:52.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:48:52.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:52.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:52.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:52.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:52.459 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:52.459 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:52.459 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:52.459 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:52.459 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:48:52.459 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:48:52.459 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:48:52.459 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4566 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:48:52.459 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4566 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:48:52.459 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4566 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:48:52.459 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4566 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:48:52.459 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4566 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:48:52.459 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4566 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:48:52.460 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4566 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:48:57.463 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:48:57.463 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:48:57.464 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:57.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:57.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:57.467 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:57.472 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:57.472 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:48:57.472 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:57.473 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:48:57.473 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:48:57.474 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:48:57.475 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:48:57.475 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:48:57.475 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:57.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:57.476 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:48:57.476 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:48:57.476 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:48:57.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:57.477 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:48:57.477 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:48:57.477 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:48:57.478 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:57.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:57.478 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:48:57.478 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:48:57.478 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:48:57.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:57.480 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:48:57.480 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:48:57.480 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:48:57.480 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:48:57.481 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:57.481 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:48:57.481 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:48:57.481 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:48:57.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:57.484 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:48:57.485 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:48:57.485 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:48:57.485 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:48:57.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:57.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:57.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:57.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:48:57.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:57.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:57.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:57.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:57.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:57.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:57.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:57.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:57.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:57.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:57.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:57.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:57.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:57.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:48:57.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:48:57.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:57.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:48:57.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:57.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:57.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:57.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:48:57.490 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:48:57.973 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:48:58.010 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:48:58.011 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:48:58.011 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:48:58.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:48:58.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:48:58.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:48:58.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:48:58.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:48:58.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:48:58.028 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:48:58.028 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:48:58.028 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:48:58.067 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:48:58.071 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:48:58.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 01:48:58.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:48:58.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:48:58.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:48:58.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:48:58.443 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:48:58.487 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:58.488 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:58.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:58.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:58.872 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 01:48:58.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:48:58.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:48:58.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:48:58.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:48:58.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:48:58.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:48:58.884 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:48:58.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:48:58.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:48:58.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:48:58.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:48:58.885 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:48:58.885 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:48:58.885 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:49:03.886 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:49:03.887 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:49:03.888 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:49:03.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:49:03.890 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:49:03.891 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:49:03.894 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:49:03.894 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:49:03.894 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:49:03.894 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:49:03.894 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:49:03.895 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:49:03.895 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:49:03.895 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:49:03.895 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:49:03.896 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:49:03.896 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:49:03.896 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:49:03.896 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:49:03.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:49:03.897 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:49:03.897 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:49:03.897 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:49:03.897 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:49:03.898 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:49:03.898 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:49:03.898 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:49:03.898 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:49:03.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:49:03.900 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:49:03.900 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:49:03.900 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:49:03.900 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:49:03.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:49:03.900 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:49:03.900 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:49:03.900 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:49:03.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:03.903 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:49:03.903 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:49:03.903 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:49:03.904 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:03.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:03.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:03.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:03.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:03.908 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:49:04.389 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:49:04.428 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:49:04.429 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:49:04.430 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:49:04.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:49:04.441 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:49:04.441 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:49:04.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:49:04.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:04.446 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:49:04.446 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:49:04.446 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:49:04.446 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:49:04.481 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:49:04.485 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:49:04.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 01:49:04.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:49:04.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:49:04.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:04.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:04.866 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:49:04.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:49:04.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:49:04.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:49:04.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:49:05.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 01:49:05.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:05.303 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:49:05.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:49:05.312 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:49:05.312 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:49:05.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:49:05.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:49:05.315 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:49:05.315 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:49:05.315 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:49:05.315 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:49:05.315 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:49:05.315 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:49:05.315 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:49:05.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=303 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:49:05.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=303 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:49:05.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=303 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:49:05.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=303 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:49:05.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=303 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:49:05.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=303 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:49:05.315 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=303 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:49:10.314 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:49:10.315 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:49:10.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:49:10.317 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:49:10.318 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:49:10.319 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:49:10.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:49:10.328 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:49:10.328 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:49:10.328 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:49:10.328 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:49:10.331 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:49:10.332 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:49:10.332 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:49:10.332 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:49:10.333 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:49:10.333 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:49:10.334 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:49:10.334 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:49:10.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:49:10.334 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:49:10.334 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:49:10.335 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:49:10.335 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:49:10.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:49:10.335 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:49:10.335 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:49:10.335 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:49:10.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:49:10.337 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:49:10.337 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:49:10.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:49:10.337 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:49:10.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:49:10.337 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:49:10.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:49:10.337 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:49:10.337 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:10.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:49:10.341 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:49:10.341 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:49:10.341 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:49:10.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:49:10.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:10.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:10.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:10.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:49:10.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:10.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:10.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:10.345 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:49:10.829 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:49:10.863 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:49:10.864 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:49:10.865 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:49:10.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:49:10.883 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:49:10.883 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:49:10.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:49:10.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:10.888 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:49:10.888 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:49:10.888 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:49:10.889 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:49:10.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:49:10.932 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:49:10.932 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:49:10.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:10.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:11.305 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:49:11.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:49:11.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:49:11.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:49:11.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:49:11.784 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:49:12.262 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:49:12.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:49:12.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:49:12.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:49:12.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:49:12.740 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:49:13.218 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:49:13.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:49:13.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:49:13.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:49:13.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:49:13.696 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:49:14.173 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:49:14.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:49:14.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:49:14.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:49:14.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:49:14.651 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:49:15.128 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:49:15.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:49:15.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:49:15.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:49:15.351 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:49:15.606 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:49:16.084 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:49:16.562 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:49:17.040 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:49:17.518 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:49:17.996 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:49:18.474 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:49:18.952 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:49:19.430 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:49:19.907 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:49:20.385 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:49:20.863 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:49:21.341 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:49:21.819 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:49:22.297 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:49:22.774 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:49:23.252 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:49:23.730 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:49:24.208 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:49:24.685 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:49:25.164 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:49:25.642 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:49:26.120 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:49:26.598 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:49:26.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:49:26.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:26.907 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:49:26.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:49:26.927 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:49:26.927 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:49:26.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:49:26.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:26.929 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:49:26.929 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:49:26.929 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:49:26.929 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:49:26.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:49:26.982 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:49:26.982 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:49:26.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:26.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:27.076 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:49:27.553 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:49:28.031 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:49:28.509 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:49:28.987 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:49:29.465 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:49:29.943 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:49:30.421 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:49:30.898 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:49:31.376 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:49:31.855 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:49:32.333 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:49:32.810 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:49:33.288 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:49:33.765 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:49:34.243 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:49:34.721 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:49:35.198 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:49:35.675 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:49:36.153 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:49:36.631 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:49:37.108 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:49:37.586 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:49:38.064 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:49:38.541 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 01:49:39.018 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 01:49:39.497 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 01:49:39.975 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 01:49:40.453 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 01:49:40.931 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 01:49:41.409 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 01:49:41.887 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 01:49:42.365 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 01:49:42.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:49:42.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:42.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:49:42.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:49:42.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:49:42.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:49:42.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:49:42.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:42.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:49:42.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:49:42.576 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:49:42.576 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:49:42.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:49:42.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:49:42.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:49:42.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:42.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:42.842 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 01:49:43.320 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 01:49:43.795 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 01:49:44.274 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 01:49:44.752 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 01:49:45.230 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 01:49:45.708 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 01:49:46.185 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 01:49:46.663 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 01:49:47.141 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 01:49:47.619 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 01:49:48.096 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 01:49:48.574 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 01:49:49.052 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 01:49:49.529 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 01:49:50.008 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 01:49:50.486 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 01:49:50.964 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 01:49:51.442 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 01:49:51.920 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 01:49:52.398 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 01:49:52.876 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 01:49:53.353 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 01:49:53.832 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 01:49:54.311 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 01:49:54.789 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 01:49:55.267 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 01:49:55.744 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 01:49:56.222 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 01:49:56.700 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 01:49:57.178 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 01:49:57.656 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 01:49:58.134 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 01:49:58.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:49:58.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:58.211 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:49:58.211 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:49:58.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:49:58.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:49:58.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:49:58.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:58.218 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:49:58.218 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:49:58.218 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:49:58.218 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:49:58.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:49:58.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:49:58.225 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:49:58.225 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:49:58.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:58.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:49:58.611 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 01:49:59.089 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 01:49:59.567 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 01:50:00.044 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 01:50:00.523 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 01:50:01.001 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 01:50:01.479 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 01:50:01.957 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 01:50:02.434 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 01:50:02.912 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 01:50:03.390 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 01:50:03.867 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 01:50:04.344 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 01:50:04.822 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 01:50:05.300 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 01:50:05.778 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 01:50:06.256 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 01:50:06.734 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 01:50:07.212 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 01:50:07.689 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 01:50:08.167 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 01:50:08.644 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 01:50:09.121 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 01:50:09.599 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 01:50:10.077 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 01:50:10.555 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 01:50:11.033 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-05 01:50:11.511 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-05 01:50:11.989 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-05 01:50:12.468 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-05 01:50:12.945 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-05 01:50:13.423 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-05 01:50:13.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:50:13.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:50:13.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:50:13.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:50:13.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:13.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:13.869 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:13.869 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:13.873 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:50:13.873 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:50:13.873 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:50:13.873 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:50:13.873 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:50:13.873 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:50:13.874 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:50:13.874 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:13.874 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:13.874 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:13.874 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:13.874 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:13.874 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:13.875 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:13.875 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:13.875 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:13.875 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:13.875 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:13.875 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:13.875 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:13.875 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:18.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:50:18.873 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:50:18.874 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:50:18.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:50:18.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:50:18.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:50:18.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:50:18.887 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:50:18.887 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:18.887 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:50:18.887 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:50:18.891 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:50:18.891 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:50:18.891 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:50:18.891 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:18.892 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:50:18.892 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:50:18.892 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:50:18.892 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:50:18.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:18.894 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:50:18.894 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:50:18.894 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:50:18.894 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:18.895 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:50:18.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:50:18.895 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:50:18.895 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:50:18.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:18.896 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:50:18.896 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:50:18.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:50:18.897 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:18.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:50:18.897 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:50:18.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:50:18.897 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:50:18.897 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:18.898 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:50:18.899 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:50:18.899 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:50:18.899 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:18.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:50:18.900 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:50:18.900 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:50:18.900 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:50:23.903 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:50:23.903 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:50:23.905 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:50:23.906 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:50:23.908 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:50:23.908 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:50:23.914 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:50:23.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:50:23.914 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:23.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:50:23.914 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:50:23.915 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:50:23.916 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:50:23.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:50:23.917 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:23.917 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:50:23.918 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:50:23.918 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:50:23.918 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:50:23.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:23.919 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:50:23.920 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:50:23.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:50:23.920 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:23.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:50:23.921 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:50:23.921 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:50:23.921 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:50:23.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:23.923 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:50:23.923 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:50:23.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:50:23.923 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:23.923 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:50:23.923 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:50:23.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:50:23.923 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:50:23.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:23.927 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:50:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:50:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:50:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:50:23.927 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:50:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:50:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:50:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:50:23.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:50:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:23.927 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:50:23.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:23.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:23.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:23.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:23.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:23.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:23.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:23.928 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:50:23.928 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:50:23.928 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:50:23.928 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:50:23.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:23.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:23.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:23.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:50:23.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:23.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:23.933 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:50:24.417 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:50:24.463 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:50:24.464 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:50:24.465 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:50:24.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:50:24.495 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:50:24.495 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:50:24.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:50:24.502 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:50:24.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:50:24.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:50:24.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:50:24.505 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:50:24.505 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:50:24.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:50:24.510 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:50:24.510 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:50:24.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:50:24.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:50:24.894 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:50:24.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:24.934 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:24.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:24.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:25.372 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:50:25.850 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:50:25.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:25.934 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:25.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:25.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:26.328 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:50:26.805 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:50:26.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:26.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:26.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:26.942 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:27.283 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:50:27.761 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:50:27.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:27.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:27.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:27.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:28.239 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:50:28.717 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:50:28.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:28.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:28.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:28.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:29.195 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:50:29.673 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:50:30.151 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:50:30.628 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:50:31.106 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:50:31.583 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:50:32.061 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:50:32.539 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:50:33.017 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:50:33.495 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:50:33.973 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:50:34.451 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:50:34.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:50:34.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:50:34.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:50:34.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:50:34.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:34.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:34.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:34.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:34.904 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:50:34.904 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:50:34.904 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:50:34.904 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:50:34.904 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:50:34.904 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:50:34.904 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:50:39.907 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:50:39.907 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:50:39.909 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:50:39.911 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:50:39.911 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:50:39.911 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:50:39.920 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:50:39.922 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:50:39.922 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:39.923 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:50:39.923 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:50:39.927 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:50:39.927 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:50:39.928 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:50:39.928 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:39.928 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:50:39.928 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:50:39.928 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:50:39.928 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:50:39.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:39.930 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:50:39.931 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:50:39.931 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:50:39.931 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:39.931 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:50:39.931 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:50:39.931 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:50:39.931 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:50:39.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:39.933 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:50:39.933 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:50:39.933 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:50:39.933 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:39.934 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:50:39.934 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:50:39.934 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:50:39.934 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:50:39.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:39.937 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:50:39.937 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:50:39.937 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:50:39.938 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:39.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:39.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:39.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:39.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:39.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:39.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:39.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:39.942 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:50:40.427 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:50:40.467 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:50:40.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:50:40.470 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:50:40.472 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:50:40.499 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:50:40.499 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:50:40.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:50:40.504 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:50:40.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:50:40.506 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:50:40.506 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:50:40.506 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:50:40.506 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:50:40.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:50:40.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:50:40.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:50:40.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:50:40.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:50:40.903 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:50:40.940 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:40.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:40.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:40.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:41.381 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:50:41.859 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:50:41.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:41.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:41.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:41.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:42.337 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:50:42.815 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:50:42.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:42.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:42.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:42.948 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:43.293 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:50:43.771 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:50:43.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:43.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:43.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:43.949 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:44.249 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:50:44.727 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:50:44.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:44.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:44.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:44.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:45.205 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:50:45.684 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:50:46.162 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:50:46.639 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:50:47.118 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:50:47.596 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:50:48.073 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:50:48.551 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:50:49.029 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:50:49.507 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:50:49.985 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:50:50.463 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:50:50.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:50:50.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:50:50.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:50:50.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:50:50.921 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:50.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:50.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:50.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:50.924 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:50:50.924 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:50:50.924 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:50:50.924 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:50:50.924 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:50:50.924 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:50:50.924 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:50:50.924 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2345 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:50.924 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2345 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:50.925 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2345 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:50.925 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2345 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:50.925 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2345 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:50.925 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2345 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:50.925 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2345 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:50:55.924 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:50:55.924 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:50:55.926 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:50:55.928 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:50:55.929 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:50:55.929 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:50:55.935 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:50:55.936 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:50:55.936 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:55.936 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:50:55.936 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:50:55.938 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:50:55.938 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:50:55.939 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:50:55.939 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:55.939 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:50:55.939 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:50:55.940 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:50:55.940 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:50:55.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:55.941 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:50:55.941 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:50:55.941 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:50:55.941 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:55.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:50:55.941 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:50:55.941 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:50:55.941 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:50:55.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:55.943 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:50:55.943 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:50:55.943 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:50:55.943 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:50:55.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:50:55.943 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:50:55.944 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:50:55.944 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:50:55.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:55.946 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:50:55.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:50:55.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:50:55.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:50:55.946 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:50:55.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:50:55.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:50:55.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:50:55.947 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:50:55.947 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:50:55.947 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:55.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:50:55.952 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:50:56.434 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:50:56.478 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:50:56.480 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:50:56.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:50:56.482 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:50:56.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:50:56.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:50:56.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:50:56.519 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:50:56.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:50:56.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:50:56.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:50:56.522 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:50:56.522 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:50:56.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:50:56.528 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:50:56.528 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:50:56.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:50:56.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:50:56.911 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:50:56.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:56.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:56.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:56.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:57.389 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:50:57.405 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:50:57.867 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:50:57.950 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:57.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:57.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:57.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:58.345 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:50:58.823 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:50:58.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:58.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:58.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:58.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:50:59.301 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:50:59.778 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:50:59.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:50:59.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:50:59.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:50:59.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:00.256 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:51:00.734 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:51:00.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:00.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:00.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:00.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:01.212 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:51:01.689 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:51:02.167 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:51:02.645 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:51:03.123 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:51:03.601 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:51:04.079 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:51:04.557 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:51:05.035 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:51:05.513 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:51:05.991 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:51:06.469 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:51:06.946 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:51:07.424 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:51:07.902 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:51:08.380 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:51:08.857 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:51:09.334 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:51:09.812 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:51:10.290 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:51:10.768 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:51:11.246 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:51:11.724 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:51:12.202 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:51:12.680 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:51:13.158 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:51:13.636 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:51:14.113 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:51:14.591 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:51:15.069 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:51:15.547 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:51:16.025 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:51:16.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:51:16.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:51:16.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:51:16.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:51:16.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:16.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:16.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:16.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:16.133 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:51:16.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:51:16.134 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:51:16.134 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:51:16.134 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:51:16.134 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:51:16.134 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:51:16.134 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:16.134 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:16.134 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:16.134 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:16.134 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:16.134 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:16.134 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:21.136 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:51:21.136 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:51:21.137 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:51:21.140 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:51:21.140 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:51:21.140 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:51:21.149 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:51:21.151 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:51:21.151 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:51:21.152 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:51:21.152 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:51:21.155 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:51:21.156 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:51:21.156 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:51:21.157 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:51:21.157 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:51:21.157 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:51:21.158 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:51:21.158 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:51:21.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:21.160 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:51:21.161 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:51:21.161 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:51:21.161 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:51:21.161 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:51:21.161 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:51:21.161 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:51:21.162 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:51:21.162 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:21.164 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:51:21.164 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:51:21.164 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:51:21.164 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:51:21.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:51:21.165 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:51:21.165 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:51:21.165 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:51:21.165 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:51:21.167 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:51:21.167 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:51:21.167 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:21.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:21.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:21.172 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:51:21.655 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:51:21.699 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:51:21.701 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:51:21.701 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:51:21.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:51:21.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:51:21.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:51:21.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:51:21.739 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:51:21.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:51:21.742 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:51:21.742 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:51:21.742 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:51:21.742 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:51:21.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:51:21.748 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:51:21.748 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:51:21.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:51:21.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:51:22.131 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:51:22.169 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:22.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:22.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:22.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:22.609 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:51:22.625 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:51:23.087 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:51:23.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:23.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:23.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:23.176 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:23.565 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:51:23.599 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:51:24.042 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:51:24.172 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:24.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:24.172 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:24.176 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:24.520 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:51:24.573 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:51:24.998 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:51:25.173 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:25.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:25.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:25.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:25.476 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:51:25.548 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:51:25.954 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:51:26.174 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:26.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:26.174 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:26.179 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:26.432 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:51:26.522 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:51:26.910 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:51:27.388 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:51:27.496 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:51:27.865 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:51:28.343 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:51:28.470 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:51:28.821 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:51:29.299 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:51:29.444 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:51:29.777 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:51:30.254 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:51:30.418 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:51:30.732 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:51:31.210 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:51:31.392 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:51:31.688 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:51:32.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:51:32.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:51:32.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:51:32.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:51:32.150 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:32.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:32.151 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:32.151 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:32.154 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:51:32.154 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:51:32.155 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:51:32.155 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:51:32.155 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:51:32.155 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:51:32.155 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:51:32.155 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.156 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.156 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.156 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.156 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.156 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.156 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.156 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2347 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.156 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2347 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.156 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2347 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.156 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2347 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.156 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2347 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.157 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2347 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.157 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2347 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:32.157 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2347 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:37.154 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:51:37.154 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:51:37.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:51:37.157 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:51:37.159 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:51:37.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:51:37.169 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:51:37.169 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:51:37.169 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:51:37.169 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:51:37.169 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:51:37.169 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:51:37.169 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:51:37.170 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:51:37.170 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:51:37.170 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:51:37.170 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:51:37.170 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:51:37.170 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:51:37.170 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:37.170 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:51:37.170 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:51:37.170 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:51:37.170 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:51:37.170 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:51:37.170 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:51:37.170 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:51:37.170 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:51:37.170 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:37.171 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:51:37.171 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:51:37.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:51:37.171 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:51:37.171 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:51:37.171 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:51:37.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:51:37.171 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:51:37.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:37.172 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:51:37.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:51:37.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:51:37.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:51:37.172 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:51:37.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:51:37.173 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:51:37.173 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:51:37.173 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:37.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:37.178 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:51:37.660 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:51:37.695 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:51:37.696 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:51:37.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:51:37.698 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:51:37.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:51:37.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:51:37.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:51:37.740 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:51:37.742 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:51:37.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:51:37.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:51:37.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:51:37.745 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:51:37.745 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:51:37.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:51:37.755 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:51:37.755 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:51:37.755 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:51:37.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:51:37.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:51:38.137 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:51:38.175 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:38.175 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:38.176 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:38.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:38.614 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:51:38.631 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:51:39.092 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:51:39.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:39.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:39.176 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:39.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:39.569 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:51:40.047 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:51:40.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:40.177 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:40.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:40.179 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:40.525 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:51:41.004 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:51:41.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:41.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:41.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:41.179 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:41.482 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:51:41.960 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:51:42.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:42.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:42.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:42.180 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:42.438 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:51:42.915 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:51:43.392 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:51:43.870 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:51:44.348 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:51:44.825 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:51:45.303 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:51:45.781 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:51:46.259 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:51:46.736 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:51:47.214 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:51:47.692 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:51:48.170 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:51:48.371 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:51:48.647 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:51:49.149 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:51:49.626 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:51:50.105 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:51:50.582 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:51:51.060 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:51:51.538 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:51:52.016 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:51:52.494 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:51:52.972 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:51:53.449 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:51:53.927 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:51:54.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:51:54.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:51:54.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:51:54.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:51:54.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:54.257 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:54.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:54.258 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:54.258 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:51:54.258 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:51:54.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:51:54.259 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:51:54.259 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:51:54.259 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:51:54.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:51:54.259 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3643 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:54.259 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3643 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:54.259 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3643 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:54.259 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3643 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:54.259 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3643 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:54.259 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3643 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:54.259 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3643 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:51:59.260 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:51:59.261 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:51:59.262 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:51:59.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:51:59.263 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:51:59.264 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:51:59.270 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:51:59.271 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:51:59.271 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:51:59.271 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:51:59.272 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:51:59.274 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:51:59.274 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:51:59.274 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:51:59.274 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:51:59.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:51:59.274 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:51:59.274 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:51:59.274 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:51:59.274 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:51:59.276 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:51:59.276 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:51:59.276 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:51:59.276 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:51:59.276 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:51:59.276 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:51:59.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:51:59.277 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:51:59.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:51:59.278 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:51:59.278 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:51:59.278 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:51:59.278 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:51:59.278 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:51:59.278 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:51:59.278 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:51:59.278 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:51:59.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:51:59.280 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:51:59.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:51:59.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:51:59.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:51:59.280 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:51:59.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:51:59.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:51:59.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:51:59.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:51:59.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:59.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:59.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:51:59.281 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:51:59.281 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:51:59.281 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:59.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:51:59.286 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:51:59.770 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:51:59.800 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:51:59.801 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:51:59.802 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:51:59.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:51:59.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:51:59.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:51:59.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:51:59.838 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:51:59.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:51:59.843 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:51:59.843 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:51:59.843 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:51:59.843 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:51:59.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:51:59.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:51:59.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:51:59.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:51:59.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:00.246 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:52:00.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:00.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:00.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:00.286 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:00.724 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:52:00.740 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:52:01.202 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:52:01.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:01.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:01.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:01.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:01.680 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:52:02.157 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:52:02.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:02.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:02.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:02.288 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:02.635 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:52:03.113 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:52:03.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:03.286 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:03.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:03.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:03.592 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:52:04.070 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:52:04.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:04.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:04.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:04.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:04.546 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:52:05.024 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:52:05.502 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:52:05.980 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:52:06.458 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:52:06.936 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:52:07.413 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:52:07.892 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:52:08.369 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:52:08.847 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:52:09.324 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:52:09.803 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:52:09.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:09.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:09.880 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:09.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:09.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:09.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:09.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:09.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:09.896 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:52:09.896 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:52:09.896 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:52:09.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:52:09.897 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:52:09.897 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:52:09.897 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:52:09.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2266 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:09.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2266 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:09.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2266 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:09.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2266 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:09.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2266 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:09.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2266 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:09.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2266 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:14.897 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:52:14.897 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:52:14.898 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:52:14.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:52:14.901 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:52:14.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:52:14.904 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:52:14.904 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:52:14.904 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:14.904 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:52:14.904 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:52:14.905 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:52:14.905 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:52:14.906 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:52:14.906 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:14.906 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:52:14.906 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:52:14.906 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:52:14.906 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:52:14.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:14.907 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:52:14.908 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:52:14.908 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:52:14.908 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:14.908 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:52:14.908 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:52:14.908 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:52:14.908 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:52:14.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:14.909 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:52:14.909 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:52:14.910 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:52:14.910 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:14.910 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:52:14.910 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:52:14.910 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:52:14.910 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:52:14.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:14.912 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:52:14.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:52:14.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:52:14.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:52:14.912 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:52:14.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:52:14.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:52:14.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:52:14.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:52:14.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:14.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:14.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:52:14.913 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:52:14.913 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:52:14.913 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:14.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:14.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:14.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:14.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:14.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:14.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:14.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:14.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:14.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:14.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:14.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:14.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:14.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:14.918 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:52:15.401 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:52:15.433 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:52:15.434 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:52:15.435 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:52:15.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:15.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:15.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:15.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:52:15.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:15.453 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:15.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:15.453 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:52:15.453 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:52:15.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:15.506 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:15.506 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:15.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:15.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:15.879 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:52:15.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:15.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:15.885 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:15.885 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:15.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:15.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:15.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:52:15.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:15.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:15.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:15.906 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:52:15.906 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:52:15.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:15.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:15.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:15.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:15.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:15.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:15.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:15.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:15.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:16.356 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:52:16.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:16.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:16.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:16.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:16.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:16.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:16.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:52:16.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:16.638 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:16.638 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:16.638 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:52:16.638 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:52:16.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:16.694 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:16.694 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:16.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:16.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:16.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:16.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:16.797 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:16.797 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:16.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:16.819 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:16.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:52:16.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:16.821 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:16.821 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:16.821 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:52:16.821 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:52:16.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:16.826 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:16.826 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:16.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:16.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:16.833 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:52:16.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:16.917 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:16.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:16.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:17.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:17.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:17.229 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:17.229 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:17.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:17.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:17.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:17.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:17.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:52:17.235 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:52:17.235 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:52:17.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:52:17.235 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:52:17.235 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:52:17.235 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:52:17.235 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:17.235 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:17.235 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:17.235 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:17.235 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:17.235 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:22.242 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:52:22.242 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:52:22.242 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:52:22.242 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:52:22.242 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:52:22.242 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:52:22.251 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:52:22.253 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:52:22.253 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:22.254 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:52:22.254 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:52:22.258 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:52:22.258 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:52:22.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:52:22.259 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:22.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:52:22.259 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:52:22.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:52:22.259 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:52:22.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:22.262 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:52:22.262 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:52:22.262 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:52:22.262 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:22.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:52:22.263 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:52:22.264 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:52:22.264 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:52:22.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:22.265 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:52:22.265 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:52:22.265 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:52:22.265 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:22.265 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:52:22.265 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:52:22.266 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:52:22.266 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:52:22.266 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:22.268 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:52:22.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:52:22.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:52:22.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:52:22.268 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:52:22.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:52:22.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:52:22.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:52:22.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:52:22.269 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:52:22.269 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:52:22.269 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:22.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:22.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:22.274 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:52:22.757 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:52:22.794 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:52:22.796 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:52:22.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:22.797 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:52:22.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:22.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:22.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:52:22.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:22.821 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:22.821 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:22.821 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:52:22.821 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:52:22.849 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:52:22.854 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 01:52:22.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:22.864 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:22.864 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:22.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:22.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:23.234 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:52:23.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:23.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:23.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:23.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:23.710 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:52:23.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:23.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:23.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:23.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:23.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:23.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:23.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:23.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:23.759 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:52:23.759 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:52:23.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:52:23.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:52:23.759 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:52:23.759 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:52:23.759 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:52:23.759 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=318 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:23.759 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=318 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:23.759 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=318 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:23.759 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=318 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:23.759 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=318 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:23.759 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=318 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:23.759 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=318 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:23.759 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=318 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:28.760 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:52:28.760 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:52:28.761 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:52:28.763 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:52:28.764 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:52:28.764 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:52:28.774 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:52:28.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:52:28.775 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:28.775 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:52:28.775 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:52:28.778 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:52:28.779 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:52:28.779 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:52:28.779 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:28.779 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:52:28.780 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:52:28.780 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:52:28.780 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:52:28.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:28.782 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:52:28.782 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:52:28.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:52:28.782 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:28.782 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:52:28.782 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:52:28.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:52:28.782 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:52:28.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:28.784 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:52:28.784 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:52:28.784 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:52:28.784 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:28.784 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:52:28.784 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:52:28.784 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:52:28.784 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:52:28.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:28.787 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:52:28.787 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:52:28.787 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:52:28.788 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:28.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:28.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:28.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:28.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:28.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:28.792 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:52:29.275 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:52:29.312 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:52:29.314 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:52:29.316 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:52:29.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:29.329 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:29.329 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:29.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:52:29.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:29.333 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:29.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:29.333 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:52:29.333 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:52:29.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:29.380 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:29.380 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:29.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:29.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:29.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:29.753 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:52:29.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:29.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:29.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:29.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:30.231 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:52:30.709 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:52:30.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:30.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:30.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:30.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:31.187 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:52:31.665 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:52:31.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:31.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:31.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:31.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:32.143 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:52:32.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:32.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:32.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:32.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:32.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:32.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:32.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:52:32.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:32.526 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:32.526 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:32.526 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:52:32.526 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:52:32.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:32.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:32.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:32.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:32.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:32.620 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:52:32.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:32.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:32.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:32.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:32.797 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:33.098 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:52:33.578 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:52:33.795 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:33.795 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:33.795 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:33.798 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:34.056 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:52:34.534 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:52:35.013 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:52:35.491 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:52:35.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:35.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:35.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:35.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:35.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:35.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:35.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:52:35.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:35.772 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:35.773 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:35.773 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:52:35.773 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:52:35.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:35.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:35.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:35.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:35.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:35.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:35.968 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:52:36.446 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:52:36.924 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:52:37.401 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:52:37.879 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:52:38.357 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:52:38.834 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:52:38.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:38.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:38.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:38.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:38.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:38.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:38.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:52:38.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:38.985 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:38.985 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:38.985 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:52:38.985 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:52:39.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:39.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:39.028 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:39.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:39.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:39.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:39.311 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:52:39.790 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:52:40.268 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:52:40.745 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:52:41.223 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:52:41.701 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:52:42.178 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:52:42.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:42.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:42.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:42.236 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:42.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:42.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:42.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:42.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:42.250 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:52:42.250 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:52:42.250 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:52:42.250 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:52:42.250 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:52:42.250 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:52:42.251 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:52:42.251 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:42.251 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:42.251 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:42.251 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:42.251 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:42.252 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:42.252 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:52:47.250 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:52:47.250 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:52:47.251 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:52:47.253 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:52:47.253 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:52:47.254 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:52:47.262 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:52:47.264 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:52:47.264 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:47.265 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:52:47.265 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:52:47.267 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:52:47.268 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:52:47.268 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:52:47.268 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:47.269 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:52:47.269 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:52:47.269 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:52:47.270 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:52:47.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:47.270 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:52:47.270 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:52:47.270 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:52:47.270 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:47.271 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:52:47.271 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:52:47.271 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:52:47.271 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:52:47.271 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:47.272 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:52:47.273 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:52:47.273 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:52:47.273 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:52:47.273 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:52:47.273 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:52:47.273 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:52:47.273 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:52:47.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:47.275 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:52:47.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:52:47.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:52:47.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:52:47.275 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:52:47.276 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:52:47.276 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:52:47.276 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:47.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:47.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:52:47.281 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:52:47.764 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:52:47.808 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:52:47.810 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:52:47.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:52:47.812 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:52:47.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:52:47.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:52:47.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:52:47.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:52:47.813 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:52:47.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:52:47.813 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:52:47.813 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:52:48.241 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:52:48.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:48.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:48.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:48.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:48.718 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:52:49.196 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:52:49.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:49.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:49.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:49.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:49.674 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:52:50.151 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:52:50.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:50.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:50.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:50.286 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:50.629 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:52:51.106 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:52:51.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:51.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:51.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:51.286 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:51.584 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:52:52.061 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:52:52.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:52:52.283 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:52:52.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:52:52.288 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:52:52.539 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:52:53.017 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:52:53.494 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:52:53.972 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:52:54.450 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:52:54.927 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:52:55.405 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:52:55.883 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:52:56.361 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:52:56.838 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:52:57.316 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:52:57.794 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:52:58.271 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:52:58.749 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:52:59.227 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:52:59.705 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:53:00.182 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:53:00.660 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:53:01.138 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:53:01.616 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:53:01.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:53:01.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:53:01.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:01.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:01.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:01.906 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:01.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:53:01.907 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:53:01.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:53:01.907 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:53:01.907 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:53:01.907 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:53:01.907 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:53:01.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:01.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:01.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:01.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:01.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:01.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:01.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:06.910 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:53:06.910 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:53:06.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:53:06.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:53:06.915 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:53:06.915 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:53:06.925 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:53:06.926 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:53:06.926 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:53:06.927 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:53:06.927 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:53:06.930 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:53:06.930 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:53:06.931 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:53:06.931 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:53:06.931 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:53:06.932 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:53:06.932 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:53:06.932 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:53:06.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:06.933 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:53:06.933 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:53:06.934 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:53:06.934 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:53:06.934 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:53:06.935 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:53:06.935 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:53:06.935 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:53:06.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:06.936 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:53:06.936 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:53:06.936 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:53:06.936 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:53:06.936 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:53:06.936 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:53:06.936 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:53:06.936 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:53:06.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:06.939 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:53:06.939 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:53:06.939 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:53:06.940 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:06.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:06.944 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:53:07.428 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:53:07.472 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:53:07.475 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:53:07.477 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:53:07.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:53:07.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:53:07.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:53:07.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:53:07.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:53:07.502 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:53:07.503 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:53:07.503 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:53:07.503 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:53:07.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:53:07.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:53:07.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:53:07.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:53:07.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:53:07.905 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:53:07.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:07.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:07.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:07.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:08.382 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:53:08.859 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:53:08.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:08.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:08.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:08.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:09.336 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:53:09.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:53:09.532 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:53:09.532 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:53:09.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:53:09.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:53:09.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:53:09.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:53:09.540 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:53:09.540 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:53:09.811 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:53:09.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:09.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:09.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:09.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:10.289 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:53:10.767 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:53:10.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:10.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:10.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:10.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:11.245 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:53:11.722 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:53:11.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:11.946 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:11.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:11.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:12.200 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:53:12.677 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:53:13.155 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:53:13.632 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:53:14.110 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:53:14.588 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:53:15.065 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:53:15.543 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:53:16.020 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:53:16.498 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:53:16.976 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:53:17.454 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:53:17.931 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:53:18.409 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:53:18.887 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:53:19.365 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:53:19.843 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:53:20.321 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:53:20.798 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:53:21.276 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:53:21.754 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:53:22.232 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:53:22.710 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:53:23.187 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:53:23.664 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:53:24.142 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:53:24.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:53:24.430 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:53:24.430 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:53:24.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:24.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:24.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:24.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:24.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:53:24.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:53:24.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:53:24.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:53:24.444 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:53:24.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:53:24.444 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:53:24.445 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3739 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:24.445 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3739 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:24.445 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3739 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:24.445 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3739 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:24.445 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3739 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:24.445 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3739 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:24.445 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3739 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:29.445 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:53:29.445 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:53:29.446 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:53:29.448 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:53:29.449 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:53:29.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:53:29.459 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:53:29.460 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:53:29.460 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:53:29.460 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:53:29.460 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:53:29.461 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:53:29.462 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:53:29.462 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:53:29.462 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:53:29.462 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:53:29.462 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:53:29.463 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:53:29.463 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:53:29.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:29.464 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:53:29.464 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:53:29.464 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:53:29.464 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:53:29.464 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:53:29.464 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:53:29.464 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:53:29.464 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:53:29.464 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:29.465 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:53:29.465 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:53:29.465 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:53:29.466 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:53:29.466 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:53:29.466 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:53:29.466 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:53:29.466 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:53:29.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:53:29.468 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:53:29.468 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:53:29.468 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:29.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:29.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:29.473 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:53:29.954 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:53:29.993 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:53:29.994 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:53:29.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:53:29.997 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:53:29.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:53:29.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:53:29.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:53:30.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:53:30.000 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:53:30.000 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:53:30.000 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:53:30.000 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:53:30.432 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:53:30.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:30.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:30.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:30.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:30.909 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:53:31.387 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:53:31.471 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:31.471 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:31.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:31.475 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:31.865 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:53:32.343 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:53:32.472 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:32.472 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:32.473 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:32.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:32.820 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:53:33.298 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:53:33.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:33.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:33.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:33.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:33.776 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:53:34.253 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:53:34.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:34.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:34.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:34.477 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:34.731 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:53:35.208 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:53:35.686 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:53:36.164 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:53:36.642 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:53:37.120 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:53:37.597 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:53:38.074 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:53:38.551 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:53:39.029 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:53:39.506 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:53:39.984 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:53:40.462 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:53:40.939 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:53:41.417 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:53:41.895 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:53:42.372 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:53:42.850 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:53:43.328 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:53:43.806 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:53:44.283 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:53:44.761 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:53:45.239 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:53:45.716 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:53:46.194 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:53:46.672 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:53:47.149 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:53:47.627 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:53:48.105 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:53:48.583 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:53:49.060 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:53:49.538 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:53:50.015 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:53:50.493 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:53:50.971 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:53:51.449 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:53:51.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:53:51.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:53:51.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:51.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:51.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:51.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:51.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:53:51.495 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:53:51.496 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:53:51.496 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:53:51.496 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:53:51.496 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:53:51.496 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:53:51.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4704 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:51.497 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4704 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:51.497 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4704 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:51.497 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4704 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:51.497 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4704 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:51.497 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4704 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:51.497 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4704 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:53:56.495 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:53:56.495 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:53:56.496 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:53:56.497 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:53:56.498 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:53:56.498 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:53:56.505 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:53:56.506 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:53:56.507 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:53:56.507 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:53:56.507 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:53:56.511 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:53:56.511 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:53:56.512 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:53:56.512 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:53:56.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:53:56.514 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:53:56.514 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:53:56.514 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:53:56.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:56.516 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:53:56.516 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:53:56.517 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:53:56.517 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:53:56.517 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:53:56.518 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:53:56.518 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:53:56.518 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:53:56.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:56.519 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:53:56.519 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:53:56.520 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:53:56.520 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:53:56.520 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:53:56.520 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:53:56.520 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:53:56.520 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:53:56.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:56.524 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:53:56.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:53:56.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:53:56.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:53:56.524 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:53:56.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:53:56.524 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:53:56.524 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:53:56.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:53:56.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:56.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:56.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:56.525 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:53:56.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:56.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:56.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:56.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:56.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:56.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:56.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:56.525 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:53:56.525 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:53:56.525 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:53:56.525 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:53:56.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:56.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:53:56.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:56.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:53:56.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:56.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:56.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:56.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:53:56.530 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:53:57.012 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:53:57.057 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:53:57.058 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:53:57.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:53:57.060 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:53:57.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:53:57.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:53:57.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:53:57.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:53:57.065 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:53:57.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:53:57.066 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:53:57.066 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:53:57.490 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:53:57.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:57.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:57.531 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:57.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:57.967 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:53:58.444 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:53:58.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:58.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:58.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:58.537 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:58.922 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:53:59.399 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:53:59.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:53:59.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:53:59.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:53:59.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:53:59.877 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:54:00.355 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:54:00.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:54:00.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:54:00.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:54:00.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:54:00.833 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:54:01.311 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:54:01.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:54:01.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:54:01.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:54:01.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:54:01.788 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:54:02.266 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:54:02.744 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:54:03.222 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:54:03.699 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:54:04.177 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:54:04.655 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:54:05.132 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:54:05.609 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:54:06.087 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:54:06.565 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:54:07.042 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:54:07.520 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:54:07.998 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:54:08.475 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:54:08.952 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:54:09.430 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:54:09.908 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:54:10.386 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:54:10.876 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:54:11.354 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:54:11.832 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:54:12.309 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:54:12.787 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:54:13.266 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:54:13.744 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:54:14.221 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:54:14.698 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:54:15.176 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:54:15.654 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:54:16.131 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:54:16.609 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:54:17.087 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:54:17.565 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:54:18.042 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:54:18.520 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:54:18.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:54:18.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:54:18.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:54:18.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:54:18.551 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:54:18.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:54:18.554 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:54:18.554 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:54:18.554 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:54:18.554 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:54:18.554 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:54:18.554 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:54:18.554 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:54:18.554 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4701 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:54:18.554 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4701 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:54:18.554 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4701 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:54:18.554 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4701 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:54:18.554 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4701 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:54:18.554 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4701 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:54:23.558 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:54:23.559 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:54:23.559 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:54:23.559 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:54:23.559 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:54:23.559 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:54:23.566 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:54:23.568 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:54:23.568 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:54:23.569 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:54:23.569 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:54:23.572 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:54:23.572 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:54:23.572 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:54:23.572 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:54:23.573 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:54:23.573 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:54:23.573 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:54:23.573 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:54:23.573 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:54:23.576 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:54:23.576 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:54:23.576 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:54:23.577 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:54:23.577 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:54:23.577 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:54:23.578 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:54:23.578 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:54:23.578 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:54:23.579 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:54:23.579 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:54:23.579 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:54:23.579 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:54:23.579 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:54:23.579 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:54:23.579 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:54:23.579 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:54:23.579 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:54:23.582 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:54:23.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:54:23.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:54:23.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:54:23.582 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:54:23.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:54:23.583 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:54:23.583 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:54:23.583 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:54:23.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:54:23.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:54:23.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:54:23.588 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:54:24.072 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:54:24.112 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:54:24.114 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:54:24.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:54:24.116 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:54:24.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:54:24.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:54:24.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:54:24.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:54:24.120 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:54:24.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:54:24.120 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:54:24.120 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:54:24.549 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:54:24.586 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:54:24.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:54:24.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:54:24.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:54:25.027 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:54:25.504 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:54:25.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:54:25.588 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:54:25.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:54:25.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:54:25.982 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:54:26.460 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:54:26.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:54:26.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:54:26.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:54:26.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:54:26.937 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:54:27.415 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:54:27.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:54:27.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:54:27.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:54:27.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:54:27.893 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:54:28.371 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:54:28.591 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:54:28.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:54:28.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:54:28.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:54:28.848 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:54:29.326 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:54:29.803 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:54:30.281 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:54:30.759 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:54:31.237 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:54:31.714 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:54:32.192 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:54:32.670 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:54:33.148 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:54:33.625 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:54:34.103 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:54:34.581 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:54:35.058 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:54:35.536 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:54:36.014 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:54:36.492 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:54:36.969 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:54:37.447 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:54:37.924 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:54:38.402 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:54:38.879 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:54:39.357 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:54:39.835 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:54:40.312 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:54:40.790 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:54:41.268 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:54:41.745 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:54:42.223 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:54:42.701 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:54:43.179 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:54:43.657 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:54:44.135 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:54:44.612 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:54:45.090 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:54:45.568 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:54:46.046 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:54:46.524 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:54:47.002 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:54:47.480 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:54:47.958 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:54:48.436 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:54:48.913 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:54:49.391 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:54:49.869 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:54:50.347 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:54:50.825 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:54:51.302 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:54:51.780 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 01:54:52.258 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 01:54:52.736 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 01:54:53.213 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 01:54:53.690 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 01:54:54.168 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 01:54:54.646 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 01:54:55.124 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 01:54:55.601 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 01:54:56.079 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 01:54:56.557 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 01:54:57.034 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 01:54:57.512 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 01:54:57.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:54:57.605 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:54:57.609 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:54:57.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:54:57.609 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:54:57.609 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:54:57.612 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:54:57.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:54:57.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:54:57.613 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:54:57.613 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:54:57.613 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:54:57.613 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:54:57.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7265 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:54:57.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7265 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:54:57.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7265 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:54:57.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7265 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:54:57.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7265 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:54:57.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7265 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:02.614 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:55:02.614 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:55:02.614 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:02.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:02.614 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:02.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:02.617 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:02.618 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:55:02.618 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:02.619 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:55:02.619 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:55:02.621 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:55:02.621 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:55:02.622 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:55:02.622 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:02.622 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:02.622 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:55:02.623 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:55:02.623 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:55:02.623 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:02.624 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:55:02.624 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:55:02.624 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:55:02.624 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:02.624 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:02.624 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:55:02.625 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:55:02.625 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:55:02.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:02.626 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:55:02.626 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:55:02.626 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:55:02.626 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:02.627 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:02.627 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:55:02.627 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:55:02.627 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:55:02.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:02.629 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:55:02.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:02.630 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:55:02.630 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:55:02.630 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:55:02.631 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:02.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:02.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:02.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:02.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:02.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:02.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:02.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:02.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:02.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:02.635 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:55:03.116 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:55:03.160 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:55:03.162 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:55:03.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:55:03.164 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:55:03.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:55:03.167 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:55:03.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:55:03.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:55:03.167 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:55:03.168 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:55:03.168 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:55:03.168 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:55:03.593 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:55:03.634 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:03.634 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:03.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:03.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:04.071 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:55:04.549 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:55:04.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:04.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:04.636 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:04.641 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:05.027 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:55:05.505 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:55:05.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:05.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:05.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:05.641 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:05.983 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:55:06.461 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:55:06.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:06.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:06.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:06.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:06.938 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:55:07.416 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:55:07.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:07.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:07.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:07.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:07.894 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:55:08.371 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:55:08.848 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:55:09.326 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:55:09.804 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:55:10.281 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:55:10.758 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:55:11.236 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:55:11.714 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:55:12.191 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:55:12.669 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:55:13.147 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:55:13.625 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:55:14.102 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:55:14.580 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:55:15.058 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:55:15.535 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:55:16.013 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:55:16.490 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:55:16.968 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:55:17.446 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:55:17.924 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:55:18.402 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:55:18.880 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:55:19.357 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:55:19.835 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:55:20.313 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:55:20.791 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:55:21.269 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:55:21.747 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:55:22.225 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:55:22.702 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:55:23.180 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:55:23.658 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:55:24.135 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:55:24.613 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:55:25.091 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:55:25.568 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:55:26.046 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:55:26.523 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:55:27.001 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:55:27.479 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:55:27.957 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:55:28.435 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:55:28.912 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:55:29.390 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:55:29.868 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:55:30.345 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:55:30.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:55:30.651 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:55:30.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:30.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:30.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:30.656 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:30.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:30.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:30.658 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:30.658 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:55:30.658 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:55:30.658 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:55:30.658 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:35.658 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:55:35.659 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:55:35.660 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:35.662 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:35.663 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:35.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:35.670 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:35.671 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:55:35.671 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:35.671 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:55:35.671 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:55:35.674 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:55:35.674 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:55:35.675 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:55:35.675 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:35.675 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:35.675 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:55:35.675 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:55:35.675 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:55:35.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:35.677 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:55:35.678 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:55:35.678 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:55:35.678 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:35.678 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:35.678 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:55:35.678 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:55:35.678 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:55:35.678 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:35.680 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:55:35.680 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:55:35.680 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:55:35.680 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:35.680 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:35.680 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:55:35.681 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:55:35.681 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:55:35.681 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:35.683 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:55:35.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:55:35.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:55:35.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:55:35.683 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:55:35.684 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:55:35.684 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:55:35.684 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:55:35.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:35.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:35.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:35.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:35.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:35.689 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:55:36.170 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:55:36.201 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:55:36.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:55:36.202 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:55:36.203 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:55:36.210 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:36.210 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:36.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:36.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:36.214 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:36.214 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:36.214 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:36.214 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:55:36.214 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:55:36.214 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:55:36.215 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:36.215 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=113 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:36.215 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=113 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:36.215 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=113 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:36.215 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=113 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:36.215 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=113 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:36.215 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=113 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:36.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=113 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.214 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:55:41.214 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:55:41.218 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:41.218 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:41.218 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:41.218 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:41.226 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:41.228 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:55:41.228 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:41.229 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:55:41.229 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:55:41.233 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:55:41.233 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:55:41.233 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:55:41.233 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:41.234 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:41.234 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:55:41.234 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:55:41.234 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:55:41.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:41.237 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:55:41.237 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:55:41.237 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:55:41.237 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:41.237 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:41.237 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:55:41.237 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:55:41.237 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:55:41.237 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:41.240 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:55:41.240 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:55:41.240 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:55:41.240 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:41.240 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:41.240 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:55:41.240 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:55:41.240 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:55:41.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:41.243 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:55:41.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:55:41.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:55:41.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:55:41.243 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:55:41.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:55:41.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:55:41.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:55:41.244 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:55:41.244 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:55:41.244 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:41.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:41.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:41.249 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:55:41.733 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:55:41.778 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:55:41.780 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:55:41.781 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:55:41.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:55:41.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:41.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:41.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:41.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:41.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:41.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:41.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:41.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:41.794 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:55:41.794 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:55:41.794 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:55:41.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:41.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:46.795 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:55:46.795 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:55:46.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:46.797 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:46.798 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:46.798 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:46.806 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:46.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:55:46.807 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:46.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:55:46.807 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:55:46.810 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:55:46.810 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:55:46.810 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:55:46.811 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:46.811 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:46.811 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:55:46.812 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:55:46.812 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:55:46.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:46.812 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:55:46.812 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:55:46.812 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:55:46.812 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:46.813 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:46.813 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:55:46.813 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:55:46.813 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:55:46.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:46.814 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:55:46.815 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:55:46.815 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:55:46.815 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:46.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:46.815 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:55:46.815 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:55:46.815 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:55:46.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:46.817 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:55:46.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:55:46.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:55:46.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:55:46.817 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:55:46.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:55:46.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:55:46.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:55:46.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:55:46.818 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:55:46.818 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:55:46.818 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:46.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:46.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:46.823 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:55:47.304 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:55:47.337 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:55:47.338 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:55:47.339 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:55:47.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:55:47.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:47.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:47.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:47.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:47.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:47.348 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:47.349 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:47.349 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:47.349 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:55:47.349 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:55:47.349 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:55:47.349 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=113 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:47.350 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=113 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:47.350 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=113 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:47.350 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=113 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:47.350 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=113 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:47.350 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=113 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:55:52.349 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:55:52.349 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:55:52.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:52.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:52.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:52.351 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:52.357 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:55:52.358 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:55:52.359 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:52.359 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:55:52.359 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:55:52.363 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:55:52.363 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:55:52.363 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:55:52.363 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:52.364 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:55:52.364 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:55:52.364 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:55:52.364 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:55:52.364 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:52.367 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:55:52.367 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:55:52.367 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:55:52.367 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:52.367 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:55:52.367 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:55:52.367 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:55:52.368 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:55:52.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:52.370 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:55:52.370 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:55:52.370 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:55:52.370 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:55:52.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:55:52.371 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:55:52.371 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:55:52.371 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:55:52.371 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:52.374 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:55:52.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:55:52.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:55:52.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:55:52.374 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:55:52.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:55:52.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:55:52.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:55:52.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:55:52.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:52.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:55:52.375 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:55:52.375 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:55:52.375 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:52.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:52.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:55:52.380 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:55:52.860 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:55:52.906 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:55:52.908 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:55:52.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:55:52.910 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:55:52.912 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:55:52.912 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:55:52.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:55:52.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:55:52.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:55:52.912 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:55:52.912 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:55:52.912 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:55:53.333 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:55:53.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:53.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:53.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:53.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:53.810 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:55:54.288 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:55:54.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:54.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:54.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:54.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:54.766 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:55:55.243 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:55:55.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:55.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:55.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:55.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:55.721 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:55:56.199 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:55:56.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:56.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:56.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:56.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:56.676 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:55:57.154 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:55:57.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:55:57.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:55:57.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:55:57.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:55:57.632 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:55:58.110 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:55:58.588 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:55:59.065 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:55:59.544 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:56:00.021 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:56:00.499 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:56:00.955 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:56:00.955 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:56:00.957 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:00.958 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:00.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:00.958 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:00.961 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:56:00.961 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:56:00.961 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:56:00.961 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:56:00.961 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:56:00.961 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:56:00.961 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:56:00.961 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.961 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.961 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.961 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.961 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.961 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.961 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:00.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:05.961 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:56:05.962 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:56:05.963 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:56:05.965 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:56:05.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:56:05.969 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:56:05.976 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:56:05.977 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:56:05.977 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:05.977 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:56:05.977 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:56:05.981 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:56:05.981 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:56:05.981 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:56:05.981 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:05.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:56:05.982 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:56:05.982 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:56:05.982 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:56:05.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:05.984 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:56:05.985 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:56:05.985 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:56:05.985 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:05.985 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:56:05.985 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:56:05.985 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:56:05.985 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:56:05.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:05.987 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:56:05.987 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:56:05.987 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:56:05.987 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:05.988 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:56:05.988 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:56:05.988 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:56:05.988 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:56:05.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:05.991 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:56:05.992 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:56:05.992 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:56:05.992 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:56:05.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:05.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:05.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:05.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:56:05.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:05.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:05.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:05.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:05.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:05.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:05.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:05.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:05.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:05.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:05.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:05.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:05.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:05.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:05.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:05.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:05.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:05.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:05.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:05.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:05.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:05.996 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:56:06.478 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:56:06.522 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:56:06.524 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:56:06.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:56:06.526 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:56:06.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:56:06.529 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:56:06.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:56:06.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:56:06.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:56:06.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:56:06.531 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:56:06.531 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:56:06.955 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:56:06.995 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:06.995 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:06.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:06.999 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:07.433 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:56:07.910 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:56:07.996 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:07.996 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:07.997 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:08.000 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:08.387 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:56:08.864 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:56:08.997 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:08.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:08.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:09.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:09.342 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:56:09.819 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:56:09.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:09.998 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:09.999 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:10.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:10.297 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:56:10.775 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:56:10.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:10.998 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:11.001 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:11.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:11.253 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:56:11.731 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:56:12.209 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:56:12.687 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:56:13.165 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:56:13.642 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:56:14.120 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:56:14.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:56:14.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:56:14.582 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:14.583 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:14.583 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:14.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:14.586 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:56:14.587 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:56:14.587 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:56:14.587 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:56:14.587 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:56:14.587 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:56:14.587 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:56:14.587 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.588 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.589 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.589 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:14.589 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:19.587 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:56:19.587 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:56:19.588 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:56:19.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:56:19.590 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:56:19.591 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:56:19.595 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:56:19.597 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:56:19.597 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:19.597 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:56:19.597 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:56:19.601 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:56:19.601 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:56:19.601 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:56:19.602 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:19.602 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:56:19.602 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:56:19.602 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:56:19.603 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:56:19.603 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:19.604 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:56:19.604 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:56:19.604 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:56:19.604 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:19.604 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:56:19.604 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:56:19.605 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:56:19.605 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:56:19.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:19.606 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:56:19.606 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:56:19.606 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:56:19.606 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:19.606 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:56:19.606 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:56:19.606 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:56:19.607 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:56:19.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:19.609 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:56:19.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:56:19.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:56:19.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:56:19.609 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:56:19.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:56:19.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:56:19.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:56:19.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:56:19.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:19.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:56:19.610 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:56:19.610 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:56:19.610 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:19.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:19.611 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:19.611 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:19.611 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:19.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:19.611 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:19.611 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:19.611 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:19.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:19.611 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:19.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:19.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:19.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:19.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:19.615 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:56:20.097 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:56:20.142 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:56:20.144 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:56:20.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:56:20.147 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:56:20.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:56:20.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:56:20.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:56:20.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:56:20.152 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:56:20.152 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:56:20.152 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:56:20.152 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:56:20.575 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:56:20.612 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:20.613 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:20.613 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:20.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:21.053 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:56:21.531 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:56:21.613 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:21.614 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:21.614 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:21.618 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:22.009 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:56:22.486 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:56:22.614 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:22.614 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:22.615 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:22.619 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:22.964 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:56:23.442 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:56:23.615 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:23.616 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:23.616 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:23.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:23.920 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:56:24.397 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:56:24.616 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:24.616 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:24.617 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:24.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:24.875 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:56:25.353 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:56:25.830 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:56:26.308 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:56:26.786 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:56:27.263 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:56:27.741 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:56:28.193 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:56:28.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:56:28.197 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:28.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:28.197 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:28.197 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:28.199 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:56:28.199 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:56:28.199 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:56:28.199 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:56:28.199 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:56:28.199 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:56:28.199 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:56:28.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:28.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:28.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:28.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:28.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:28.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:28.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:28.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:33.200 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:56:33.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:56:33.202 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:56:33.206 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:56:33.206 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:56:33.207 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:56:33.214 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:56:33.215 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:56:33.215 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:33.215 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:56:33.216 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:56:33.219 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:56:33.219 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:56:33.219 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:56:33.219 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:33.219 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:56:33.219 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:56:33.220 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:56:33.220 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:56:33.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:33.222 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:56:33.222 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:56:33.222 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:56:33.223 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:33.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:56:33.223 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:56:33.223 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:56:33.223 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:56:33.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:33.227 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:56:33.227 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:56:33.227 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:56:33.227 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:33.227 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:56:33.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:56:33.227 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:56:33.227 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:56:33.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:33.231 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:56:33.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:56:33.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:56:33.231 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:56:33.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:56:33.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:56:33.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:56:33.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:56:33.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:56:33.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:33.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:33.231 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:56:33.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:33.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:33.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:33.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:33.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:33.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:33.232 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:56:33.232 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:56:33.232 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:56:33.232 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:56:33.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:33.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:33.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:33.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:56:33.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:33.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:33.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:33.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:33.237 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:56:33.721 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:56:33.760 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:56:33.762 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:56:33.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:56:33.765 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:56:33.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:56:33.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:56:33.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:56:33.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:56:33.770 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:56:33.770 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:56:33.770 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:56:33.770 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:56:34.198 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:56:34.236 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:34.236 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:34.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:34.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:34.676 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:56:35.154 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:56:35.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:35.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:35.240 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:35.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:35.631 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:56:36.109 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:56:36.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:36.239 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:36.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:36.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:36.587 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:56:37.064 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:56:37.240 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:37.240 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:37.242 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:37.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:37.542 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:56:38.020 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:56:38.240 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:38.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:38.243 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:38.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:38.498 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:56:38.976 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:56:39.453 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:56:39.932 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:56:40.406 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:56:40.884 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:56:41.361 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:56:41.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:56:41.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:56:41.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:41.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:41.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:41.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:41.823 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:56:41.823 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:56:41.823 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:56:41.823 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:56:41.823 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:56:41.823 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:56:41.823 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:56:41.823 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.823 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.823 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.823 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.823 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.824 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.824 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.824 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.824 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.824 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.824 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.824 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.824 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.824 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.824 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:41.824 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:46.822 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:56:46.823 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:56:46.824 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:56:46.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:56:46.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:56:46.830 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:56:46.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:56:46.845 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:56:46.845 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:46.845 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:56:46.846 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:56:46.849 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:56:46.849 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:56:46.850 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:56:46.850 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:46.850 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:56:46.851 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:56:46.851 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:56:46.851 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:56:46.851 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:46.852 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:56:46.852 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:56:46.852 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:56:46.852 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:46.852 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:56:46.852 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:56:46.852 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:56:46.852 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:56:46.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:46.854 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:56:46.854 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:56:46.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:56:46.854 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:56:46.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:56:46.854 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:56:46.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:56:46.854 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:56:46.855 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:46.857 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:56:46.857 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:56:46.857 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:56:46.858 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:46.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:56:46.862 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:56:47.346 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:56:47.385 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:56:47.387 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:56:47.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:56:47.389 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:56:47.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:56:47.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:56:47.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:56:47.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:56:47.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:56:47.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:56:47.396 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:56:47.396 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:56:47.823 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:56:47.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:47.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:47.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:47.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:48.301 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:56:48.779 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:56:48.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:48.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:48.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:48.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:49.256 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:56:49.734 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:56:49.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:49.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:49.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:49.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:50.211 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:56:50.689 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:56:50.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:50.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:50.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:50.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:51.167 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:56:51.645 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:56:51.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:51.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:51.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:51.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:52.123 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:56:52.600 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:56:53.078 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:56:53.555 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:56:54.033 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:56:54.511 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:56:54.989 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:56:55.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:56:55.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:56:55.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:56:55.450 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:56:55.450 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:56:55.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:56:55.453 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:56:55.453 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:56:55.453 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:56:55.453 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:56:55.453 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:56:55.453 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:56:55.453 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:56:55.453 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:55.453 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:55.453 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:55.453 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:55.453 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:55.453 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:56:55.453 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:00.453 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:57:00.454 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:57:00.455 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:57:00.456 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:57:00.456 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:57:00.456 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:57:00.465 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:57:00.467 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:57:00.467 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:00.467 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:57:00.467 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:57:00.470 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:57:00.470 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:57:00.471 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:57:00.471 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:00.471 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:57:00.472 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:57:00.472 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:57:00.472 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:57:00.473 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:00.473 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:57:00.473 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:57:00.473 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:57:00.474 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:00.474 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:57:00.474 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:57:00.474 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:57:00.474 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:57:00.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:00.475 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:57:00.476 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:57:00.476 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:57:00.476 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:00.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:57:00.476 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:57:00.476 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:57:00.476 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:57:00.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:00.478 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:57:00.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:57:00.479 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:57:00.479 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:57:00.479 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:57:00.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:00.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:00.484 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:57:00.968 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:57:01.006 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:57:01.008 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:57:01.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:57:01.010 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:57:01.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:57:01.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:57:01.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:57:01.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:57:01.014 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:57:01.014 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:57:01.015 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:57:01.015 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:57:01.445 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:57:01.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:01.483 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:01.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:01.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:01.923 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:57:02.401 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:57:02.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:02.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:02.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:02.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:02.878 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:57:03.356 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:57:03.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:03.486 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:03.486 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:03.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:03.834 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:57:04.312 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:57:04.486 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:04.486 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:04.487 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:04.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:04.789 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:57:05.265 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:57:05.487 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:05.487 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:05.487 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:05.488 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:05.742 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:57:06.220 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:57:06.698 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:57:07.175 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:57:07.652 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:57:08.129 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:57:08.606 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:57:09.083 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:57:09.560 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:57:10.038 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:57:10.516 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:57:10.993 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:57:11.471 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:57:11.949 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:57:12.427 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:57:12.901 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:57:13.379 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:57:13.857 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:57:14.334 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:57:14.812 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:57:15.289 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:57:15.767 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:57:16.245 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:57:16.723 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:57:17.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:57:17.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:57:17.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:17.078 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:17.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:17.078 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:17.081 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:57:17.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:57:17.082 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:57:17.082 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:57:17.082 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:57:17.082 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:57:17.082 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:57:17.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3547 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:17.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3547 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:17.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3547 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:17.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3547 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:17.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3547 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:17.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3547 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:22.081 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:57:22.081 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:57:22.083 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:57:22.084 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:57:22.084 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:57:22.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:57:22.092 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:57:22.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:57:22.093 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:22.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:57:22.093 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:57:22.095 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:57:22.095 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:57:22.095 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:57:22.096 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:22.096 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:57:22.096 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:57:22.096 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:57:22.096 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:57:22.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:22.098 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:57:22.098 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:57:22.098 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:57:22.098 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:22.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:57:22.098 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:57:22.098 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:57:22.098 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:57:22.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:22.100 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:57:22.100 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:57:22.100 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:57:22.100 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:22.100 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:57:22.101 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:57:22.101 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:57:22.101 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:57:22.101 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:22.103 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:57:22.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:57:22.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:57:22.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:57:22.103 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:57:22.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:57:22.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:57:22.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:57:22.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:57:22.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:22.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:22.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:22.103 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:57:22.104 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:57:22.104 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:57:22.104 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:22.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:22.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:22.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:22.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:22.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:22.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:22.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:22.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:22.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:22.109 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:57:22.592 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:57:22.631 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:57:22.632 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:57:22.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:57:22.634 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:57:22.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:57:22.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:57:22.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:57:22.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:57:22.643 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:57:22.643 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:57:22.643 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:57:22.643 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:57:23.069 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:57:23.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:23.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:23.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:23.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:23.546 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:57:24.024 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:57:24.107 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:24.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:24.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:24.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:24.502 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:57:24.979 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:57:25.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:25.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:25.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:25.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:25.457 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:57:25.935 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:57:26.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:26.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:26.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:26.114 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:26.412 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:57:26.890 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:57:27.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:27.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:27.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:27.114 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:27.368 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:57:27.846 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:57:28.324 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:57:28.801 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:57:29.279 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:57:29.757 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:57:30.235 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:57:30.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:57:30.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:57:30.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:30.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:30.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:30.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:30.696 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:57:30.696 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:57:30.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:57:30.696 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:57:30.696 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:57:30.696 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:57:30.696 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:57:35.699 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:57:35.699 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:57:35.700 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:57:35.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:57:35.703 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:57:35.703 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:57:35.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:57:35.712 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:57:35.712 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:35.713 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:57:35.713 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:57:35.715 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:57:35.716 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:57:35.716 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:57:35.716 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:35.717 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:57:35.717 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:57:35.717 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:57:35.718 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:57:35.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:35.718 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:57:35.718 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:57:35.719 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:57:35.719 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:35.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:57:35.719 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:57:35.719 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:57:35.719 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:57:35.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:35.720 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:57:35.720 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:57:35.720 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:57:35.720 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:35.720 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:57:35.720 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:57:35.720 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:57:35.720 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:57:35.720 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:35.722 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:57:35.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:57:35.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:57:35.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:57:35.722 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:57:35.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:57:35.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:57:35.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:57:35.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:57:35.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:57:35.723 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:57:35.723 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:57:35.723 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:35.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:35.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:35.728 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:57:36.210 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:57:36.255 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:57:36.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:57:36.258 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:57:36.260 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:57:36.269 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:57:36.269 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:57:36.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:57:36.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:57:36.270 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:57:36.270 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:57:36.271 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:57:36.271 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:57:36.688 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:57:36.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:36.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:36.726 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:36.730 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:37.166 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:57:37.643 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:57:37.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:37.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:37.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:37.731 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:38.121 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:57:38.599 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:57:38.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:38.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:38.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:38.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:39.077 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:57:39.555 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:57:39.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:39.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:39.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:39.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:40.032 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:57:40.510 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:57:40.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:40.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:40.730 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:40.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:40.987 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:57:41.465 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:57:41.943 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:57:42.420 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:57:42.898 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:57:43.375 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:57:43.853 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:57:44.331 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:57:44.809 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:57:45.286 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:57:45.764 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:57:46.242 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:57:46.719 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:57:47.196 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:57:47.674 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:57:48.152 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:57:48.630 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:57:49.107 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:57:49.585 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:57:50.063 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:57:50.540 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:57:51.018 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:57:51.496 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:57:51.974 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:57:52.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:57:52.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:57:52.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:52.317 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:52.317 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:52.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:52.320 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:57:52.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:57:52.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:57:52.320 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:57:52.320 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:57:52.320 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:57:52.320 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:57:52.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3545 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:52.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3545 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:52.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3545 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:52.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3545 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:52.321 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3545 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:52.321 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3545 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:52.321 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3545 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:57.321 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:57:57.321 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:57:57.324 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:57:57.324 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:57:57.324 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:57:57.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:57:57.337 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:57:57.337 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:57:57.338 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:57.338 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:57:57.338 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:57:57.340 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:57:57.340 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:57:57.340 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:57:57.340 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:57.340 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:57:57.340 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:57:57.340 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:57:57.340 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:57:57.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:57.342 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:57:57.342 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:57:57.342 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:57:57.342 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:57.342 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:57:57.342 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:57:57.342 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:57:57.342 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:57:57.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:57.344 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:57:57.344 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:57:57.344 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:57:57.344 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:57:57.344 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:57:57.344 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:57:57.344 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:57:57.344 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:57:57.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:57.345 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:57:57.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:57:57.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:57:57.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:57:57.345 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:57:57.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:57:57.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:57:57.346 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:57:57.346 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:57:57.346 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:57:57.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:57:57.350 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:57:57.834 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:57:57.868 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:57:57.870 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:57:57.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:57:57.872 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:57:57.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:57:57.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:57:57.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:57:57.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:57:57.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:57:57.897 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:57:57.897 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:57:57.899 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:57:57.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:57:57.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:57:57.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:57:57.900 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:57:57.900 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:57:57.900 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:57:57.901 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:57.901 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:57.901 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:57.901 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:57.901 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:57.901 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:57:57.901 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:02.900 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:58:02.901 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:58:02.902 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:02.903 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:02.903 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:02.904 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:02.909 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:02.910 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:58:02.911 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:02.911 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:58:02.911 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:58:02.915 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:58:02.915 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:58:02.915 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:58:02.915 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:02.915 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:02.915 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:58:02.915 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:58:02.915 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:58:02.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:02.918 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:58:02.918 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:58:02.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:58:02.918 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:02.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:02.918 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:58:02.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:58:02.918 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:58:02.919 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:02.920 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:58:02.920 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:58:02.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:58:02.920 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:02.921 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:02.921 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:58:02.921 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:58:02.921 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:58:02.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:02.923 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:58:02.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:58:02.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:58:02.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:58:02.923 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:58:02.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:58:02.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:58:02.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:58:02.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:58:02.924 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:58:02.924 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:58:02.924 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:02.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:02.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:02.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:02.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:02.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:02.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:02.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:02.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:02.929 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:58:03.412 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:58:03.459 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:58:03.461 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:58:03.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:58:03.465 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:58:03.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:58:03.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:58:03.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:58:03.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:03.523 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:03.523 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:03.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:03.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:03.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:03.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:03.527 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:03.527 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:58:03.527 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:58:03.527 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:58:03.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:03.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:03.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:03.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:03.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:03.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:03.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:03.529 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:03.529 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:03.529 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:03.529 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:03.529 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:08.525 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:58:08.526 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:58:08.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:08.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:08.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:08.529 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:08.531 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:08.532 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:58:08.532 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:08.532 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:58:08.532 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:58:08.532 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:58:08.533 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:58:08.533 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:58:08.533 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:08.533 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:08.533 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:58:08.533 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:58:08.533 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:58:08.534 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:08.535 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:58:08.535 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:58:08.535 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:58:08.535 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:08.535 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:08.535 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:58:08.535 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:58:08.535 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:58:08.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:08.537 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:58:08.537 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:58:08.537 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:58:08.537 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:08.537 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:08.537 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:58:08.537 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:58:08.537 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:58:08.537 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:08.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:58:08.541 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:58:08.541 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:58:08.541 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:08.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:08.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:08.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:08.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:08.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:08.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:08.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:08.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:08.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:08.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:08.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:08.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:08.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:08.546 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:58:09.029 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:58:09.066 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:58:09.066 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:58:09.067 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:58:09.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:58:09.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:58:09.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:58:09.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:58:09.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:09.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:09.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:09.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:09.104 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:09.104 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:09.104 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:09.104 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:09.104 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:58:09.104 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:58:09.104 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:58:09.104 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:09.104 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:09.104 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:09.104 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:09.104 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:09.104 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:09.104 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:09.105 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:09.105 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:09.105 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:09.105 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:09.105 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:09.105 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:09.105 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:14.105 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:58:14.105 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:58:14.107 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:14.108 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:14.108 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:14.108 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:14.117 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:14.119 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:58:14.119 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:14.120 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:58:14.120 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:58:14.123 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:58:14.123 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:58:14.124 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:58:14.124 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:14.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:14.125 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:58:14.125 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:58:14.125 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:58:14.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:14.126 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:58:14.126 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:58:14.126 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:58:14.127 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:14.127 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:14.127 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:58:14.127 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:58:14.127 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:58:14.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:14.128 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:58:14.128 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:58:14.128 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:58:14.128 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:14.128 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:14.129 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:58:14.129 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:58:14.129 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:58:14.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:58:14.131 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:58:14.131 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:58:14.131 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:14.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:14.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:14.136 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:58:14.620 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:58:14.657 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:58:14.659 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:58:14.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:58:14.661 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:58:14.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:58:14.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:58:14.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:58:14.713 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:14.713 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:14.713 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:14.713 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:14.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:14.717 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:14.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:14.717 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:58:14.717 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:58:14.717 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:58:14.718 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:14.718 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:14.718 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:14.718 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:14.718 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:14.718 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:14.718 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:14.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:14.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:19.716 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:58:19.717 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:58:19.720 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:19.720 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:19.720 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:19.720 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:19.726 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:19.728 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:58:19.728 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:19.729 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:58:19.729 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:58:19.732 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:58:19.733 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:58:19.733 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:58:19.733 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:19.733 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:19.733 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:58:19.734 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:58:19.734 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:58:19.734 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:19.736 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:58:19.736 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:58:19.736 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:58:19.736 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:19.737 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:19.737 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:58:19.737 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:58:19.737 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:58:19.737 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:19.739 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:58:19.739 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:58:19.739 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:58:19.740 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:19.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:19.740 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:58:19.740 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:58:19.740 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:58:19.740 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:19.743 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:58:19.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:58:19.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:58:19.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:58:19.743 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:58:19.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:58:19.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:58:19.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:58:19.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:58:19.744 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:58:19.744 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:58:19.744 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:19.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:19.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:19.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:19.749 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:58:20.233 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:58:20.281 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:58:20.283 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:58:20.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:58:20.286 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:58:20.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:58:20.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:58:20.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:58:20.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:58:20.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:58:20.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:58:20.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:20.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:20.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:20.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:20.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:20.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:20.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:20.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:20.330 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:58:20.330 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:58:20.330 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:58:20.330 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:20.330 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:20.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:20.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:20.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:20.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:20.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:25.333 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:58:25.334 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:58:25.335 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:25.337 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:25.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:25.338 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:25.346 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:25.347 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:58:25.347 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:25.348 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:58:25.348 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:58:25.351 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:58:25.351 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:58:25.352 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:58:25.352 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:25.352 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:25.353 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:58:25.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:58:25.353 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:58:25.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:25.354 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:58:25.354 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:58:25.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:58:25.354 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:25.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:25.354 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:58:25.355 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:58:25.355 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:58:25.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:25.356 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:58:25.356 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:58:25.357 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:58:25.357 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:25.357 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:25.357 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:58:25.357 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:58:25.357 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:58:25.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:25.359 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:58:25.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:58:25.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:58:25.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:58:25.359 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:58:25.360 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:58:25.360 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:58:25.360 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:25.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:25.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:25.365 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:58:25.849 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:58:25.890 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:58:25.892 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:58:25.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:58:25.895 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:58:25.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:58:25.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:58:25.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:58:25.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:58:25.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:58:25.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:58:25.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:25.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:25.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:25.951 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:25.952 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:25.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:25.952 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:25.952 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:58:25.952 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:58:25.952 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:58:25.952 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:25.952 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:25.952 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:25.952 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:25.953 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:25.953 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:58:30.954 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:58:30.955 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:58:30.956 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:30.957 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:30.958 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:30.959 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:30.965 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:58:30.966 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:58:30.966 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:30.967 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:58:30.967 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:58:30.971 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:58:30.971 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:58:30.971 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:58:30.971 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:30.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:58:30.971 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:58:30.972 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:58:30.972 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:58:30.972 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:30.974 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:58:30.974 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:58:30.974 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:58:30.974 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:30.974 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:58:30.974 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:58:30.974 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:58:30.974 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:58:30.974 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:30.976 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:58:30.976 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:58:30.976 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:58:30.976 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:58:30.976 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:58:30.976 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:58:30.977 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:58:30.977 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:58:30.977 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:30.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:58:30.980 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:58:30.980 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:58:30.980 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:30.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:30.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:30.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:30.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:58:30.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:58:30.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:30.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:58:30.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:30.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:30.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:30.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:58:30.985 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:58:31.469 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:58:31.508 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:58:31.510 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:58:31.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:58:31.512 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:58:31.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:58:31.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:58:31.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 01:58:31.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 01:58:31.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 01:58:31.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 01:58:31.517 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 01:58:31.517 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 01:58:31.946 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:58:31.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:31.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:31.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:31.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:32.424 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:58:32.902 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:58:32.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:32.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:32.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:32.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:33.380 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:58:33.858 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:58:33.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:33.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:33.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:33.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:34.336 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:58:34.813 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:58:34.986 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:34.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:34.986 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:34.989 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:35.291 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:58:35.769 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:58:35.987 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:58:35.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:58:35.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:58:35.990 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:58:36.247 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:58:36.724 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:58:37.202 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:58:37.680 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 01:58:38.158 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 01:58:38.635 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 01:58:39.113 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 01:58:39.591 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 01:58:40.069 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 01:58:40.547 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 01:58:41.025 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 01:58:41.503 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 01:58:41.980 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 01:58:42.458 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 01:58:42.936 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 01:58:43.414 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 01:58:43.892 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 01:58:44.370 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 01:58:44.847 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 01:58:45.325 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 01:58:45.803 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 01:58:46.281 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 01:58:46.759 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 01:58:47.236 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 01:58:47.714 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 01:58:48.192 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 01:58:48.670 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 01:58:49.148 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 01:58:49.625 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 01:58:50.103 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 01:58:50.581 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 01:58:51.058 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 01:58:51.536 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 01:58:52.014 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 01:58:52.492 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 01:58:52.969 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 01:58:53.446 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 01:58:53.924 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 01:58:54.402 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 01:58:54.880 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 01:58:55.357 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 01:58:55.836 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 01:58:56.314 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 01:58:56.791 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 01:58:57.270 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 01:58:57.748 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 01:58:58.226 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 01:58:58.703 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 01:58:59.181 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 01:58:59.659 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 01:59:00.137 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 01:59:00.615 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 01:59:01.092 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 01:59:01.564 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 01:59:02.041 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 01:59:02.519 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 01:59:02.997 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 01:59:03.474 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 01:59:03.952 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 01:59:04.430 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 01:59:04.908 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 01:59:05.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 01:59:05.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 01:59:05.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:05.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:05.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:05.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:05.008 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:05.008 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:05.008 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:05.008 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:05.008 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:59:05.008 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:59:05.008 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:59:10.014 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:59:10.014 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:59:10.014 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:10.014 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:10.014 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:10.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:10.023 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:10.025 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:59:10.025 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:10.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:59:10.026 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:59:10.029 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:59:10.030 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:59:10.030 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:59:10.030 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:10.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:10.030 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:59:10.031 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:59:10.031 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:59:10.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:10.033 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:59:10.033 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:59:10.034 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:59:10.034 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:10.034 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:10.034 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:59:10.035 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:59:10.035 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:59:10.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:10.036 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:59:10.037 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:59:10.037 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:59:10.037 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:10.037 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:10.037 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:59:10.037 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:59:10.037 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:59:10.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:10.040 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:59:10.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:59:10.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:59:10.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:59:10.040 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:59:10.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:59:10.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:59:10.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:59:10.041 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:59:10.041 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:59:10.041 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:10.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:10.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:10.046 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:59:10.529 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:59:10.579 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:59:10.580 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:59:10.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:59:10.582 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:59:11.010 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:59:11.046 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:11.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:11.049 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:11.053 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:11.490 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:59:11.971 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:59:12.048 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:12.049 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:12.050 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:12.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:12.452 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:59:12.933 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:59:13.049 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:13.049 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:13.051 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:13.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:13.411 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:59:13.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:59:13.599 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:13.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:13.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:13.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:13.600 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:13.600 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:13.600 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:13.600 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:13.600 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:59:13.600 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:59:13.600 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:59:13.600 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=756 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:13.601 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=756 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:13.601 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=756 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:13.601 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=756 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:13.601 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=757 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:18.603 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:59:18.604 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:59:18.605 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:18.606 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:18.607 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:18.608 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:18.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:18.617 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:59:18.617 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:18.618 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:59:18.618 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:59:18.622 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:59:18.623 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:59:18.623 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:59:18.623 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:18.624 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:18.624 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:59:18.624 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:59:18.625 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:59:18.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:18.625 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:59:18.625 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:59:18.625 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:59:18.626 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:18.626 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:18.626 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:59:18.626 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:59:18.626 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:59:18.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:18.628 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:59:18.628 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:59:18.628 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:59:18.628 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:18.628 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:18.628 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:59:18.628 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:59:18.628 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:59:18.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:18.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:59:18.632 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:59:18.632 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:59:18.632 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:18.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:18.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:18.633 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:18.633 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:18.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:18.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:18.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:18.633 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:18.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:18.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:18.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:18.637 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:59:19.120 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:59:19.157 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:59:19.160 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:59:19.162 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:59:19.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:59:19.589 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:59:19.634 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:19.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:19.636 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:19.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:20.058 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:59:20.536 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:59:20.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:20.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:20.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:20.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:21.016 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:59:21.498 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:59:21.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:21.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:21.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:21.641 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:21.977 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:59:22.458 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:59:22.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:22.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:22.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:22.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:22.939 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:59:23.419 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:59:23.640 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:23.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:23.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:23.644 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:23.898 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:59:24.376 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:59:24.857 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:59:25.171 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:25.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:25.172 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:25.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:25.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:25.172 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:25.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:25.172 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:25.172 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:59:25.172 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:59:25.172 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:59:25.172 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:25.172 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:25.172 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:25.172 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:25.172 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:25.172 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:25.172 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:30.177 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:59:30.178 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:59:30.178 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:30.178 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:30.178 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:30.178 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:30.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:30.185 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:59:30.185 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:30.185 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:59:30.186 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:59:30.188 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:59:30.188 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:59:30.188 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:59:30.188 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:30.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:30.189 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:59:30.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:59:30.189 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:59:30.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:30.190 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:59:30.190 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:59:30.190 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:59:30.190 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:30.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:30.191 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:59:30.191 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:59:30.191 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:59:30.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:30.192 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:59:30.192 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:59:30.192 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:59:30.192 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:30.192 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:59:30.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:30.192 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:59:30.192 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:59:30.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:30.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:59:30.195 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:59:30.195 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:59:30.195 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:30.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:30.199 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:59:30.683 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:59:30.722 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:59:30.724 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:59:30.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:59:30.726 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:59:31.161 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:59:31.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:31.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:31.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:31.200 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:31.635 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:59:32.113 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:59:32.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:32.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:32.199 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:32.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:32.594 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:59:33.074 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:59:33.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:33.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:33.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:33.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:33.555 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:59:34.036 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:59:34.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:34.200 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:34.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:34.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:34.518 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:59:34.996 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:59:35.201 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:35.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:35.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:35.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:35.475 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:59:35.957 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:59:36.436 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:59:36.738 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:36.738 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:36.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:36.738 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:36.739 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:36.739 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:36.739 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:36.739 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:36.739 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:59:36.739 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:59:36.739 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:59:41.742 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:59:41.742 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:59:41.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:41.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:41.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:41.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:41.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:41.757 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:59:41.757 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:41.758 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:59:41.758 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:59:41.762 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:59:41.762 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:59:41.763 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:59:41.763 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:41.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:41.764 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:59:41.764 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:59:41.764 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:59:41.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:41.765 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:59:41.765 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:59:41.766 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:59:41.766 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:41.766 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:41.766 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:59:41.766 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:59:41.766 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:59:41.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:41.768 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:59:41.768 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:59:41.768 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:59:41.768 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:41.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:41.769 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:59:41.769 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:59:41.769 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:59:41.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:41.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:41.773 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:59:41.773 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:59:41.773 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:59:41.773 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:59:41.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:41.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:41.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:41.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:59:41.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:41.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:41.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:41.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:41.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:41.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:41.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:41.778 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:59:42.261 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:59:42.303 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:59:42.305 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:59:42.307 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:59:42.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:59:42.741 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:59:42.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:42.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:42.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:42.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:43.220 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:59:43.700 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:59:43.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:43.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:43.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:43.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:44.178 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:59:44.659 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:59:44.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:44.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:44.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:44.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:45.138 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:59:45.616 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:59:45.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:45.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:45.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:45.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:46.094 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:59:46.572 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:59:46.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:46.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:46.787 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:46.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:47.051 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:59:47.529 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:59:48.008 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 01:59:48.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:48.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:48.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:48.322 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:48.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:48.324 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:48.324 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:48.324 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:48.324 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:59:48.324 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:59:48.324 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 01:59:48.325 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:48.325 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:48.325 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:48.325 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:48.325 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:48.325 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:48.325 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 01:59:53.325 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 01:59:53.325 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 01:59:53.326 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:53.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:53.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:53.329 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:53.334 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 01:59:53.334 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:59:53.334 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:53.335 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 01:59:53.335 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 01:59:53.337 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 01:59:53.337 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 01:59:53.337 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:59:53.337 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:53.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 01:59:53.337 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 01:59:53.337 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 01:59:53.337 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 01:59:53.338 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:53.339 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 01:59:53.339 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 01:59:53.339 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:59:53.339 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:53.340 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 01:59:53.340 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 01:59:53.340 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 01:59:53.340 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 01:59:53.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:53.341 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 01:59:53.341 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 01:59:53.341 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:59:53.342 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 01:59:53.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 01:59:53.342 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 01:59:53.342 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 01:59:53.342 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 01:59:53.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:53.345 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 01:59:53.345 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 01:59:53.345 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 01:59:53.346 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 01:59:53.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 01:59:53.350 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 01:59:53.835 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 01:59:53.874 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 01:59:53.874 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 01:59:53.874 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 01:59:53.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:59:54.304 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 01:59:54.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:54.349 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:54.350 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:54.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:54.773 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 01:59:55.244 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 01:59:55.350 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:55.350 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:55.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:55.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:55.723 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 01:59:56.201 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 01:59:56.351 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:56.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:56.352 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:56.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:56.680 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 01:59:57.159 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 01:59:57.353 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:57.353 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:57.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:57.360 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:57.637 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 01:59:57.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 01:59:58.115 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 01:59:58.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 01:59:58.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 01:59:58.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 01:59:58.361 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 01:59:58.600 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 01:59:59.082 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 01:59:59.563 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:00:00.044 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:00:00.524 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:00:01.002 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:00:01.481 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:00:01.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:01.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:01.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:01.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:01.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:01.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:01.916 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:01.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:01.916 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:01.916 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:01.916 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:00:01.916 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1830 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:01.916 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1830 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:01.916 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1830 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:01.916 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1830 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:01.916 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1830 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:01.916 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1830 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:01.916 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1830 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:06.919 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:06.919 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:06.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:06.921 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:06.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:06.922 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:06.936 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:06.937 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:06.937 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:06.937 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:06.937 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:00:06.939 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:00:06.939 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:00:06.939 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:06.939 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:06.939 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:06.940 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:00:06.940 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:06.940 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:00:06.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:06.942 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:00:06.942 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:00:06.942 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:06.942 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:06.942 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:00:06.942 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:06.942 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:06.942 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:00:06.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:06.944 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:00:06.944 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:00:06.944 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:06.944 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:06.944 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:06.944 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:00:06.944 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:06.944 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:00:06.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:00:06.946 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:00:06.946 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:00:06.946 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:06.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:06.951 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:00:07.432 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:00:07.468 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:00:07.469 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:00:07.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:00:07.470 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:00:07.911 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:00:07.949 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:07.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:07.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:07.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:08.383 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:00:08.851 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:00:08.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:08.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:08.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:08.951 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:09.320 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:00:09.798 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:00:09.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:09.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:09.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:09.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:10.276 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:00:10.754 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:00:10.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:10.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:10.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:10.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:11.231 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:00:11.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:11.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:11.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:11.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:11.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:11.482 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:11.482 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:11.482 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:11.482 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:11.482 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:11.482 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:00:11.483 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=974 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:11.483 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=974 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:11.483 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=974 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:11.483 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=974 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:11.483 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=974 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:11.483 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=974 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:16.485 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:16.486 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:16.489 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:16.489 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:16.489 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:16.489 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:16.497 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:16.498 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:16.499 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:16.499 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:16.499 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:00:16.502 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:00:16.502 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:00:16.502 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:16.503 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:16.503 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:16.503 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:00:16.503 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:16.504 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:00:16.504 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:16.505 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:00:16.505 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:00:16.505 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:16.505 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:16.505 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:16.505 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:00:16.505 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:16.505 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:00:16.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:16.507 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:00:16.507 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:00:16.507 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:16.507 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:16.507 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:16.507 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:00:16.508 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:16.508 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:00:16.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:16.510 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:00:16.510 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:00:16.510 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:00:16.511 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:16.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:16.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:16.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:16.515 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:00:16.999 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:00:17.038 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:00:17.041 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:00:17.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:00:17.043 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:00:17.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:17.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:17.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:17.054 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:17.057 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:17.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:17.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:17.058 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:17.058 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:17.058 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:00:17.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:17.058 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:17.058 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:17.058 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:17.058 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:17.058 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:17.058 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:17.058 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:22.057 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:22.057 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:22.058 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:22.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:22.062 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:22.064 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:22.072 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:22.072 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:22.072 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:22.073 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:22.073 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:00:22.074 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:00:22.075 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:00:22.075 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:22.075 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:22.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:22.076 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:00:22.076 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:22.076 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:00:22.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:22.077 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:00:22.077 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:00:22.077 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:22.077 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:22.077 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:22.077 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:00:22.077 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:22.077 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:00:22.077 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:22.079 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:00:22.079 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:00:22.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:22.079 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:22.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:22.079 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:00:22.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:22.079 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:00:22.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:22.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:00:22.082 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:00:22.082 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:00:22.082 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:22.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:22.086 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:00:22.571 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:00:22.604 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:00:22.605 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:00:22.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:00:22.607 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:00:22.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:00:22.617 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:22.617 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:22.617 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:22.618 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:22.621 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:22.621 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:22.621 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:22.621 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:22.622 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:22.622 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:22.622 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:00:22.622 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:22.622 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:22.622 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:22.622 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:22.622 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:22.622 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:22.622 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:22.623 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:27.621 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:27.621 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:27.625 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:27.625 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:27.625 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:27.625 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:27.634 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:27.636 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:27.636 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:27.637 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:27.637 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:00:27.643 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:00:27.643 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:00:27.644 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:27.644 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:27.644 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:27.644 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:00:27.645 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:27.645 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:00:27.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:27.647 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:00:27.648 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:00:27.648 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:27.648 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:27.648 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:27.649 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:00:27.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:27.649 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:00:27.649 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:27.650 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:00:27.651 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:00:27.651 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:27.651 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:27.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:27.651 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:00:27.651 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:27.651 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:00:27.651 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:27.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:00:27.655 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:00:27.655 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:00:27.655 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:27.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:27.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:27.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:27.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:27.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:27.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:27.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:27.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:27.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:27.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:27.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:27.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:27.660 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:00:28.143 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:00:28.182 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:00:28.184 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:00:28.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:00:28.186 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:00:28.196 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:28.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:28.197 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:28.197 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:28.200 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:28.201 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:28.201 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:28.201 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:28.201 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:28.201 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:28.201 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:00:28.201 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:28.201 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:28.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:28.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:28.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:28.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:28.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:28.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:28.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:28.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:28.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:33.200 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:33.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:33.201 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:33.203 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:33.204 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:33.204 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:33.212 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:33.214 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:33.214 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:33.214 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:33.214 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:00:33.217 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:00:33.218 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:00:33.218 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:33.218 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:33.219 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:33.219 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:00:33.220 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:33.220 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:00:33.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:33.220 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:00:33.220 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:00:33.221 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:33.221 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:33.221 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:33.221 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:00:33.221 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:33.221 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:00:33.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:33.223 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:00:33.223 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:00:33.223 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:33.223 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:33.223 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:33.223 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:00:33.223 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:33.223 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:00:33.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:33.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:00:33.227 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:00:33.227 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:00:33.227 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:33.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:33.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:33.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:33.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:33.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:33.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:33.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:33.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:33.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:33.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:33.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:33.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:33.232 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:00:33.716 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:00:33.759 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:00:33.759 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:00:33.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:00:33.760 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:00:33.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:00:33.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:00:33.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:00:33.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:00:33.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:00:33.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:00:33.767 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:00:33.767 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:00:34.193 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:00:34.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:34.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:34.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:34.239 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:34.671 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:00:35.149 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:00:35.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:35.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:35.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:35.239 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:35.626 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:00:36.104 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:00:36.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:36.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:36.236 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:36.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:36.581 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:00:36.824 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:00:36.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:00:36.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:00:36.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:00:36.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:00:36.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:00:36.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:00:36.876 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:36.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:36.877 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:36.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:36.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:36.879 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:36.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:36.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:36.879 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:36.879 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:36.879 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:00:36.879 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=780 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:36.879 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=780 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:36.879 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=780 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:36.879 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=780 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:36.880 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=780 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:36.880 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=780 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:41.878 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:41.879 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:41.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:41.882 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:41.882 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:41.883 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:41.887 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:41.888 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:41.888 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:41.888 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:41.889 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:00:41.890 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:00:41.891 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:00:41.891 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:41.891 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:41.892 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:41.892 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:00:41.892 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:41.892 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:00:41.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:41.893 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:00:41.893 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:00:41.894 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:41.894 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:41.894 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:41.894 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:00:41.894 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:41.894 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:00:41.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:41.897 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:00:41.897 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:00:41.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:41.898 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:41.898 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:41.898 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:00:41.898 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:41.898 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:00:41.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:41.901 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:00:41.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:00:41.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:00:41.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:00:41.901 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:41.902 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:00:41.902 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:00:41.902 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:00:41.903 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:00:41.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:41.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:41.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:41.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:00:41.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:41.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:41.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:41.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:41.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:41.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:41.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:41.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:41.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:41.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:41.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:41.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:41.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:41.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:41.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:41.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:41.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:41.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:41.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:41.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:41.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:41.907 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:00:42.391 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:00:42.432 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:00:42.434 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:00:42.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:00:42.435 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:00:42.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:00:42.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:00:42.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:00:42.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:00:42.441 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:00:42.441 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:00:42.441 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:00:42.441 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:00:42.869 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:00:42.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:42.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:42.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:42.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:43.346 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:00:43.824 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:00:43.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:43.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:43.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:43.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:44.302 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:00:44.780 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:00:44.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:44.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:44.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:44.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:45.257 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:00:45.500 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:00:45.500 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:00:45.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:00:45.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:00:45.735 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:00:45.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:45.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:45.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:45.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:46.213 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:00:46.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:00:46.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:00:46.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:00:46.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:46.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:46.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:46.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:46.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:46.235 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:46.235 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:46.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:46.235 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:46.235 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:46.235 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:00:51.235 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:51.235 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:51.236 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:51.237 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:51.237 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:51.238 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:51.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:51.246 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:51.246 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:51.246 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:00:51.246 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:00:51.248 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:00:51.248 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:00:51.248 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:51.248 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:51.249 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:51.249 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:00:51.249 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:00:51.249 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:00:51.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:51.251 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:00:51.251 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:00:51.251 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:51.251 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:51.251 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:51.251 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:00:51.251 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:00:51.251 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:00:51.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:51.253 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:00:51.253 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:00:51.253 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:51.253 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:00:51.253 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:51.253 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:00:51.254 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:00:51.254 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:00:51.254 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:51.256 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:00:51.256 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:00:51.257 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:00:51.257 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:51.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:51.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:00:51.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:00:51.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:51.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:00:51.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:00:51.261 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:00:51.745 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:00:51.790 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:00:51.792 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:00:51.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:00:51.796 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:00:51.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:00:51.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:00:51.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:00:51.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:00:51.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:00:51.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:00:51.805 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:00:51.805 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:00:52.222 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:00:52.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:52.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:52.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:52.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:52.700 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:00:53.178 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:00:53.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:53.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:53.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:53.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:53.655 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:00:54.132 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:00:54.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:54.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:54.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:54.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:54.610 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:00:54.852 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:00:54.853 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:00:54.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:00:54.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:00:55.088 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:00:55.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:55.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:55.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:55.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:55.566 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:00:56.043 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:00:56.263 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:56.263 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:56.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:56.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:56.521 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:00:56.999 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:00:57.477 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:00:57.954 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:00:58.432 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:00:58.910 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:00:59.388 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:00:59.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:00:59.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:00:59.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:00:59.866 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:00:59.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:00:59.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:00:59.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:00:59.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:00:59.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:00:59.875 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:00:59.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:00:59.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:00:59.875 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:00:59.875 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:00:59.876 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:00:59.876 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:59.876 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:59.876 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:59.876 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:59.876 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:00:59.876 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:01:04.874 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:01:04.874 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:01:04.874 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:04.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:04.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:04.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:04.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:04.878 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:01:04.878 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:04.878 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:01:04.878 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:01:04.880 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:01:04.880 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:01:04.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:01:04.880 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:04.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:04.880 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:01:04.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:01:04.880 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:01:04.880 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:04.881 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:01:04.881 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:01:04.881 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:01:04.881 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:04.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:04.881 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:01:04.881 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:01:04.881 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:01:04.881 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:04.881 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:01:04.881 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:01:04.881 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:01:04.881 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:04.882 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:04.882 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:01:04.882 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:01:04.882 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:01:04.882 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:01:04.883 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:01:04.883 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:01:04.883 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:04.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:04.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:04.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:04.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:04.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:04.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:04.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:04.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:04.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:04.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:04.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:04.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:04.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:04.888 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:01:05.356 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:01:05.398 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:01:05.398 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:01:05.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:01:05.399 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:01:05.400 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:01:05.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:01:05.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:01:05.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:01:05.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:01:05.401 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:01:05.401 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:01:05.401 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:01:05.824 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:01:05.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:05.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:05.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:05.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:06.294 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:01:06.765 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:01:06.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:06.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:06.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:06.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:07.236 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:01:07.710 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:01:07.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:07.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:07.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:07.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:08.180 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:01:08.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:01:08.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:01:08.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:01:08.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:01:08.648 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:01:08.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:08.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:08.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:08.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:09.119 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:01:09.589 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:01:09.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:09.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:09.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:09.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:10.058 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:01:10.526 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:01:10.996 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:01:11.463 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:01:11.931 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:01:12.399 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:01:12.867 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:01:13.335 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:01:13.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:01:13.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:01:13.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:01:13.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:13.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:13.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:13.465 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:13.465 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:13.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:13.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:13.465 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:01:13.465 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:01:13.465 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:01:13.466 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:18.466 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:01:18.466 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:01:18.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:18.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:18.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:18.467 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:18.471 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:18.471 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:01:18.472 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:18.472 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:01:18.472 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:01:18.472 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:01:18.472 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:01:18.472 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:01:18.472 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:18.472 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:18.472 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:01:18.472 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:01:18.472 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:01:18.472 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:18.473 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:01:18.473 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:01:18.474 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:01:18.474 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:18.474 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:18.474 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:01:18.474 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:01:18.474 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:01:18.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:18.475 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:01:18.475 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:01:18.475 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:01:18.475 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:18.475 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:18.475 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:01:18.475 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:01:18.475 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:01:18.475 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:18.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:01:18.477 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:01:18.477 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:01:18.477 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:18.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:18.481 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:01:18.952 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:01:18.988 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:01:18.989 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:01:18.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:01:18.989 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:01:18.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:01:18.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:01:18.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:01:18.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:01:18.991 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:01:18.991 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:01:18.991 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:01:18.991 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:01:19.421 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:01:19.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:19.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:19.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:19.480 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:19.889 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:01:20.358 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:01:20.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:20.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:20.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:20.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:20.828 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:01:21.297 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:01:21.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:21.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:21.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:21.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:21.766 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:01:22.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:01:22.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:01:22.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:01:22.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:01:22.235 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:01:22.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:22.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:22.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:22.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:22.704 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:01:23.173 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:01:23.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:23.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:23.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:23.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:23.642 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:01:24.109 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:01:24.576 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:01:25.044 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:01:25.512 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:01:25.980 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:01:26.447 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:01:26.918 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:01:27.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:01:27.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:01:27.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:01:27.008 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:27.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:27.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:27.008 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:27.009 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:27.009 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:27.009 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:27.009 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:27.009 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:01:27.009 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:01:27.009 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:01:32.009 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:01:32.009 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:01:32.010 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:32.010 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:32.010 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:32.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:32.015 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:32.016 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:01:32.016 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:32.016 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:01:32.016 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:01:32.017 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:01:32.017 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:01:32.017 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:01:32.017 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:32.017 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:32.017 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:01:32.017 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:01:32.017 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:01:32.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:32.017 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:01:32.017 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:01:32.017 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:01:32.017 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:32.017 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:32.018 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:01:32.018 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:01:32.018 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:01:32.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:32.018 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:01:32.018 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:01:32.018 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:01:32.018 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:32.018 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:32.018 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:01:32.018 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:01:32.018 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:01:32.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:01:32.020 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:01:32.020 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:01:32.020 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:32.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:32.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:32.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:32.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:32.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:32.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:32.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:32.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:32.025 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:01:32.496 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:01:32.535 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:01:32.535 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:01:32.536 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:01:32.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:01:32.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:01:32.537 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:01:32.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:01:32.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:01:32.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:01:32.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:01:32.538 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:01:32.538 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:01:32.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:01:32.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:01:32.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:01:32.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:01:32.965 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:01:33.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:33.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:33.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:33.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:33.434 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:01:33.904 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:01:34.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:34.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:34.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:34.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:34.373 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:01:34.842 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:01:35.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:35.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:35.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:35.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:35.310 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:01:35.779 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:01:36.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:36.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:36.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:36.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:36.249 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:01:36.717 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:01:37.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:37.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:37.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:37.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:37.185 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:01:37.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:01:37.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:01:37.541 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:37.541 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:37.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:37.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:37.541 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:37.541 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:37.541 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:37.541 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:01:37.541 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:01:37.541 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:01:37.541 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:37.541 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1202 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:01:37.542 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1202 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:01:37.542 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1202 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:01:37.542 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1202 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:01:37.542 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1202 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:01:37.542 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1202 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:01:37.542 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1202 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:01:37.542 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1202 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:01:42.542 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:01:42.542 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:01:42.542 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:42.543 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:42.543 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:42.543 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:42.546 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:42.547 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:01:42.547 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:42.547 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:01:42.547 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:01:42.548 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:01:42.548 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:01:42.548 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:01:42.548 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:42.548 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:42.548 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:01:42.548 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:01:42.548 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:01:42.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:42.548 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:01:42.548 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:01:42.548 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:01:42.548 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:42.548 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:42.549 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:01:42.549 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:01:42.549 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:01:42.549 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:42.549 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:01:42.549 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:01:42.549 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:01:42.549 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:42.549 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:42.549 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:01:42.549 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:01:42.549 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:01:42.549 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:01:42.551 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:01:42.551 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:01:42.551 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:42.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:42.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:42.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:42.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:42.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:42.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:42.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:42.556 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:01:43.027 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:01:43.063 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:01:43.064 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:01:43.064 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:01:43.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:01:43.065 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:01:43.065 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:01:43.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:01:43.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:01:43.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:01:43.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:01:43.066 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:01:43.066 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:01:43.498 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:01:43.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:43.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:43.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:43.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:43.970 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:01:44.440 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:01:44.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:44.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:44.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:44.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:44.911 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:01:45.380 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:01:45.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:45.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:45.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:45.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:45.848 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:01:46.088 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:01:46.088 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:01:46.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:01:46.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:01:46.317 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:01:46.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:46.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:46.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:46.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:46.786 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:01:47.253 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:01:47.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:47.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:47.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:47.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:47.720 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:01:48.187 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:01:48.655 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:01:48.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:01:48.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:01:48.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:01:48.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:48.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:48.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:48.702 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:48.703 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:48.703 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:48.703 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:48.703 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:01:48.703 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:01:48.703 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:01:48.703 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:53.703 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:01:53.703 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:01:53.703 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:53.704 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:53.704 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:53.705 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:53.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:53.712 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:01:53.712 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:53.712 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:01:53.712 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:01:53.713 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:01:53.713 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:01:53.713 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:01:53.713 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:53.713 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:53.713 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:01:53.714 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:01:53.714 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:01:53.714 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:53.714 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:01:53.714 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:01:53.714 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:01:53.714 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:53.714 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:53.714 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:01:53.714 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:01:53.714 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:01:53.714 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:53.715 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:01:53.715 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:01:53.715 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:01:53.715 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:01:53.715 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:53.715 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:01:53.715 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:01:53.715 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:01:53.715 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:01:53.716 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:01:53.716 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:01:53.716 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:53.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:53.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:01:53.721 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:01:54.192 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:01:54.228 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:01:54.228 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:01:54.229 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:01:54.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:01:54.231 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:01:54.231 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:01:54.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:01:54.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:01:54.231 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:01:54.231 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:01:54.231 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:01:54.231 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:01:54.663 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:01:54.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:54.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:54.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:54.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:55.134 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:01:55.605 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:01:55.719 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:55.719 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:55.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:55.722 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:56.076 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:01:56.546 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:01:56.719 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:56.720 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:56.720 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:56.722 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:57.017 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:01:57.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:01:57.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:01:57.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:01:57.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:01:57.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:01:57.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:01:57.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:01:57.288 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:01:57.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:01:57.288 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:01:57.288 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:01:57.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:01:57.288 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:01:57.288 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:02:02.289 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:02:02.289 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:02:02.289 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:02.289 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:02.289 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:02.290 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:02.293 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:02.293 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:02:02.293 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:02.293 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:02:02.293 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:02:02.293 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:02:02.294 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:02:02.294 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:02:02.294 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:02.294 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:02.294 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:02:02.294 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:02:02.294 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:02:02.294 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:02.294 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:02:02.294 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:02:02.294 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:02:02.294 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:02.294 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:02.294 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:02:02.294 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:02:02.294 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:02:02.295 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:02.295 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:02:02.295 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:02:02.295 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:02:02.295 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:02.295 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:02.295 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:02:02.295 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:02:02.295 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:02:02.295 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:02.296 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:02:02.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:02:02.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:02:02.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:02:02.296 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:02:02.297 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:02:02.297 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:02:02.297 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:02.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:02.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:02.302 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:02:02.773 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:02:02.811 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:02:02.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:02:02.812 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:02:02.813 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:02.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:02:02.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:02:02.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:02:02.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:02:02.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:02:02.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:02:02.815 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:02:02.815 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:02:03.242 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:02:03.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:03.299 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:03.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:03.302 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:03.714 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:02:04.185 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:02:04.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:04.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:04.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:04.302 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:04.656 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:02:05.127 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:02:05.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:05.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:05.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:05.302 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:05.598 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:02:05.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:02:05.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:02:05.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:02:05.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:05.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:05.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:05.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:05.915 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:05.915 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:05.915 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:05.915 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:05.915 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:02:05.915 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:02:05.915 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:02:10.915 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:02:10.915 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:02:10.915 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:10.916 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:10.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:10.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:10.920 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:10.920 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:02:10.920 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:10.920 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:02:10.920 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:02:10.921 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:02:10.921 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:02:10.921 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:02:10.921 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:10.921 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:10.921 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:02:10.921 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:02:10.921 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:02:10.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:10.921 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:02:10.921 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:02:10.921 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:02:10.921 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:10.921 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:10.921 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:02:10.922 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:02:10.922 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:02:10.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:10.922 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:02:10.922 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:02:10.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:02:10.922 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:10.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:10.922 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:02:10.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:02:10.922 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:02:10.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:10.923 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:02:10.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:02:10.924 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:02:10.924 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:02:10.924 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:10.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:10.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:10.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:10.929 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:02:11.400 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:02:11.437 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:02:11.437 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:02:11.438 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:11.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:02:11.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:02:11.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:02:11.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:02:11.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:02:11.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:02:11.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:02:11.440 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:02:11.440 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:02:11.714 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:02:11.714 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:02:11.716 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:11.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:11.716 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:11.716 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:11.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:11.717 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:11.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:11.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:11.717 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:02:11.717 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:02:11.717 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:02:16.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:02:16.720 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:02:16.721 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:16.722 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:16.722 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:16.723 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:16.730 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:16.730 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:02:16.730 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:16.730 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:02:16.730 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:02:16.733 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:02:16.734 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:02:16.734 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:02:16.734 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:16.734 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:16.734 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:02:16.734 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:02:16.734 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:02:16.734 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:16.736 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:02:16.736 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:02:16.737 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:02:16.737 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:16.737 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:16.737 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:02:16.737 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:02:16.737 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:02:16.737 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:16.739 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:02:16.739 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:02:16.739 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:02:16.739 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:16.739 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:16.739 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:02:16.739 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:02:16.739 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:02:16.739 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:16.742 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:02:16.742 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:02:16.742 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:02:16.743 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:16.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:16.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:16.747 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:02:17.232 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:02:17.272 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:02:17.275 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:02:17.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:02:17.277 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:17.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:02:17.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:02:17.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:02:17.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:02:17.287 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:02:17.287 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:02:17.287 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:02:17.287 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:02:17.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:02:17.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:02:17.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:17.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:17.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:17.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:17.507 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:17.507 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:17.508 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:17.508 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:02:17.508 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:02:17.508 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:02:17.508 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:17.508 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=163 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:17.508 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=163 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:17.508 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=163 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:17.508 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=163 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:17.508 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=163 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:17.508 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=163 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:17.508 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=163 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:17.508 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=163 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:22.508 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:02:22.508 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:02:22.509 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:22.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:22.509 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:22.510 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:22.513 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:22.513 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:02:22.513 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:22.513 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:02:22.513 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:02:22.514 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:02:22.514 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:02:22.514 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:02:22.514 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:22.514 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:22.514 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:02:22.514 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:02:22.514 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:02:22.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:22.515 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:02:22.515 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:02:22.515 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:02:22.515 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:22.515 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:22.515 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:02:22.515 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:02:22.515 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:02:22.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:22.516 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:02:22.516 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:02:22.516 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:02:22.516 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:22.516 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:22.516 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:02:22.516 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:02:22.516 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:02:22.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:02:22.517 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:02:22.517 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:02:22.517 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:22.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:22.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:22.522 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:02:22.999 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:02:23.043 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:02:23.044 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:02:23.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:02:23.045 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:23.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:02:23.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:02:23.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:02:23.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:02:23.050 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:02:23.050 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:02:23.051 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:02:23.051 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:02:23.472 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:02:23.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:23.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:23.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:23.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:23.943 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:02:24.418 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:02:24.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:24.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:24.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:24.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:24.894 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:02:25.367 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:02:25.522 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:25.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:25.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:25.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:25.840 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:02:26.315 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:02:26.522 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:26.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:26.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:26.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:26.791 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:02:27.264 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:02:27.522 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:27.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:27.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:27.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:27.739 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:02:28.211 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:02:28.685 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:02:29.157 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:02:29.631 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:02:30.106 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:02:30.581 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:02:31.055 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:02:31.529 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:02:31.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:02:31.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:02:31.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:31.868 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:31.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:31.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:31.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:31.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:31.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:31.870 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:02:31.870 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:02:31.870 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:02:31.870 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:36.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:02:36.873 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:02:36.874 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:36.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:36.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:36.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:36.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:36.886 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:02:36.886 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:36.886 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:02:36.886 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:02:36.890 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:02:36.890 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:02:36.891 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:02:36.891 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:36.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:36.892 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:02:36.892 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:02:36.892 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:02:36.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:36.893 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:02:36.893 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:02:36.893 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:02:36.893 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:36.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:36.893 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:02:36.893 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:02:36.894 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:02:36.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:36.895 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:02:36.895 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:02:36.895 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:02:36.895 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:36.896 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:36.896 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:02:36.896 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:02:36.896 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:02:36.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:36.898 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:02:36.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:02:36.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:02:36.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:02:36.898 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:02:36.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:02:36.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:02:36.899 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:02:36.899 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:02:36.899 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:36.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:36.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:36.904 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:02:37.382 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:02:37.428 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:02:37.430 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:02:37.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:02:37.432 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:37.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:02:37.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:02:37.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:02:37.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:02:37.441 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:02:37.441 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:02:37.441 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:02:37.441 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:02:37.852 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:02:37.902 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:37.902 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:37.903 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:37.905 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:38.327 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:02:38.802 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:02:38.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:38.903 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:38.903 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:38.906 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:39.278 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:02:39.754 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:02:39.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:39.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:39.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:39.907 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:40.228 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:02:40.703 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:02:40.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:40.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:40.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:40.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:41.178 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:02:41.652 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:02:41.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:41.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:41.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:41.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:42.126 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:02:42.602 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:02:43.079 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:02:43.555 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:02:44.028 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:02:44.504 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:02:44.978 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:02:45.449 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:02:45.919 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:02:46.272 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:02:46.272 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:02:46.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:46.273 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:46.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:46.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:46.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:46.275 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:46.275 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:46.275 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:46.275 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:02:46.275 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:02:46.275 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:02:51.277 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:02:51.278 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:02:51.280 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:51.280 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:51.280 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:51.281 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:51.289 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:51.289 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:02:51.290 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:51.290 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:02:51.290 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:02:51.292 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:02:51.293 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:02:51.293 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:02:51.293 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:51.294 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:51.294 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:02:51.294 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:02:51.294 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:02:51.294 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:51.295 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:02:51.295 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:02:51.295 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:02:51.295 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:51.295 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:51.295 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:02:51.296 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:02:51.296 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:02:51.296 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:51.297 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:02:51.297 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:02:51.298 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:02:51.298 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:02:51.298 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:51.298 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:02:51.298 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:02:51.298 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:02:51.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:51.300 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:02:51.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:02:51.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:02:51.300 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:02:51.300 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:02:51.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:02:51.301 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:02:51.301 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:02:51.301 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:51.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:51.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:02:51.306 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:02:51.784 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:02:51.828 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:02:51.829 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:02:51.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:02:51.831 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:51.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:02:51.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:02:51.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:02:51.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:02:51.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:02:51.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:02:51.835 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:02:51.835 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:02:52.257 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:02:52.304 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:52.304 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:52.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:52.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:52.729 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:02:53.203 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:02:53.305 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:53.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:53.306 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:53.308 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:53.675 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:02:54.147 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:02:54.306 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:54.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:54.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:54.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:54.620 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:02:54.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:02:54.880 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:54.880 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:02:54.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:02:54.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:02:54.931 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:54.970 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:55.012 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:55.053 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:55.090 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:55.094 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:02:55.132 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:55.173 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:55.208 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:55.249 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:55.291 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:55.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:55.307 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:55.308 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:55.311 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:55.327 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:55.369 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:02:55.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:02:55.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:02:55.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:02:55.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:02:55.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:02:55.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:02:55.415 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:02:55.418 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:02:55.418 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:02:55.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:02:55.418 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:02:55.418 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:02:55.418 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:02:55.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:02:55.418 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=888 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:55.418 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=888 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:55.418 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=888 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:55.418 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=888 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:55.419 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=888 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:55.419 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=888 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:55.419 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=888 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:02:55.419 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=888 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:00.417 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:00.417 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:00.419 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:00.420 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:00.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:00.421 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:00.430 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:00.432 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:00.432 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:00.432 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:00.432 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:03:00.436 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:03:00.437 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:03:00.437 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:00.437 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:00.438 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:00.438 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:03:00.438 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:00.438 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:03:00.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:00.439 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:03:00.439 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:03:00.440 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:00.440 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:00.440 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:00.440 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:03:00.440 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:00.440 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:03:00.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:00.442 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:03:00.442 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:03:00.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:00.442 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:00.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:00.442 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:03:00.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:00.442 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:03:00.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:00.446 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:03:00.447 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:03:00.447 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:03:00.447 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:00.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:00.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:00.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:00.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:00.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:00.452 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:03:00.929 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:03:00.972 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:03:00.973 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:03:00.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:03:00.973 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:03:01.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:01.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:01.068 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:01.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:01.069 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:01.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:01.069 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:01.069 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:01.069 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:01.069 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:01.069 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:03:01.069 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=134 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:01.069 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=134 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:01.069 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=134 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:01.069 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=134 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:01.069 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=134 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:01.069 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=134 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:01.069 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=134 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:06.071 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:06.071 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:06.072 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:06.074 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:06.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:06.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:06.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:06.085 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:06.085 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:06.085 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:06.085 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:03:06.089 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:03:06.089 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:03:06.089 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:06.089 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:06.090 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:06.090 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:03:06.090 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:06.090 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:03:06.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:06.092 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:03:06.093 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:03:06.093 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:06.093 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:06.093 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:06.093 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:03:06.093 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:06.093 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:03:06.093 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:06.095 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:03:06.095 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:03:06.095 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:06.095 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:06.095 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:06.095 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:03:06.095 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:06.095 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:03:06.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:06.098 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:03:06.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:03:06.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:03:06.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:03:06.098 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:03:06.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:03:06.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:03:06.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:03:06.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:03:06.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:06.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:03:06.099 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:03:06.099 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:03:06.099 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:06.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:06.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:06.104 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:03:06.582 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:03:06.613 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:03:06.614 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:03:06.614 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:03:06.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:03:07.058 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:03:07.102 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:07.102 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:07.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:07.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:07.528 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:03:08.002 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:03:08.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:08.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:08.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:08.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:08.470 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:03:08.942 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:03:09.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:09.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:09.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:09.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:09.420 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:03:09.896 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:03:10.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:10.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:10.106 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:10.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:10.375 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:03:10.853 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:03:11.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:11.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:11.106 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:11.110 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:11.330 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:03:11.803 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:03:12.280 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:03:12.760 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:03:13.237 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:03:13.705 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:03:14.175 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:03:14.654 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:03:15.126 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:03:15.595 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:03:15.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:03:15.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:15.627 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:15.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:15.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:15.628 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:15.628 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:15.628 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:15.628 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:15.628 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:15.628 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:15.628 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:03:15.628 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2050 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:15.628 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2050 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:15.628 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2050 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:15.628 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2050 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:15.628 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2050 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:15.628 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2050 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:15.628 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2050 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:20.634 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:20.634 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:20.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:20.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:20.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:20.634 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:20.637 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:20.638 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:20.638 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:20.638 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:20.639 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:03:20.641 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:03:20.641 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:03:20.641 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:20.641 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:20.641 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:20.642 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:03:20.642 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:20.642 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:03:20.642 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:20.643 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:03:20.643 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:03:20.644 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:20.644 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:20.644 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:20.644 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:03:20.644 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:20.644 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:03:20.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:20.646 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:03:20.646 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:03:20.646 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:20.646 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:20.646 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:20.646 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:03:20.646 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:20.646 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:03:20.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:20.649 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:03:20.649 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:03:20.649 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:03:20.650 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:20.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:20.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:20.654 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:03:21.138 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:03:21.171 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:03:21.172 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:03:21.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:03:21.173 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:03:21.619 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:03:21.652 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:21.653 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:21.653 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:21.656 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:22.091 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:03:22.568 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:03:22.654 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:22.654 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:22.654 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:22.657 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:23.048 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:03:23.529 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:03:23.655 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:23.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:23.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:23.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:24.010 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:03:24.491 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:03:24.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:24.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:24.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:24.660 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:24.970 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:03:25.439 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:03:25.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:25.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:25.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:25.660 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:25.908 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:03:26.389 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:03:26.868 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:03:27.347 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:03:27.825 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:03:28.293 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:03:28.764 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:03:29.246 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:03:29.718 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:03:30.187 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:03:30.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:03:30.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:30.200 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:30.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:30.200 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:30.201 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:30.201 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:30.201 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:30.201 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:30.201 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:30.201 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:30.201 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:03:35.202 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:35.203 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:35.204 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:35.205 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:35.205 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:35.206 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:35.209 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:35.209 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:35.209 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:35.209 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:35.210 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:03:35.213 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:03:35.213 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:03:35.213 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:35.213 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:35.214 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:35.214 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:03:35.214 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:35.214 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:03:35.214 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:35.216 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:03:35.216 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:03:35.217 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:35.217 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:35.217 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:35.217 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:03:35.217 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:35.217 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:03:35.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:35.219 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:03:35.219 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:03:35.219 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:35.219 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:35.219 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:35.219 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:03:35.219 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:35.219 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:03:35.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:35.222 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:03:35.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:03:35.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:03:35.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:03:35.222 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:03:35.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:03:35.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:03:35.223 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:03:35.223 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:03:35.223 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:03:35.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:35.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:35.228 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:03:35.711 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:03:35.752 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:03:35.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:03:35.752 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:03:35.753 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:03:36.180 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:03:36.226 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:36.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:36.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:36.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:36.649 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:03:37.127 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:03:37.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:37.228 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:37.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:37.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:37.608 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:03:38.090 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:03:38.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:38.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:38.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:38.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:38.571 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:03:38.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:03:38.795 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:38.795 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:38.796 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:38.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:38.798 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:38.798 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:38.798 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:38.798 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:38.798 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:38.798 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:38.798 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:03:38.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=764 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=764 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=764 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=764 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=764 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=764 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=764 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.799 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:38.799 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:43.799 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:43.800 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:43.801 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:43.802 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:43.802 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:43.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:43.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:43.811 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:43.811 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:43.812 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:43.812 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:03:43.815 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:03:43.815 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:03:43.816 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:43.816 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:43.817 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:43.817 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:03:43.818 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:43.818 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:03:43.818 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:43.819 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:03:43.820 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:03:43.820 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:43.820 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:43.821 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:43.821 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:03:43.821 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:43.821 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:03:43.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:43.823 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:03:43.823 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:03:43.823 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:43.823 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:43.824 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:43.824 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:03:43.824 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:43.824 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:03:43.824 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:43.827 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:03:43.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:03:43.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:43.828 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:03:43.828 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:03:43.829 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:03:43.829 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:03:43.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:43.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:43.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:43.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:03:43.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:43.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:43.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:43.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:43.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:43.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:43.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:43.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:43.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:43.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:43.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:43.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:43.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:43.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:43.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:43.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:43.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:43.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:43.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:43.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:43.834 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:03:44.317 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:03:44.364 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:03:44.367 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:03:44.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:03:44.369 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:03:44.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:03:44.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:03:44.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:03:44.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:03:44.404 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:03:44.404 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:03:44.404 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:03:44.404 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:03:44.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:03:44.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:03:44.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:03:44.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:03:44.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:03:44.794 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:03:44.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:03:44.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:03:44.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:03:44.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:03:44.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:44.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:44.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:44.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:44.809 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:44.809 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:44.809 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:44.809 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:44.809 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:44.809 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:44.809 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:03:49.810 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:49.811 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:49.812 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:49.814 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:49.817 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:49.818 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:49.832 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:49.834 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:49.834 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:49.834 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:49.834 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:03:49.838 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:03:49.839 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:03:49.839 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:49.839 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:49.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:49.840 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:03:49.840 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:49.840 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:03:49.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:49.841 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:03:49.841 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:03:49.842 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:49.842 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:49.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:49.842 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:03:49.842 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:49.842 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:03:49.842 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:49.843 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:03:49.843 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:03:49.843 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:49.843 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:49.844 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:49.844 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:03:49.844 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:49.844 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:03:49.844 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:49.846 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:03:49.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:03:49.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:03:49.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:03:49.846 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:03:49.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:03:49.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:03:49.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:03:49.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:03:49.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:49.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:49.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:49.846 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:03:49.847 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:03:49.847 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:03:49.847 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:49.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:49.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:49.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:49.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:49.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:49.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:49.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:49.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:49.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:49.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:49.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:49.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:49.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:49.852 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:03:50.335 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:03:50.374 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:03:50.375 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:03:50.376 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:03:50.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:03:50.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:50.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:50.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:50.386 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:50.389 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:50.390 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:50.390 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:50.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:50.390 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:50.390 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:50.390 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:03:50.390 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:50.390 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:50.390 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:50.390 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:50.390 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:50.390 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:55.390 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:55.390 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:55.394 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:55.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:55.394 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:55.394 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:55.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:55.405 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:55.405 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:55.405 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:03:55.406 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:03:55.410 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:03:55.410 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:03:55.410 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:55.410 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:55.411 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:55.411 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:03:55.411 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:03:55.411 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:03:55.411 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:55.414 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:03:55.414 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:03:55.414 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:55.414 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:55.414 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:55.414 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:03:55.414 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:03:55.414 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:03:55.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:55.417 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:03:55.417 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:03:55.417 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:55.417 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:03:55.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:55.417 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:03:55.417 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:03:55.417 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:03:55.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:55.420 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:03:55.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:03:55.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:03:55.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:03:55.420 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:03:55.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:03:55.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:03:55.421 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:03:55.421 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:03:55.421 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:55.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:55.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:55.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:03:55.426 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:03:55.910 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:03:55.946 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:03:55.947 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:03:55.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:03:55.949 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:03:56.390 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:03:56.425 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:56.425 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:56.425 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:56.428 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:56.868 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:03:57.345 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:03:57.426 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:57.427 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:57.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:57.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:57.826 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:03:57.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:03:57.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:03:57.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:03:57.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:03:57.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:03:57.968 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:03:57.968 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:03:57.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:03:57.968 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:03:57.968 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:03:57.968 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:03:57.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=542 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:57.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=542 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:57.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=542 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:57.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=542 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:57.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=542 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:57.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=542 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:03:57.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=542 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:02.970 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:02.970 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:02.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:02.972 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:02.972 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:02.973 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:02.979 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:02.981 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:02.981 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:02.982 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:02.982 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:04:02.987 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:04:02.988 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:04:02.988 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:02.988 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:02.988 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:02.988 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:04:02.988 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:02.988 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:04:02.989 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:02.991 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:04:02.991 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:04:02.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:02.992 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:02.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:02.992 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:04:02.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:02.992 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:04:02.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:02.995 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:04:02.995 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:04:02.995 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:02.995 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:02.995 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:02.995 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:04:02.995 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:02.995 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:04:02.995 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:02.998 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:04:02.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:04:02.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:04:02.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:02.999 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:04:02.999 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:04:02.999 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:04:02.999 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:03.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:03.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:03.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:03.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:03.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:03.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:03.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:03.004 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:04:03.487 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:04:03.526 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:04:03.527 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:04:03.528 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:04:03.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:04:03.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:04:03.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:04:03.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:04:03.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:04:03.530 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:04:03.530 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:04:03.530 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:04:03.530 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:04:03.964 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:04:04.002 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:04.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:04.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:04.008 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:04.441 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:04:04.919 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:04:05.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:05.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:05.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:05.009 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:05.397 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:04:05.873 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:04:06.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:06.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:06.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:06.010 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:06.351 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:04:06.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:04:06.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:04:06.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:06.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:06.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:06.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:06.378 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:06.378 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:06.378 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:06.378 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:06.378 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:06.378 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:06.378 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:04:11.379 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:11.379 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:11.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:11.382 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:11.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:11.383 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:11.391 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:11.391 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:11.391 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:11.391 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:11.391 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:04:11.393 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:04:11.393 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:04:11.394 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:11.394 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:11.394 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:11.395 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:04:11.395 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:11.395 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:04:11.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:11.396 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:04:11.396 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:04:11.396 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:11.396 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:11.397 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:11.397 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:04:11.397 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:11.397 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:04:11.397 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:11.399 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:04:11.399 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:04:11.399 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:11.399 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:11.399 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:11.399 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:04:11.400 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:11.400 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:04:11.400 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:11.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:04:11.403 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:04:11.403 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:04:11.403 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:11.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:11.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:11.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:11.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:11.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:11.408 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:04:11.891 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:04:11.930 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:04:11.932 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:04:11.935 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:04:11.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:04:11.939 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:04:11.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:04:11.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:04:11.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:04:11.941 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:04:11.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:04:11.941 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:04:11.941 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:04:12.369 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:04:12.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:12.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:12.406 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:12.410 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:12.846 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:04:13.324 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:04:13.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:13.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:13.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:13.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:13.801 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:04:14.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:04:14.056 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:04:14.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:14.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:14.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:14.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:14.061 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:14.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:14.061 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:14.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:14.061 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:14.061 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:14.061 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:04:14.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:14.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:14.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:14.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:14.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:14.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:14.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:19.063 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:19.063 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:19.065 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:19.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:19.066 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:19.066 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:19.074 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:19.074 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:19.075 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:19.075 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:19.075 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:04:19.079 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:04:19.079 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:04:19.080 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:19.080 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:19.081 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:19.081 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:04:19.082 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:19.082 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:04:19.082 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:19.083 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:04:19.083 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:04:19.083 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:19.084 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:19.084 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:19.084 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:04:19.084 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:19.084 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:04:19.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:19.086 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:04:19.086 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:04:19.086 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:19.086 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:19.086 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:19.086 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:04:19.086 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:19.086 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:04:19.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:19.089 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:04:19.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:04:19.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:04:19.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:04:19.089 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:19.090 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:04:19.090 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:04:19.090 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:04:19.090 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:19.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:19.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:19.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:19.095 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:04:19.579 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:04:19.626 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:04:19.628 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:04:19.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:04:19.630 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:04:19.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:04:19.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:04:19.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:04:19.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:04:19.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:04:19.637 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:04:19.637 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:04:19.637 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:04:20.056 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:04:20.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:20.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:20.096 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:20.099 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:20.534 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:04:21.012 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:04:21.095 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:21.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:21.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:21.100 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:21.490 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:04:21.968 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:04:22.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:22.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:22.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:22.101 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:22.445 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:04:22.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:04:22.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:04:22.472 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:22.472 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:22.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:22.472 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:22.476 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:22.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:22.476 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:22.476 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:22.476 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:22.476 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:04:22.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:22.476 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:22.476 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:22.476 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:22.476 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=722 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:22.476 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=722 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:22.476 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=722 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:22.476 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=722 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:22.476 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=722 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:22.476 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=722 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:22.476 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=722 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:22.476 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=722 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:27.475 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:27.476 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:27.477 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:27.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:27.478 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:27.479 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:27.487 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:27.489 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:27.489 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:27.489 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:27.489 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:04:27.493 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:04:27.493 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:04:27.494 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:27.494 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:27.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:27.494 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:04:27.494 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:27.494 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:04:27.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:27.496 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:04:27.496 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:04:27.496 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:27.496 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:27.496 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:27.497 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:04:27.497 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:27.497 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:04:27.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:27.499 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:04:27.499 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:04:27.499 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:27.499 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:27.499 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:27.499 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:04:27.499 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:27.499 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:04:27.499 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:27.502 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:04:27.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:04:27.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:04:27.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:04:27.502 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:04:27.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:04:27.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:04:27.503 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:04:27.503 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:04:27.503 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:27.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:27.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:27.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:27.508 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:04:27.991 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:04:28.042 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:04:28.044 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:04:28.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:04:28.047 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:04:28.055 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:04:28.055 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:04:28.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:04:28.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:04:28.057 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:04:28.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:04:28.057 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:04:28.058 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:04:28.468 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:04:28.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:28.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:28.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:28.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:28.946 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:04:29.424 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:04:29.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:29.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:29.510 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:29.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:29.903 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:04:30.157 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:04:30.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:04:30.164 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:30.164 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:30.164 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:30.164 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:30.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:30.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:30.167 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:30.167 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:30.167 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:30.167 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:30.167 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:30.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:35.168 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:35.168 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:35.170 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:35.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:35.172 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:35.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:35.182 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:35.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:35.184 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:35.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:35.185 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:04:35.189 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:04:35.189 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:04:35.190 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:35.190 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:35.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:35.191 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:04:35.191 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:35.191 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:04:35.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:35.192 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:04:35.192 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:04:35.192 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:35.192 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:35.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:35.193 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:04:35.193 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:35.193 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:04:35.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:35.195 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:04:35.195 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:04:35.195 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:35.195 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:35.195 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:35.195 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:04:35.195 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:35.195 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:04:35.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:35.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:04:35.199 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:04:35.199 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:04:35.199 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:35.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:35.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:35.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:35.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:35.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:35.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:35.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:35.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:35.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:35.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:35.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:35.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:35.204 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:04:35.686 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:04:35.730 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:04:35.732 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:04:35.734 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:04:35.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:04:35.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:04:35.742 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:04:35.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:04:35.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:04:35.743 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:04:35.743 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:04:35.744 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:04:35.744 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:04:36.163 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:04:36.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:36.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:36.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:36.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:36.641 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:04:37.118 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:04:37.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:37.206 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:37.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:37.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:37.596 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:04:38.074 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:04:38.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:38.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:38.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:38.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:38.551 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:04:39.029 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:04:39.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:39.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:39.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:39.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:39.507 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:04:39.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:04:39.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:04:39.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:39.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:39.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:39.533 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:39.535 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:39.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:39.535 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:39.535 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:39.535 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:39.535 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:39.535 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:04:39.535 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=926 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:39.535 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=926 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:39.535 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=926 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:39.535 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=926 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:39.535 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=926 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:39.535 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=926 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:44.535 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:44.536 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:44.537 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:44.538 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:44.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:44.539 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:44.547 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:44.548 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:44.548 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:44.548 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:44.548 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:04:44.551 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:04:44.551 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:04:44.552 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:44.552 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:44.552 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:44.553 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:04:44.553 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:44.553 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:04:44.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:44.555 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:04:44.555 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:04:44.555 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:44.555 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:44.555 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:44.555 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:04:44.555 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:44.555 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:04:44.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:44.557 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:04:44.557 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:04:44.557 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:44.557 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:44.557 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:44.557 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:04:44.557 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:44.558 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:04:44.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:44.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:04:44.561 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:04:44.561 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:04:44.561 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:44.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:44.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:44.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:44.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:44.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:44.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:44.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:44.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:44.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:44.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:44.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:44.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:44.566 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:04:45.049 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:04:45.091 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:04:45.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:04:45.093 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:04:45.093 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:04:45.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:04:45.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:04:45.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:04:45.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:04:45.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:04:45.101 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:04:45.101 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:04:45.101 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:04:45.526 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:04:45.563 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:45.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:45.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:45.568 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:46.004 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:04:46.481 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:04:46.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:46.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:46.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:46.570 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:46.959 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:04:47.437 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:04:47.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:47.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:47.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:47.571 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:47.915 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:04:48.169 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:04:48.169 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:04:48.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:48.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:48.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:48.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:48.178 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:48.178 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:48.178 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:48.178 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:48.178 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:04:48.178 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:48.178 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:48.178 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:48.178 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:48.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:48.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:48.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:48.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:48.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:53.183 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:53.183 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:53.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:53.183 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:53.183 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:53.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:53.192 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:53.194 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:53.194 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:53.195 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:04:53.195 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:04:53.200 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:04:53.200 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:04:53.201 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:53.201 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:53.201 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:53.202 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:04:53.202 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:04:53.202 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:04:53.203 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:53.204 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:04:53.205 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:04:53.205 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:53.205 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:53.205 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:53.206 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:04:53.206 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:04:53.206 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:04:53.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:53.207 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:04:53.207 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:04:53.207 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:53.207 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:04:53.207 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:53.208 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:04:53.208 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:04:53.208 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:04:53.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:53.210 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:04:53.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:53.211 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:04:53.211 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:04:53.211 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:04:53.211 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:53.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:04:53.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:53.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:53.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:04:53.216 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:04:53.696 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:04:53.742 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:04:53.743 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:04:53.744 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:04:53.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:04:54.170 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:04:54.216 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:54.218 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:54.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:54.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:54.648 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:04:55.128 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:04:55.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:55.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:55.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:55.225 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:55.609 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:04:55.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:04:55.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:04:55.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:04:55.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:04:55.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:04:55.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:04:55.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:04:55.758 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:04:55.758 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:04:55.758 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:04:55.758 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=543 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=543 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=543 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=543 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=543 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=543 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=543 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=543 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:04:55.758 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:00.762 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:00.763 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:00.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:00.763 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:00.763 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:00.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:00.770 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:00.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:00.770 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:00.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:00.770 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:05:00.772 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:05:00.772 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:05:00.772 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:00.772 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:00.772 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:00.773 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:05:00.773 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:00.773 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:05:00.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:00.775 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:05:00.775 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:05:00.776 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:00.776 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:00.776 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:00.776 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:05:00.776 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:00.776 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:05:00.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:00.778 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:05:00.778 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:05:00.778 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:00.778 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:00.778 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:00.778 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:05:00.779 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:00.779 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:05:00.779 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:00.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:05:00.782 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:05:00.782 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:05:00.782 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:00.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:00.786 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:05:01.269 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:05:01.310 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:05:01.312 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:05:01.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:01.314 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:05:01.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:05:01.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:05:01.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:05:01.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:01.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:01.746 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:05:01.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:01.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:01.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:01.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:02.224 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:05:02.702 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:05:02.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:02.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:02.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:02.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:03.181 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:05:03.660 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:05:03.787 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:03.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:03.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:03.790 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:04.138 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:05:04.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:04.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:04.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:04.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:04.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:04.379 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:04.379 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:04.379 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:04.380 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:04.380 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:04.380 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:05:04.380 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:04.380 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:04.380 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:04.380 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:04.380 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:04.381 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:04.381 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:04.381 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:04.381 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:09.379 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:09.379 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:09.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:09.382 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:09.382 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:09.383 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:09.390 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:09.391 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:09.391 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:09.392 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:09.392 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:05:09.395 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:05:09.395 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:05:09.395 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:09.396 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:09.396 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:09.396 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:05:09.397 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:09.397 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:05:09.397 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:09.398 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:05:09.399 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:05:09.399 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:09.399 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:09.399 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:09.400 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:05:09.400 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:09.400 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:05:09.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:09.401 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:05:09.401 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:05:09.401 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:09.401 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:09.401 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:09.401 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:05:09.401 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:09.401 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:05:09.401 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:09.403 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:05:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:05:09.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:05:09.404 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:05:09.404 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:05:09.404 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:09.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:09.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:09.409 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:05:09.894 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:05:09.925 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:05:09.926 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:05:09.926 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:05:09.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:09.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:05:09.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:05:09.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:05:09.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:09.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:09.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:09.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:09.959 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:09.959 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:09.959 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:09.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:09.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:09.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:09.963 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:09.963 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:09.963 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:09.963 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:05:09.963 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:09.963 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:09.963 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:09.963 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:09.963 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:09.964 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:09.964 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:14.965 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:14.965 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:14.965 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:14.965 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:14.965 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:14.965 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:14.974 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:14.976 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:14.977 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:14.977 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:14.977 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:05:14.981 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:05:14.982 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:05:14.982 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:14.982 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:14.983 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:14.983 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:05:14.984 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:14.984 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:05:14.984 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:14.985 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:05:14.985 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:05:14.985 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:14.985 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:14.986 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:14.986 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:05:14.986 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:14.986 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:05:14.986 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:14.988 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:05:14.988 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:05:14.988 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:14.988 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:14.988 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:14.988 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:05:14.989 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:14.989 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:05:14.989 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:14.992 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:05:14.992 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:05:14.992 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:05:14.993 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:14.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:14.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:14.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:14.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:14.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:14.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:14.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:14.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:14.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:14.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:14.997 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:05:15.479 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:05:15.523 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:05:15.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:15.524 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:05:15.524 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:05:15.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:05:15.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:05:15.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:05:15.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:15.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:15.955 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:05:15.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:15.997 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:15.999 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:16.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:16.437 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:05:16.919 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:05:16.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:16.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:17.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:17.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:17.398 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:05:17.876 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:05:18.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:18.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:18.001 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:18.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:18.354 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:05:18.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:18.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:18.580 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:18.581 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:18.581 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:18.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:18.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:18.584 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:18.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:18.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:18.584 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:18.584 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:18.584 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:05:18.584 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:18.584 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:18.584 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:18.584 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:18.584 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:18.584 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:18.584 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=765 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:23.584 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:23.585 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:23.586 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:23.587 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:23.587 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:23.588 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:23.594 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:23.596 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:23.596 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:23.596 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:23.596 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:05:23.598 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:05:23.599 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:05:23.599 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:23.599 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:23.600 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:23.600 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:05:23.600 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:23.600 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:05:23.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:23.601 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:05:23.601 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:05:23.601 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:23.601 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:23.601 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:23.601 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:05:23.601 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:23.602 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:05:23.602 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:23.604 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:05:23.604 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:05:23.604 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:23.604 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:23.604 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:23.604 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:05:23.604 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:23.604 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:05:23.604 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:23.607 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:05:23.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:05:23.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:23.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:23.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:23.609 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:05:23.609 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:05:23.609 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:05:23.609 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:05:23.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:23.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:23.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:23.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:05:23.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:23.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:23.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:23.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:23.614 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:05:24.097 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:05:24.144 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:05:24.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:24.147 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:05:24.150 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:05:24.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:05:24.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:05:24.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:05:24.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:24.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:24.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:24.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:24.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:24.212 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:24.212 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:24.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:24.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:24.215 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:24.215 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:24.216 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:24.216 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:24.216 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:05:24.216 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=128 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=128 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=128 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:24.216 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:29.218 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:29.218 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:29.218 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:29.218 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:29.218 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:29.218 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:29.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:29.229 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:29.229 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:29.230 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:29.230 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:05:29.234 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:05:29.234 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:05:29.235 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:29.235 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:29.235 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:29.236 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:05:29.236 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:29.236 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:05:29.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:29.237 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:05:29.237 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:05:29.238 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:29.238 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:29.238 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:29.238 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:05:29.238 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:29.238 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:05:29.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:29.240 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:05:29.240 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:05:29.241 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:29.241 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:29.241 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:29.241 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:05:29.241 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:29.241 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:05:29.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:29.244 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:05:29.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:05:29.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:05:29.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:05:29.244 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:05:29.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:05:29.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:05:29.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:05:29.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:05:29.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:05:29.245 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:05:29.245 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:05:29.245 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:05:29.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:29.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:29.250 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:05:29.734 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:05:29.772 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:05:29.775 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:05:29.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:29.777 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:05:29.787 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:29.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:29.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:29.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:29.791 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:29.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:29.792 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:29.792 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:29.792 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:29.792 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:29.792 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:05:29.793 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:29.793 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:29.793 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:29.793 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:29.793 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:29.793 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:29.793 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:34.791 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:34.792 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:34.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:34.795 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:34.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:34.796 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:34.801 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:34.801 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:34.801 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:34.802 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:34.802 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:05:34.805 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:05:34.805 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:05:34.806 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:34.806 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:34.806 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:34.806 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:05:34.806 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:34.806 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:05:34.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:34.808 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:05:34.808 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:05:34.808 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:34.808 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:34.809 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:34.809 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:05:34.809 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:34.809 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:05:34.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:34.810 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:05:34.810 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:05:34.810 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:34.810 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:34.811 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:34.811 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:05:34.811 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:34.811 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:05:34.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:34.813 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:05:34.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:05:34.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:05:34.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:05:34.813 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:05:34.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:05:34.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:05:34.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:05:34.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:05:34.814 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:05:34.814 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:05:34.814 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:34.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:34.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:34.819 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:05:35.301 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:05:35.344 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:05:35.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:35.348 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:05:35.351 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:05:35.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:35.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:35.366 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:35.367 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:35.368 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:35.368 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:35.368 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:35.368 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:35.368 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:35.368 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:35.368 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:05:35.368 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:35.368 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:35.368 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:35.368 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:35.368 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:35.368 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.370 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:40.370 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:40.372 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:40.372 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:40.372 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:40.372 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:40.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:40.380 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:40.380 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:40.380 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:40.381 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:05:40.383 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:05:40.383 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:05:40.384 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:40.384 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:40.384 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:40.385 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:05:40.385 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:40.385 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:05:40.385 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:40.386 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:05:40.386 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:05:40.386 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:40.387 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:40.387 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:40.387 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:05:40.387 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:40.387 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:05:40.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:40.388 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:05:40.388 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:05:40.388 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:40.388 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:40.389 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:40.389 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:05:40.389 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:40.389 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:05:40.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:40.391 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:05:40.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:05:40.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:05:40.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:05:40.391 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:05:40.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:05:40.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:05:40.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:05:40.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:05:40.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:40.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:05:40.392 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:05:40.392 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:05:40.392 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:40.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:40.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:40.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:40.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:40.397 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:05:40.880 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:05:40.918 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:05:40.920 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:05:40.923 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:05:40.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:40.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:40.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:40.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:40.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:40.936 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:40.936 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:40.936 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:40.936 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:40.936 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:40.936 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:40.936 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:40.937 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:45.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:45.939 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:45.940 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:45.942 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:45.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:45.943 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:45.950 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:45.951 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:45.951 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:45.951 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:45.951 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:05:45.952 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:05:45.952 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:05:45.953 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:45.953 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:45.953 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:45.953 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:05:45.954 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:45.954 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:05:45.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:45.955 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:05:45.955 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:05:45.955 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:45.955 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:45.956 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:45.956 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:05:45.956 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:45.956 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:05:45.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:45.957 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:05:45.958 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:05:45.958 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:45.958 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:45.958 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:45.958 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:05:45.958 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:45.958 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:05:45.958 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:45.961 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:05:45.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:05:45.961 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:05:45.961 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:05:45.961 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:45.962 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:05:45.962 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:05:45.962 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:05:45.963 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:05:45.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:45.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:45.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:45.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:05:45.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:45.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:45.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:45.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:45.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:45.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:45.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:45.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:45.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:45.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:45.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:45.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:45.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:45.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:45.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:45.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:45.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:45.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:45.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:45.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:45.967 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:05:46.451 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:05:46.494 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:05:46.496 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:05:46.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:46.498 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:05:46.511 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:46.512 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:46.512 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:46.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:46.515 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:46.515 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:46.515 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:46.516 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:46.516 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:46.516 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:05:46.516 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:46.516 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:46.516 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:46.516 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:46.517 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:46.517 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:51.518 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:51.518 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:51.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:51.518 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:51.519 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:51.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:51.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:51.529 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:51.529 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:51.530 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:05:51.530 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:05:51.533 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:05:51.534 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:05:51.534 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:51.535 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:51.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:51.535 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:05:51.536 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:05:51.536 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:05:51.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:51.537 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:05:51.537 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:05:51.537 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:51.537 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:51.538 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:51.538 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:05:51.538 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:05:51.538 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:05:51.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:51.539 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:05:51.539 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:05:51.539 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:51.539 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:05:51.539 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:51.539 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:05:51.539 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:05:51.540 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:05:51.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:05:51.542 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:05:51.542 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:05:51.542 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:51.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:51.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:05:51.547 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:05:52.031 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:05:52.068 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:05:52.070 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:05:52.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:52.072 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:05:52.511 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:05:52.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:52.545 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:52.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:52.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:52.990 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:05:53.469 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:05:53.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:53.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:53.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:53.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:53.950 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:05:54.430 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:05:54.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:54.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:54.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:54.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:54.908 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:05:55.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:05:55.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:05:55.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:05:55.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:05:55.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:05:55.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:05:55.093 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:05:55.093 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:05:55.377 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:05:55.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:55.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:55.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:55.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:55.847 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:05:56.325 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:05:56.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:56.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:56.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:56.551 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:56.802 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:05:57.280 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:05:57.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:05:57.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:05:57.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:05:57.409 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:05:57.410 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:05:57.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:05:57.410 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:05:57.413 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:05:57.413 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:05:57.413 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:05:57.414 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:05:57.414 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:05:57.414 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:05:57.414 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:05:57.414 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:57.414 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:57.415 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:57.415 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:57.415 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:57.415 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:57.415 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:57.415 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1255 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:57.415 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1255 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:57.415 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1255 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:57.415 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1255 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:57.415 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1255 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:05:57.415 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1255 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:02.414 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:02.414 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:02.418 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:02.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:02.418 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:02.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:02.424 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:02.425 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:02.425 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:02.426 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:02.426 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:06:02.429 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:06:02.429 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:06:02.429 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:02.429 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:02.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:02.430 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:06:02.431 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:02.431 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:06:02.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:02.432 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:06:02.432 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:06:02.432 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:02.432 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:02.433 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:02.433 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:06:02.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:02.433 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:06:02.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:02.435 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:06:02.435 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:06:02.435 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:02.435 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:02.435 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:02.435 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:06:02.435 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:02.436 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:06:02.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:02.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:02.440 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:06:02.440 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:06:02.440 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:06:02.440 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:06:02.440 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:02.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:02.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:02.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:06:02.440 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:02.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:02.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:02.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:02.440 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:02.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:02.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:02.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:02.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:02.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:02.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:02.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:02.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:02.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:02.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:02.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:02.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:02.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:02.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:02.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:02.445 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:06:02.928 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:06:02.972 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:06:02.974 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:06:02.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:02.977 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:06:03.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:03.003 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:03.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:06:03.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:03.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:03.020 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:03.020 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:03.022 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:03.022 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:03.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:03.022 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:03.022 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:03.022 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:03.022 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:06:03.022 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:03.022 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:03.022 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:03.022 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:03.022 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:03.022 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:03.022 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:08.022 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:08.022 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:08.024 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:08.025 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:08.026 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:08.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:08.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:08.036 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:08.036 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:08.037 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:08.037 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:06:08.040 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:06:08.040 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:06:08.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:08.041 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:08.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:08.041 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:06:08.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:08.041 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:06:08.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:08.043 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:06:08.043 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:06:08.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:08.044 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:08.044 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:08.044 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:06:08.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:08.044 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:06:08.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:08.046 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:06:08.046 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:06:08.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:08.046 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:08.046 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:08.046 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:06:08.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:08.046 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:06:08.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:08.049 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:06:08.050 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:06:08.050 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:06:08.050 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:08.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:08.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:08.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:08.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:08.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:08.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:08.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:08.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:08.055 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:06:08.537 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:06:08.584 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:06:08.586 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:06:08.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:08.588 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:06:08.610 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:08.610 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:08.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:06:08.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:08.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:08.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:08.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:08.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:08.629 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:08.632 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:08.632 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:08.632 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:08.632 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:08.632 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:08.632 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:08.632 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:06:08.633 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:08.633 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:08.633 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:08.633 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:08.633 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:08.633 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:13.632 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:13.633 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:13.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:13.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:13.645 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:13.645 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:13.649 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:13.651 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:13.651 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:13.651 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:13.652 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:06:13.656 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:06:13.657 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:06:13.657 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:13.657 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:13.657 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:13.657 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:06:13.657 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:13.657 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:06:13.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:13.660 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:06:13.660 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:06:13.660 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:13.660 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:13.660 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:13.660 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:06:13.661 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:13.661 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:06:13.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:13.663 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:06:13.663 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:06:13.663 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:13.663 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:13.663 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:13.663 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:06:13.664 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:13.664 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:06:13.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:13.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:13.668 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:06:13.668 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:06:13.668 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:06:13.668 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:06:13.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:13.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:13.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:13.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:06:13.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:13.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:13.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:13.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:13.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:13.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:13.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:13.673 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:06:14.157 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:06:14.190 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:06:14.191 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:06:14.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:14.192 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:06:14.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:14.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:14.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:06:14.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:14.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:14.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:14.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:14.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:14.231 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:14.231 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:14.232 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:14.232 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:14.232 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:14.232 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:14.232 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:14.233 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:06:14.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:14.233 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:14.233 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:14.233 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:14.233 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:14.233 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:14.233 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:14.233 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:19.235 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:19.235 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:19.236 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:19.238 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:19.238 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:19.239 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:19.242 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:19.242 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:19.242 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:19.242 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:19.242 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:06:19.243 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:06:19.243 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:06:19.243 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:19.243 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:19.243 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:19.243 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:06:19.244 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:19.244 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:06:19.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:19.245 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:06:19.246 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:06:19.246 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:19.246 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:19.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:19.246 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:06:19.246 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:19.246 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:06:19.246 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:19.248 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:06:19.248 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:06:19.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:19.248 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:19.248 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:19.248 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:06:19.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:19.248 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:06:19.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:19.251 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:06:19.252 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:06:19.252 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:06:19.252 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:19.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:19.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:19.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:19.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:19.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:19.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:19.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:19.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:19.257 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:06:19.740 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:06:19.784 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:06:19.786 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:06:19.788 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:06:19.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:19.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:19.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:19.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:06:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:19.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:19.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:19.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:19.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:19.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:19.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:19.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:19.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:19.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:19.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:19.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:19.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:19.829 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:19.829 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:19.829 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:06:19.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:19.829 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:19.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:19.830 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:19.830 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:19.830 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:19.830 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:19.830 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:19.830 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:19.830 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:19.830 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:24.831 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:24.831 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:24.832 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:24.834 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:24.835 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:24.835 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:24.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:24.843 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:24.843 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:24.843 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:24.843 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:06:24.845 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:06:24.846 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:06:24.846 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:24.846 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:24.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:24.847 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:06:24.847 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:24.847 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:06:24.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:24.848 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:06:24.848 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:06:24.848 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:24.848 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:24.848 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:06:24.848 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:24.848 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:24.848 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:06:24.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:24.851 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:06:24.851 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:06:24.851 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:24.851 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:24.851 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:24.851 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:06:24.851 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:24.851 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:06:24.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:24.854 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:06:24.854 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:06:24.854 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:06:24.854 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:24.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:24.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:24.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:24.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:24.859 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:06:25.342 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:06:25.381 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:06:25.383 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:06:25.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:25.385 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:06:25.387 [DEBUG] fake_trx.py:382 (BTS@172.18.201.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-05 02:06:25.387 [INFO] fake_trx.py:385 (BTS@172.18.201.20:5700) Artificial TRXC delay set to 200
2026-03-05 02:06:25.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-05 02:06:25.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:25.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:25.822 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:06:26.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:26.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:26.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:26.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:26.214 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:26.300 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:06:26.779 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:06:26.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:27.020 [DEBUG] fake_trx.py:382 (BTS@172.18.201.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-05 02:06:27.020 [INFO] fake_trx.py:385 (BTS@172.18.201.20:5700) Artificial TRXC delay set to 0
2026-03-05 02:06:27.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-05 02:06:27.020 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:27.020 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:27.020 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:27.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:27.030 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:27.030 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:27.030 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:27.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:27.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:27.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:27.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:27.031 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:27.031 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:27.031 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:27.031 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:06:27.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:27.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:27.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:27.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:27.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:27.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:27.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:32.033 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:32.033 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:32.034 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:32.036 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:32.037 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:32.038 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:32.048 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:32.049 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:32.049 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:32.049 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:32.049 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:06:32.051 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:06:32.052 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:06:32.052 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:32.052 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:32.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:32.053 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:06:32.053 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:32.053 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:06:32.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:32.055 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:06:32.055 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:06:32.055 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:32.055 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:32.055 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:06:32.055 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:32.055 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:32.055 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:06:32.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:32.057 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:06:32.057 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:06:32.057 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:32.057 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:32.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:32.058 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:06:32.058 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:32.058 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:06:32.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:32.060 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:06:32.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:06:32.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:06:32.060 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:06:32.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:06:32.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:06:32.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:06:32.061 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:06:32.061 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:06:32.061 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:32.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:32.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:32.066 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:06:32.549 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:06:32.592 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:06:32.594 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:06:32.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:32.596 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:06:32.598 [DEBUG] fake_trx.py:382 (BTS@172.18.201.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-05 02:06:32.599 [INFO] fake_trx.py:385 (BTS@172.18.201.20:5700) Artificial TRXC delay set to 200
2026-03-05 02:06:32.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-05 02:06:32.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:33.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:33.029 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:06:33.228 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:33.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:33.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:33.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:33.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:33.511 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:06:33.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:33.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:33.990 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:06:34.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:34.232 [DEBUG] fake_trx.py:382 (BTS@172.18.201.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-05 02:06:34.232 [INFO] fake_trx.py:385 (BTS@172.18.201.20:5700) Artificial TRXC delay set to 0
2026-03-05 02:06:34.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-05 02:06:34.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:34.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:34.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:34.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:34.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:34.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:34.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:34.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:34.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:34.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:34.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:34.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:34.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:34.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:34.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:34.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:34.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:34.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:34.241 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:34.241 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:34.241 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:34.241 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:34.241 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:34.241 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:34.241 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:06:34.242 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:34.242 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:34.242 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:34.242 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:34.242 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:34.242 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:34.242 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=464 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:39.242 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:39.242 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:39.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:39.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:39.246 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:39.247 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:39.254 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:39.254 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:39.255 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:39.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:39.255 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:06:39.257 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:06:39.258 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:06:39.258 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:39.258 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:39.258 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:39.258 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:06:39.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:39.259 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:06:39.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:39.260 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:06:39.260 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:06:39.260 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:39.260 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:39.260 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:39.260 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:06:39.260 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:39.260 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:06:39.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:39.262 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:06:39.262 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:06:39.262 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:39.262 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:39.262 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:39.262 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:06:39.262 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:39.262 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:06:39.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:39.265 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:06:39.265 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:06:39.265 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:06:39.266 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:39.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:39.270 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:06:39.753 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:06:39.794 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:06:39.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:39.798 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:06:39.800 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:06:39.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:39.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:39.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:06:39.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:39.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:39.841 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:39.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:39.841 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:39.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:39.842 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:39.842 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:39.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:39.843 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:39.843 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:39.843 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:39.843 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:06:39.843 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:39.843 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:39.843 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:39.843 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:39.843 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:39.843 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:39.843 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:44.845 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:44.845 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:44.846 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:44.847 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:44.847 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:44.848 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:44.854 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:44.855 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:44.855 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:44.855 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:44.855 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:06:44.858 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:06:44.858 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:06:44.858 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:44.859 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:44.859 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:44.859 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:06:44.859 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:44.859 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:06:44.859 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:44.861 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:06:44.861 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:06:44.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:44.862 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:44.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:44.862 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:06:44.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:44.862 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:06:44.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:44.864 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:06:44.864 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:06:44.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:44.864 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:44.864 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:44.864 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:06:44.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:44.864 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:06:44.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:44.867 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:06:44.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:06:44.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:06:44.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:06:44.867 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:06:44.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:06:44.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:06:44.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:06:44.868 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:06:44.868 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:06:44.868 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:44.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:44.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:44.873 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:06:45.355 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:06:45.400 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:06:45.402 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:06:45.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:45.404 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:06:45.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:45.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:45.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:06:45.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:45.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:45.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:45.437 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:45.437 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:45.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:45.439 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:45.439 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:45.439 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:45.439 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:45.439 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:45.439 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:45.439 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:06:45.439 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:45.439 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:45.439 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:45.440 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:45.440 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:45.440 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:06:50.441 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:06:50.441 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:06:50.442 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:50.443 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:50.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:50.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:50.451 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:06:50.452 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:50.452 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:50.452 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:06:50.453 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:06:50.454 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:06:50.455 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:06:50.455 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:50.455 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:50.455 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:06:50.456 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:06:50.456 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:06:50.456 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:06:50.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:50.457 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:06:50.457 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:06:50.457 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:50.457 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:50.457 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:06:50.457 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:06:50.458 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:06:50.458 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:06:50.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:50.459 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:06:50.459 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:06:50.459 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:50.459 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:06:50.459 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:06:50.459 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:06:50.459 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:06:50.459 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:06:50.460 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:50.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:06:50.463 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:06:50.463 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:06:50.463 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:50.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:06:50.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:06:50.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:50.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:06:50.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:50.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:50.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:50.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:06:50.468 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:06:50.951 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:06:50.991 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:06:50.992 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:06:50.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:50.994 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:06:51.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:51.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:51.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:06:51.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:51.017 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:06:51.017 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:06:51.017 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:06:51.017 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:06:51.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:51.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:06:51.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:06:51.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:51.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:51.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:51.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:51.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:51.116 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:51.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:51.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:51.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:06:51.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:51.135 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:06:51.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:06:51.135 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:06:51.135 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:06:51.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:51.198 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:06:51.198 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:06:51.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:51.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:51.428 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:06:51.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:51.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:51.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:51.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:51.906 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:06:52.384 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:06:52.467 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:52.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:52.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:52.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:52.862 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:06:53.341 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:06:53.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:53.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:53.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:53.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:53.818 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:06:54.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:54.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:54.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:54.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:54.229 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:54.229 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:54.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:06:54.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:54.231 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:06:54.231 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:06:54.231 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:06:54.231 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:06:54.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:54.236 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:06:54.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:06:54.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:54.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:54.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:54.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:54.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:54.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:54.295 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:06:54.314 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:54.314 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:54.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:06:54.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:54.315 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:06:54.315 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:06:54.315 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:06:54.315 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:06:54.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:54.350 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:06:54.350 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:06:54.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:54.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:54.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:54.470 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:54.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:54.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:54.772 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:06:55.250 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:06:55.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:06:55.471 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:06:55.471 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:06:55.474 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:06:55.727 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:06:56.205 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:06:56.682 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:06:57.160 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:06:57.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:57.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:57.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:57.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:57.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:06:57.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:06:57.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:06:57.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:57.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:06:57.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:06:57.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:06:57.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:06:57.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:06:57.394 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:06:57.394 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:06:57.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:57.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:06:57.638 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:06:58.116 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:06:58.593 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:06:59.071 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:06:59.549 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:07:00.026 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:07:00.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:00.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:00.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:00.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:00.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:00.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:00.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:00.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:00.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:00.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:00.422 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:00.422 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:00.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:00.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:00.451 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:00.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:00.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:00.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:00.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:00.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:00.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:00.504 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:07:00.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:00.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:00.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:00.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:00.518 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:00.518 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:00.518 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:00.518 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:00.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:00.561 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:00.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:00.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:00.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:00.981 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:07:01.459 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:07:01.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:01.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:01.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:01.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:01.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:01.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:01.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:01.691 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:01.691 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:01.691 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:01.691 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:01.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:01.750 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:01.751 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:01.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:01.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:01.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:01.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:01.843 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:01.843 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:01.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:01.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:01.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:01.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:01.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:01.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:01.862 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:01.862 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:01.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:01.883 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:01.883 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:01.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:01.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:01.936 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:07:02.414 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:07:02.892 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:07:03.370 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:07:03.848 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:07:04.326 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:07:04.804 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:07:04.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:04.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:04.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:04.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:04.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:04.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:04.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:04.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:04.910 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:04.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:04.910 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:04.910 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:04.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:04.951 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:04.952 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:04.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:04.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:05.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:05.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:05.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:05.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:05.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:05.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:05.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:05.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:05.034 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:05.034 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:05.034 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:05.034 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:05.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:05.038 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:05.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:05.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:05.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:05.282 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:07:05.760 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:07:06.239 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:07:06.716 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:07:07.195 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:07:07.673 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:07:08.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:08.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:08.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:08.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:08.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:08.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:08.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:08.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:08.065 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:08.065 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:08.065 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:08.065 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:08.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:08.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:08.097 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:08.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:08.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:08.151 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:07:08.628 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:07:09.106 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:07:09.584 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:07:10.081 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:07:10.559 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:07:11.037 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:07:11.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:11.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:11.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:11.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:11.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:11.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:11.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:11.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:11.120 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:11.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:11.120 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:11.120 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:11.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:11.129 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:11.129 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:11.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:11.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:11.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:11.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:11.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:11.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:11.228 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:11.228 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:11.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:11.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:11.230 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:11.230 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:11.230 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:11.230 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:11.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:11.283 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:11.284 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:11.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:11.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:11.515 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:07:11.993 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:07:12.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:12.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:12.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:12.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:12.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:12.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:12.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:12.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:12.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:12.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:12.190 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:12.190 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:12.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:12.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:12.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:12.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:12.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:12.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:12.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:12.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:12.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:12.466 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:07:12.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:12.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:12.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:12.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:12.468 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:12.468 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:12.468 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:12.468 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:12.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:12.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:12.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:12.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:12.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:12.943 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:07:13.421 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:07:13.899 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:07:14.377 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:07:14.855 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:07:15.333 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:07:15.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:15.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:15.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:15.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:15.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:15.540 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:15.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:15.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:15.541 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:15.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:15.541 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:15.541 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:15.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:15.575 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:15.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:15.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:15.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:15.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:15.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:15.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:15.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:15.809 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:07:15.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:15.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:15.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:15.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:15.819 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:15.819 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:15.819 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:15.819 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:15.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:15.865 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:15.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:15.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:15.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:16.287 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:07:16.765 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:07:17.243 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:07:17.721 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:07:18.199 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:07:18.676 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:07:18.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:18.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:18.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:18.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:18.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:18.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:18.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:18.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:18.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:18.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:18.889 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:18.889 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:18.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:18.915 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:18.915 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:18.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:18.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:19.154 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:07:19.631 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:07:20.109 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 02:07:20.587 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 02:07:21.064 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 02:07:21.542 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 02:07:21.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:21.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:21.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:21.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:21.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:21.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:21.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:21.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:21.941 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:21.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:21.942 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:21.942 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:21.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:21.967 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:21.967 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:21.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:21.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:22.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:22.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:22.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:22.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:22.019 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 02:07:22.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:22.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:22.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:22.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:22.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:22.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:22.029 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:22.029 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:22.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:22.075 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:22.075 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:22.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:22.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:22.497 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 02:07:22.974 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 02:07:23.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:23.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:23.017 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:23.017 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:23.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:23.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:23.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:23.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:23.036 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:23.036 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:23.036 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:23.036 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:23.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:23.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:23.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:23.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:23.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:23.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:23.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:23.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:23.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:23.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:23.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:23.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:23.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:23.151 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:23.151 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:23.151 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:23.151 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:23.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:23.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:23.157 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:23.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:23.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:23.451 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 02:07:23.930 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 02:07:24.408 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 02:07:24.887 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 02:07:25.365 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 02:07:25.843 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 02:07:26.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:26.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:26.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:26.165 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:26.181 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:26.182 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:26.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:26.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:26.183 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:26.183 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:26.183 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:26.183 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:26.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:26.226 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:26.227 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:26.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:26.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:26.320 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 02:07:26.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:26.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:26.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:26.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:26.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:26.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:26.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:26.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:26.498 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:26.498 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:26.498 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:26.498 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:26.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:26.503 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:26.503 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:26.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:26.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:26.797 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 02:07:27.274 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 02:07:27.752 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 02:07:28.229 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 02:07:28.707 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 02:07:29.184 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 02:07:29.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:29.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:29.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:29.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:29.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:29.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:29.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:29.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:29.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:29.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:29.529 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:29.529 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:29.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:29.566 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:29.566 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:29.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:29.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:29.660 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 02:07:30.138 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 02:07:30.616 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 02:07:31.093 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 02:07:31.572 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 02:07:32.050 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 02:07:32.528 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 02:07:32.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:32.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:32.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:32.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:32.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:32.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:32.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:32.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:32.594 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:32.594 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:32.594 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:32.594 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:32.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:32.627 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:32.627 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:32.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:32.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:32.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:32.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:32.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:32.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:32.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:32.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:32.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:32.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:32.700 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:32.700 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:32.700 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:32.700 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:32.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:32.713 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:32.713 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:32.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:32.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:33.004 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 02:07:33.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:33.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:33.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:33.474 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:33.482 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 02:07:33.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:07:33.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:07:33.485 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:07:33.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:07:33.488 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:07:33.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:07:33.488 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:07:33.488 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:07:33.489 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:07:33.489 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:07:33.489 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:07:38.488 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:07:38.489 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:07:38.490 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:07:38.492 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:07:38.492 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:07:38.492 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:07:38.499 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:07:38.500 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:07:38.500 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:38.501 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:07:38.501 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:07:38.503 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:07:38.504 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:07:38.504 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:07:38.504 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:38.505 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:07:38.505 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:07:38.505 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:07:38.505 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:07:38.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:07:38.506 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:07:38.506 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:07:38.507 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:07:38.507 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:38.507 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:07:38.507 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:07:38.507 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:07:38.507 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:07:38.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:07:38.508 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:07:38.508 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:07:38.509 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:07:38.509 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:38.509 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:07:38.509 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:07:38.509 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:07:38.509 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:07:38.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:07:38.512 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:07:38.512 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:07:38.512 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:38.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:38.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:38.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:38.517 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:07:39.001 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:07:39.041 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:07:39.044 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:07:39.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:39.046 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:07:39.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:39.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:39.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:39.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:39.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:39.077 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:39.078 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:39.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:39.104 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:39.104 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:39.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:39.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:39.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:39.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:39.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:39.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:39.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:39.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:39.181 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:39.181 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:39.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:39.185 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:39.185 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:39.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:39.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.281 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:39.281 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:39.299 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:39.299 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:39.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:39.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:39.300 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:39.300 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:39.300 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:39.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:39.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:39.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:39.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:39.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.398 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:39.399 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:39.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:39.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:39.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:39.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.416 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:39.416 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:39.416 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:39.416 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:39.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:39.420 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:39.420 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:39.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.475 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:07:39.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:07:39.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:07:39.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:07:39.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:07:39.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:39.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:39.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:39.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:39.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:07:39.568 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:07:39.569 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:07:39.569 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:07:39.572 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:07:39.572 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:07:39.573 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:07:39.573 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:07:39.573 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:07:39.573 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:07:39.573 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:07:39.573 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=227 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:39.573 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=227 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:39.573 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=227 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:39.573 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=227 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:39.573 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=227 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:39.573 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=227 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:44.574 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:07:44.574 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:07:44.575 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:07:44.575 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:07:44.575 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:07:44.575 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:07:44.582 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:07:44.583 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:07:44.583 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:44.584 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:07:44.584 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:07:44.587 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:07:44.587 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:07:44.588 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:07:44.588 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:44.588 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:07:44.588 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:07:44.588 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:07:44.588 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:07:44.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:07:44.591 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:07:44.591 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:07:44.591 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:07:44.591 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:44.591 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:07:44.592 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:07:44.592 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:07:44.592 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:07:44.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:07:44.594 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:07:44.594 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:07:44.594 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:07:44.594 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:44.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:07:44.594 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:07:44.594 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:07:44.594 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:07:44.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:44.597 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:07:44.597 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:07:44.597 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:07:44.598 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:44.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:44.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:44.602 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:07:45.086 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:07:45.130 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:07:45.132 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:07:45.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:45.135 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:07:45.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:45.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:45.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:45.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:45.165 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:45.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:45.165 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:45.165 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:45.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:45.189 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:45.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:45.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:45.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:45.563 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:07:45.600 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:07:45.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:07:45.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:07:45.604 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:07:46.041 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:07:46.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:46.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:46.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:46.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:46.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:46.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:46.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:46.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:46.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:46.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:46.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:46.082 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:46.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:46.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:46.085 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:46.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:46.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:46.518 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:07:46.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:07:46.602 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:07:46.602 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:07:46.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:07:46.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:46.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:46.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:46.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:46.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:46.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:46.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:46.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:46.809 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:46.809 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:46.809 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:46.809 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:46.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:46.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:46.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:46.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:46.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:46.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:46.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:46.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:46.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:46.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:46.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:46.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:46.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:46.981 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:46.981 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:46.981 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:46.981 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:46.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:46.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:46.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:46.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:46.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:46.995 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:07:47.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:47.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:47.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:47.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:47.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:07:47.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:07:47.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:07:47.400 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:07:47.402 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:07:47.402 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:07:47.402 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:07:47.402 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:07:47.402 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:07:47.402 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:07:47.402 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:07:47.402 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:47.402 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:47.402 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:47.402 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:47.402 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:47.402 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:47.402 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:52.402 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:07:52.403 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:07:52.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:07:52.406 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:07:52.406 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:07:52.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:07:52.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:07:52.417 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:07:52.417 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:52.417 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:07:52.418 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:07:52.421 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:07:52.421 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:07:52.421 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:07:52.422 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:52.422 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:07:52.422 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:07:52.423 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:07:52.423 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:07:52.423 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:07:52.424 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:07:52.424 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:07:52.424 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:07:52.424 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:52.424 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:07:52.424 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:07:52.424 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:07:52.424 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:07:52.424 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:07:52.426 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:07:52.426 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:07:52.426 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:07:52.426 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:52.426 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:07:52.426 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:07:52.426 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:07:52.427 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:07:52.427 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:07:52.429 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:07:52.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:07:52.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:07:52.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:07:52.429 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:07:52.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:07:52.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:07:52.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:07:52.430 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:07:52.430 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:07:52.430 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:52.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:52.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:52.435 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:07:52.918 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:07:52.965 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:07:52.967 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:07:52.969 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:07:52.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:52.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:52.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:52.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:52.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:52.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:52.995 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:52.995 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:52.995 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:53.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:53.017 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:53.017 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:53.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:53.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:53.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:53.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:53.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:53.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:53.205 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:53.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:53.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:53.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:53.207 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:53.207 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:53.207 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:53.207 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:53.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:53.256 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:53.256 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:53.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:53.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:53.394 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:07:53.434 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:07:53.435 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:07:53.437 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:07:53.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:07:53.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:53.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:53.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:53.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:53.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:53.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:53.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:53.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:53.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:53.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:53.560 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:53.561 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:53.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:53.582 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:53.582 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:53.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:53.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:53.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:53.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:53.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:53.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:53.869 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:53.869 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:53.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:53.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:53.870 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:53.870 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:53.870 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:53.870 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:53.871 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:07:53.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:53.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:53.928 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:53.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:53.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:54.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:54.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:54.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:54.264 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:54.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:07:54.273 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:07:54.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:07:54.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:07:54.276 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:07:54.277 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:07:54.277 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:07:54.277 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:07:54.277 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:07:54.277 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:07:54.277 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:07:54.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:54.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:54.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:54.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:54.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:54.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:54.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:54.278 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:54.278 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:54.278 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:54.278 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:54.278 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:54.278 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:54.278 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:07:59.276 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:07:59.276 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:07:59.277 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:07:59.280 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:07:59.280 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:07:59.280 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:07:59.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:07:59.300 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:07:59.300 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:59.300 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:07:59.300 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:07:59.302 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:07:59.302 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:07:59.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:07:59.302 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:59.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:07:59.302 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:07:59.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:07:59.302 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:07:59.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:07:59.303 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:07:59.303 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:07:59.303 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:07:59.303 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:59.303 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:07:59.303 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:07:59.303 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:07:59.303 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:07:59.303 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:07:59.304 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:07:59.304 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:07:59.304 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:07:59.304 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:07:59.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:07:59.304 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:07:59.304 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:07:59.304 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:07:59.304 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:59.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:59.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:59.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:07:59.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:59.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:59.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:59.307 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:07:59.307 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:07:59.307 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:07:59.307 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:07:59.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:59.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:59.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:59.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:07:59.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:07:59.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:07:59.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:59.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:59.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:07:59.312 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:07:59.796 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:07:59.838 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:07:59.840 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:07:59.841 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:07:59.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:59.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:07:59.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:07:59.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:07:59.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:59.863 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:59.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:59.863 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:07:59.864 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:07:59.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:07:59.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:07:59.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:07:59.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:07:59.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:00.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:00.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:00.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:00.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:00.083 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:00.083 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:00.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:00.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:00.084 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:00.084 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:00.085 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:00.085 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:00.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:00.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:00.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:00.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:00.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:00.273 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:08:00.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:00.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:00.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:00.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:00.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:00.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:00.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:00.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:00.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:00.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:00.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:00.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:00.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:00.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:00.437 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:00.437 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:00.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:00.461 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:00.461 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:00.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:00.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:00.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:00.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:00.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:00.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:00.750 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:08:00.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:00.758 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:00.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:00.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:00.759 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:00.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:00.759 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:00.759 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:00.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:00.806 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:00.806 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:00.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:00.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:01.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:01.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:01.143 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:01.143 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:01.151 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:01.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:01.151 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:01.151 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:01.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:08:01.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:08:01.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:08:01.153 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:08:01.153 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:08:01.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:08:01.153 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:08:01.153 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:01.154 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:01.154 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:01.154 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:01.154 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:01.154 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:01.154 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:06.154 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:08:06.154 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:08:06.155 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:08:06.157 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:08:06.158 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:08:06.158 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:08:06.163 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:08:06.164 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:08:06.164 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:06.165 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:08:06.165 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:08:06.168 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:08:06.168 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:08:06.168 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:08:06.168 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:06.168 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:08:06.168 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:08:06.169 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:08:06.169 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:08:06.169 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:06.171 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:08:06.171 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:08:06.171 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:08:06.171 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:06.171 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:08:06.171 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:08:06.171 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:08:06.171 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:08:06.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:06.173 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:08:06.173 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:08:06.173 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:08:06.173 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:06.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:08:06.173 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:08:06.174 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:08:06.174 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:08:06.174 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:06.176 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:08:06.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:08:06.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:08:06.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:08:06.176 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:08:06.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:08:06.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:08:06.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:08:06.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:08:06.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:06.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:06.176 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:08:06.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:08:06.177 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:08:06.177 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:08:06.177 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:06.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:06.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:06.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:06.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:06.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:06.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:06.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:06.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:06.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:06.182 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:08:06.665 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:08:06.712 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:08:06.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:06.715 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:08:06.719 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:08:06.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:06.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:06.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:06.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:06.748 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:06.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:06.749 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:06.749 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:06.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:06.761 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:06.761 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:06.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:06.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:07.142 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:08:07.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:07.180 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:07.183 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:07.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:07.620 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:08:08.097 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:08:08.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:08.181 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:08.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:08.188 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:08.574 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:08:08.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:08.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:08.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:08.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:08.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:08.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:08.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:08.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:08.641 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:08.641 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:08.641 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:08.641 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:08.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:08.671 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:08.671 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:08.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:08.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:09.051 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:08:09.181 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:09.182 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:09.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:09.189 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:09.529 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:08:10.003 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:08:10.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:10.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:10.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:10.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:10.481 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:08:10.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:10.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:10.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:10.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:10.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:10.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:10.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:10.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:10.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:10.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:10.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:10.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:10.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:10.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:10.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:10.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:10.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:10.957 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:08:11.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:11.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:11.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:11.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:11.435 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:08:11.912 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:08:12.390 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:08:12.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:12.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:12.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:12.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:12.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:12.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:12.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:12.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:12.453 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:12.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:12.453 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:12.453 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:12.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:12.492 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:12.492 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:12.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:12.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:12.867 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:08:13.345 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:08:13.820 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:08:14.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:14.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:14.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:14.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:14.293 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:14.294 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:14.294 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:14.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:14.297 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:08:14.298 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:08:14.298 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:08:14.298 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:08:14.298 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:08:14.298 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:08:14.298 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:08:14.298 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:08:14.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:14.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:14.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:14.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:14.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:14.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:14.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:14.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:14.300 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:14.300 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:14.300 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:14.300 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:14.300 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:14.300 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:19.297 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:08:19.298 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:08:19.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:08:19.302 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:08:19.302 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:08:19.302 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:08:19.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:08:19.308 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:08:19.308 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:19.309 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:08:19.309 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:08:19.311 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:08:19.312 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:08:19.312 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:08:19.312 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:19.313 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:08:19.313 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:08:19.313 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:08:19.313 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:08:19.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:19.314 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:08:19.315 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:08:19.315 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:08:19.315 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:19.315 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:08:19.315 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:08:19.316 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:08:19.316 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:08:19.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:19.317 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:08:19.317 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:08:19.317 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:08:19.317 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:19.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:08:19.317 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:08:19.317 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:08:19.317 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:08:19.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:19.320 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:08:19.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:08:19.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:08:19.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:08:19.320 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:08:19.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:08:19.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:08:19.321 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:08:19.321 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:08:19.321 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:19.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:19.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:19.326 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:08:19.809 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:08:19.851 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:08:19.853 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:08:19.856 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:08:19.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:19.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:19.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:19.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:19.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:19.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:19.880 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:19.880 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:19.880 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:19.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:19.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:19.912 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:19.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:19.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:20.286 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:08:20.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:20.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:20.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:20.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:20.764 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:08:21.241 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:08:21.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:21.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:21.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:21.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:21.719 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:08:21.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:21.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:21.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:21.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:21.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:21.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:21.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:21.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:21.788 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:21.788 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:21.788 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:21.788 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:21.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:21.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:21.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:21.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:21.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:22.196 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:08:22.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:22.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:22.328 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:22.333 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:22.674 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:08:23.149 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:08:23.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:23.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:23.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:23.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:23.627 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:08:23.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:23.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:23.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:23.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:23.976 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:23.977 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:23.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:23.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:23.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:23.978 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:23.978 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:23.978 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:24.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:24.006 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:24.006 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:24.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:24.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:24.104 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:08:24.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:24.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:24.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:24.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:24.582 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:08:25.060 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:08:25.538 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:08:25.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:25.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:25.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:25.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:25.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:25.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:25.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:25.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:25.599 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:25.599 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:25.599 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:25.599 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:25.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:25.640 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:25.640 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:25.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:25.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:26.016 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:08:26.494 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:08:26.971 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:08:27.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:27.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:27.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:27.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:27.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:27.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:27.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:27.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:27.449 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:08:27.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:08:27.452 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:08:27.452 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:08:27.452 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:08:27.452 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:08:27.452 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:08:27.452 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:08:27.453 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.453 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.453 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.453 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.453 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.453 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.454 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.454 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.454 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.454 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.454 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.454 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.454 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.454 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:27.454 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:32.456 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:08:32.456 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:08:32.456 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:08:32.456 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:08:32.456 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:08:32.456 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:08:32.462 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:08:32.463 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:08:32.463 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:32.463 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:08:32.464 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:08:32.466 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:08:32.466 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:08:32.466 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:08:32.467 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:32.467 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:08:32.467 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:08:32.468 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:08:32.468 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:08:32.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:32.469 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:08:32.469 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:08:32.469 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:08:32.469 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:32.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:08:32.470 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:08:32.470 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:08:32.470 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:08:32.470 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:32.472 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:08:32.472 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:08:32.472 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:08:32.472 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:32.472 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:08:32.472 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:08:32.472 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:08:32.472 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:08:32.472 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:32.475 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:08:32.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:08:32.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:08:32.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:08:32.475 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:08:32.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:08:32.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:08:32.476 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:08:32.476 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:08:32.476 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:32.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:32.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:32.481 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:08:32.964 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:08:33.005 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:08:33.007 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:08:33.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:33.010 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:08:33.030 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:33.030 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:33.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:33.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:33.034 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:33.034 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:33.034 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:33.034 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:33.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:33.069 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:33.069 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:33.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:33.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:33.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:33.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:33.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:33.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:33.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:33.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:33.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:33.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:33.262 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:33.262 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:33.262 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:33.262 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:33.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:33.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:33.301 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:33.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:33.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:33.434 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:08:33.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:33.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:33.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:33.483 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:33.912 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:08:34.390 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:08:34.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:34.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:34.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:34.484 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:34.868 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:08:35.342 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:08:35.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:35.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:35.387 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:35.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:35.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:35.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:35.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:35.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:35.405 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:35.405 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:35.405 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:35.405 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:35.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:35.439 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:35.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:35.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:35.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:35.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:35.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:35.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:35.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:35.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:35.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:35.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:35.605 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:35.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:35.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:35.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:35.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:35.624 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:35.624 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:35.624 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:35.624 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:35.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:35.675 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:35.676 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:35.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:35.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:35.820 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:08:36.298 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:08:36.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:36.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:36.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:36.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:36.776 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:08:37.253 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:08:37.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:37.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:37.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:37.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:37.730 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:08:37.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:37.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:37.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:37.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:37.843 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:37.843 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:37.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:37.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:37.845 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:37.845 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:37.845 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:37.845 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:37.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:37.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:37.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:37.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:37.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:38.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:38.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:38.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:38.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:38.164 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:38.164 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:38.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:38.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:38.165 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:38.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:38.165 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:38.165 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:38.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:38.208 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:08:38.210 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:38.210 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:38.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:38.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:38.686 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:08:39.164 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:08:39.642 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:08:40.120 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:08:40.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:40.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:40.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:40.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:40.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:40.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:40.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:40.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:40.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:40.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:40.521 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:40.521 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:40.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:40.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:40.543 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:40.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:40.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:40.597 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:08:40.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:40.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:40.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:40.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:40.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:40.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:40.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:40.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:40.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:40.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:40.849 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:40.849 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:40.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:40.887 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:40.888 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:40.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:40.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:41.075 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:08:41.553 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:08:42.031 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:08:42.510 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:08:42.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:42.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:42.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:42.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:42.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:42.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:42.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:42.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:42.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:42.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:42.958 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:42.958 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:42.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:42.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:42.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:42.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:42.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:42.987 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:08:43.464 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:08:43.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:43.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:43.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:43.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:43.639 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:43.639 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:43.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:43.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:43.640 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:43.640 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:43.640 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:43.640 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:43.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:43.648 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:43.648 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:43.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:43.648 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:43.942 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:08:44.419 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:08:44.896 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:08:45.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:45.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:45.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:45.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:45.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:45.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:45.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:45.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:45.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:45.357 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:45.357 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:45.357 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:45.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:45.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:45.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:45.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:45.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:45.374 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:08:45.851 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:08:46.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:46.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:46.012 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:46.012 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:46.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:46.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:46.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:46.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:46.033 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:46.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:46.033 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:46.033 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:46.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:46.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:46.097 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:46.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:46.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:46.328 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:08:46.806 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:08:47.284 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:08:47.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:47.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:47.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:47.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:47.750 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:47.750 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:47.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:47.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:47.752 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:47.752 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:47.752 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:47.752 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:47.761 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:08:47.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:47.818 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:47.818 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:47.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:47.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:48.239 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:08:48.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:48.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:48.328 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:48.328 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:48.348 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:48.348 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:48.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:48.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:48.350 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:48.350 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:48.350 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:48.350 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:48.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:48.387 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:48.388 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:48.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:48.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:48.717 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:08:49.195 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:08:49.673 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:08:50.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:50.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:50.070 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:50.070 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:50.089 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:50.089 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:50.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:50.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:50.091 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:50.091 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:50.091 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:50.091 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:50.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:50.151 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:08:50.154 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:50.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:50.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:50.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:50.629 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:08:50.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:50.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:50.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:50.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:50.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:50.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:50.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:50.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:50.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:50.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:50.736 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:50.736 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:50.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:50.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:50.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:50.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:50.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:51.107 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:08:51.584 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:08:52.061 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:08:52.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:52.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:52.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:52.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:52.467 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:52.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:52.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:52.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:52.470 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:08:52.470 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:08:52.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:08:52.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:08:52.470 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:08:52.470 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:08:52.470 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:08:52.470 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4272 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:52.470 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4272 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:52.470 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4272 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:57.471 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:08:57.471 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:08:57.472 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:08:57.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:08:57.474 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:08:57.474 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:08:57.483 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:08:57.484 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:08:57.484 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:57.484 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:08:57.484 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:08:57.486 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:08:57.486 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:08:57.487 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:08:57.487 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:57.487 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:08:57.487 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:08:57.487 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:08:57.487 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:08:57.487 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:57.489 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:08:57.489 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:08:57.489 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:08:57.489 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:57.489 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:08:57.489 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:08:57.489 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:08:57.489 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:08:57.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:57.490 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:08:57.490 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:08:57.491 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:08:57.491 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:08:57.491 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:08:57.491 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:08:57.491 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:08:57.491 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:08:57.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:08:57.493 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:08:57.493 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:08:57.493 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:57.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:57.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:08:57.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:08:57.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:57.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:57.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:57.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:08:57.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:57.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:57.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:08:57.498 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:08:57.981 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:08:58.019 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:08:58.022 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:08:58.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:58.024 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:08:58.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:58.052 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:58.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:58.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.057 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:58.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:58.058 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:58.059 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:58.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:58.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:58.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:58.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:58.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.159 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:58.160 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:58.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:58.178 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:58.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:58.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.179 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:58.179 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:58.179 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:58.179 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:58.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:58.224 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:58.224 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:58.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:58.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.279 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:58.279 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:58.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:58.297 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:58.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:58.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:58.298 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:58.298 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:58.298 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:58.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:58.307 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:58.307 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:58.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:58.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:58.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:58.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:58.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:58.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:58.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:58.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:58.402 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:58.402 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:58.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:58.454 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:08:58.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:58.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:58.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:58.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:58.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:58.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:58.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:58.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:58.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:58.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:58.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:58.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:58.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.558 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:58.558 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:58.558 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:58.558 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:58.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:58.600 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:58.600 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:58.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:58.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:58.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:58.869 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:58.869 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:58.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:58.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.871 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:58.871 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:58.871 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:58.871 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:58.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:58.931 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:08:58.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:58.933 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:58.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:58.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:59.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:59.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:59.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:59.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:59.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:59.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:59.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:59.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:59.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:59.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:59.105 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:59.105 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:59.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:59.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:59.115 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:59.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:59.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:59.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:59.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:59.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:59.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:59.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:59.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:59.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:08:59.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:59.278 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:59.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:59.279 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:08:59.279 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:08:59.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:59.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:08:59.313 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:08:59.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:59.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:59.409 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:08:59.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:08:59.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:08:59.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:59.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:59.496 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:08:59.496 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:08:59.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:59.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:59.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:08:59.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:08:59.506 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:08:59.506 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:08:59.509 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:08:59.509 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:08:59.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:08:59.509 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:08:59.509 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:08:59.509 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:08:59.509 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:08:59.509 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=431 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:59.509 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=431 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:59.509 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=431 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:59.509 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=431 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:59.509 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=431 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:59.509 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=431 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:08:59.509 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=431 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:04.509 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:04.509 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:04.510 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:04.511 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:04.511 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:04.512 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:04.518 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:04.520 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:04.520 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:04.520 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:04.520 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:09:04.523 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:09:04.523 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:09:04.524 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:04.524 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:04.524 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:04.524 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:09:04.525 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:04.525 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:09:04.525 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:04.525 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:09:04.525 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:09:04.526 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:04.526 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:04.526 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:04.526 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:09:04.526 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:04.526 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:09:04.526 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:04.528 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:09:04.528 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:09:04.528 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:04.528 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:04.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:04.528 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:09:04.528 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:04.528 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:09:04.528 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:04.530 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:09:04.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:09:04.531 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:09:04.531 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:09:04.531 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:04.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:04.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:04.536 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:09:05.017 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:09:05.062 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:09:05.065 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:09:05.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:05.067 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:09:05.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:05.089 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:05.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:05.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:05.094 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:05.094 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:05.094 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:05.094 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:05.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:05.120 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:05.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:05.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:05.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:05.495 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:09:05.534 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:05.535 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:05.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:05.537 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:05.972 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:09:05.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:05.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:05.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:05.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:06.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:06.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:06.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:06.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:06.013 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:06.013 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:06.013 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:06.013 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:06.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:06.017 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:06.017 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:06.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:06.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:06.450 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:09:06.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:06.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:06.482 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:06.482 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:06.499 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:06.499 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:06.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:06.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:06.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:06.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:06.501 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:06.501 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:06.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:06.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:06.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:06.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:06.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:06.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:06.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:06.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:06.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:06.927 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:09:07.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:07.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:07.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:07.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:07.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:07.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:07.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:07.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:07.227 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:07.227 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:07.227 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:07.227 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:07.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:07.266 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:07.266 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:07.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:07.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:07.405 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:09:07.537 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:07.537 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:07.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:07.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:07.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:07.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:07.696 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:07.696 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:07.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:07.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:07.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:07.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:07.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:07.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:07.719 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:07.719 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:07.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:07.732 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:07.732 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:07.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:07.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:07.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:07.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:07.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:07.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:07.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:07.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:07.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:07.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:07.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:07.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:07.862 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:07.862 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:07.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:07.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:07.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:07.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:07.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:07.881 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:09:08.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:08.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:08.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:08.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:08.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:08.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:08.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:08.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:08.344 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:08.344 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:08.344 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:08.344 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:08.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:08.351 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:08.351 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:08.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:08.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:08.358 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:09:08.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:08.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:08.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:08.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:08.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:08.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:08.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:08.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:08.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:08.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:08.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:08.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:08.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:08.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:08.774 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:08.774 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:08.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:08.834 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:08.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:08.835 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:09:08.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:08.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:09.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:09.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:09.231 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:09.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:09.240 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:09.240 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:09.240 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:09.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:09.241 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:09.241 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:09.241 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:09.241 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:09.241 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:09.241 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:09.241 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:09:09.241 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1008 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:09.241 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1008 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:09.241 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1008 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:09.241 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1008 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:09.241 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1008 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:09.241 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1008 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:09.241 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1008 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:14.244 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:14.244 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:14.245 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:14.248 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:14.248 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:14.248 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:14.257 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:14.258 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:14.258 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:14.258 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:14.258 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:09:14.259 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:09:14.259 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:09:14.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:14.259 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:14.260 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:14.260 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:09:14.260 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:14.260 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:09:14.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:14.261 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:09:14.261 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:09:14.261 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:14.261 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:14.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:14.261 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:09:14.262 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:14.262 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:09:14.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:14.263 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:09:14.263 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:09:14.263 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:14.263 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:14.263 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:14.263 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:09:14.264 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:14.264 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:09:14.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:14.266 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:09:14.266 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:09:14.266 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:14.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:14.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:14.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:14.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:14.271 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:09:14.754 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:09:14.789 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:09:14.791 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:09:14.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:14.793 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:09:14.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:14.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:14.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:14.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:14.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:14.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:14.815 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:14.815 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:14.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:14.859 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:14.859 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:14.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:14.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:14.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:14.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:14.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:14.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:14.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:14.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:14.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:14.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:14.939 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:14.939 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:14.939 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:14.939 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:14.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:15.001 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:15.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:15.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:15.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:15.056 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:15.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:15.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:15.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:15.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.075 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:15.076 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:15.076 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:15.076 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:15.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:15.081 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:15.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:15.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:15.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:15.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:15.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:15.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:15.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:15.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.180 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:15.180 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:15.180 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:15.180 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:15.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:15.228 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:09:15.229 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:15.229 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:15.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:15.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:15.270 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:15.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:15.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:15.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:15.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:15.313 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:15.313 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:15.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:15.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.315 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:15.315 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:15.315 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:15.315 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:15.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:15.375 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:15.375 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:15.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:15.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:15.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:15.474 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:15.474 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:15.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:15.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:15.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:15.476 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:15.476 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:15.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:15.515 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:15.515 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:15.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:15.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:15.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:15.704 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:09:15.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:15.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:15.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:15.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:15.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:15.712 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:15.712 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:15.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:15.762 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:15.762 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:15.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:15.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.863 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:15.863 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:15.883 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:15.883 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:15.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:15.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.885 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:15.885 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:15.885 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:15.885 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:15.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:15.949 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:15.949 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:15.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:15.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:16.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:16.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:16.098 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:16.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:16.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:16.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:16.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:16.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:16.111 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:16.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:16.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:16.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:16.112 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:16.112 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:16.112 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:09:16.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:16.113 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:16.113 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:16.113 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:16.113 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:16.113 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:16.113 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:16.113 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:16.113 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:16.113 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:16.113 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:16.114 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:16.114 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:16.114 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=396 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:21.114 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:21.114 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:21.114 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:21.114 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:21.114 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:21.114 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:21.121 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:21.122 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:21.122 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:21.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:21.123 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:09:21.124 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:09:21.125 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:09:21.125 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:21.125 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:21.125 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:21.125 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:09:21.125 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:21.125 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:09:21.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:21.127 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:09:21.128 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:09:21.128 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:21.128 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:21.128 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:21.128 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:09:21.128 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:21.128 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:09:21.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:21.129 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:09:21.129 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:09:21.129 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:21.129 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:21.130 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:21.130 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:09:21.130 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:21.130 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:09:21.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:21.132 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:09:21.132 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:09:21.132 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:21.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:21.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:21.137 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:09:21.620 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:09:21.657 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:09:21.658 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:09:21.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:21.659 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:09:21.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:21.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:21.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:21.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:21.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:21.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:21.670 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:21.670 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:21.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:21.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:21.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:21.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:21.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:22.098 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:09:22.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:22.136 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:22.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:22.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:22.576 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:09:22.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:22.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:22.600 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:22.600 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:22.619 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:22.619 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:22.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:22.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:22.620 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:22.620 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:22.620 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:22.621 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:22.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:22.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:22.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:22.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:22.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:23.053 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:09:23.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:23.137 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:23.137 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:23.140 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:23.531 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:09:23.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:23.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:23.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:23.574 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:23.574 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=521 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:23.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:23.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:23.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:23.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:23.595 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:23.595 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:23.595 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:23.595 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:23.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:23.635 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:23.635 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:23.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:23.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:24.008 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:09:24.137 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:24.138 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:24.138 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:24.141 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:24.486 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:09:24.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:24.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:24.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:24.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:24.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:24.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:24.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:24.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:24.809 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:24.809 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:24.809 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:24.809 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:24.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:24.812 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:24.812 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:24.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:24.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:24.961 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:09:25.138 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:25.139 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:25.139 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:25.142 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:25.439 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:09:25.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:25.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:25.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:25.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:25.780 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:25.780 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:25.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:25.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:25.782 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:25.782 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:25.782 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:25.782 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:25.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:25.827 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:25.827 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:25.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:25.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:25.917 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:09:26.139 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:26.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:26.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:26.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:26.394 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:09:26.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:26.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:26.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:26.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:26.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:26.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:26.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:26.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:26.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:26.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:26.459 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:26.459 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:26.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:26.496 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:26.497 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:26.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:26.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:26.872 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:09:27.350 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:09:27.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:27.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:27.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:27.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:27.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:27.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:27.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:27.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:27.414 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:27.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:27.414 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:27.414 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:27.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:27.449 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:27.449 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:27.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:27.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:27.829 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:09:28.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:28.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:28.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:28.297 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:28.306 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:09:28.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:28.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:28.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:28.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:28.309 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:28.309 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:28.309 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:28.309 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:28.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:28.363 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:28.363 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:28.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:28.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:28.783 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:09:29.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:29.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:29.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:29.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:29.261 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:09:29.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:29.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:29.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:29.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:29.265 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:29.266 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:29.266 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:29.266 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:29.266 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:29.266 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:29.266 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:09:29.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1737 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.268 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.268 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.268 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:29.268 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1738 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:34.265 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:34.265 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:34.266 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:34.267 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:34.268 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:34.268 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:34.279 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:34.280 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:34.281 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:34.281 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:34.281 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:09:34.286 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:09:34.286 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:09:34.286 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:34.287 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:34.287 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:34.288 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:09:34.288 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:34.288 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:09:34.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:34.289 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:09:34.290 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:09:34.290 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:34.290 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:34.290 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:34.290 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:09:34.290 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:34.290 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:09:34.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:34.292 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:09:34.293 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:09:34.293 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:34.293 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:34.293 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:34.293 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:09:34.293 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:34.293 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:09:34.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:34.297 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:09:34.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:09:34.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:09:34.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:09:34.297 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:09:34.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:09:34.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:09:34.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:09:34.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:09:34.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:09:34.298 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:09:34.298 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:34.298 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:34.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:34.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:34.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:34.303 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:09:34.786 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:09:34.825 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:09:34.827 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:09:34.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:34.829 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:09:34.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:34.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:34.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:34.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:34.852 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:34.852 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:34.853 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:34.853 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:34.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:34.891 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:34.891 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:34.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:34.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:35.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:35.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:35.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:35.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:35.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:35.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:35.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:35.029 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:35.029 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:35.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:35.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:35.080 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:35.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:35.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:35.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:35.263 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:09:35.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:35.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:35.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:35.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.269 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:35.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:35.269 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:35.269 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:35.303 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:35.303 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:35.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:35.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:35.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:35.320 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:35.320 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:35.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:35.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:35.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:35.511 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:35.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:35.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:35.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.512 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:35.512 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:35.512 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:35.512 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:35.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:35.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:35.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:35.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.736 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:09:35.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:35.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:35.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:35.884 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:35.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:35.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:35.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:35.886 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:35.888 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:35.888 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:35.888 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:35.888 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:35.888 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:35.888 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:35.888 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:09:35.888 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=341 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:35.889 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=341 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:35.889 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=341 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:35.889 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=341 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:35.889 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=341 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:35.889 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=341 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:35.889 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=341 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:40.890 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:40.890 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:40.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:40.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:40.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:40.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:40.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:40.900 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:40.900 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:40.901 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:40.901 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:09:40.903 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:09:40.904 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:09:40.904 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:40.905 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:40.905 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:40.905 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:09:40.906 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:40.906 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:09:40.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:40.906 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:09:40.907 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:09:40.907 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:40.907 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:40.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:40.908 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:09:40.908 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:40.908 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:09:40.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:40.909 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:09:40.909 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:09:40.909 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:40.909 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:40.909 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:40.909 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:09:40.910 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:40.910 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:09:40.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:40.912 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:09:40.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:09:40.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:09:40.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:09:40.912 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:09:40.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:09:40.913 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:09:40.913 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:40.913 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:40.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:40.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:40.918 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:09:41.402 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:09:41.436 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:09:41.438 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:09:41.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:41.440 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:09:41.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:41.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:41.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:41.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:41.461 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:41.461 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:41.461 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:41.461 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:41.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:41.508 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:41.508 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:41.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:41.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:41.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:41.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:41.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:41.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:41.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:41.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:41.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:41.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:41.645 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:41.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:41.645 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:41.645 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:41.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:41.690 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:41.690 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:41.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:41.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:41.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:41.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:41.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:41.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:41.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:41.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:41.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:41.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:41.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:41.842 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:41.842 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:41.842 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:41.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:41.879 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:09:41.886 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:41.886 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:41.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:41.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:41.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:41.917 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:41.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:41.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:42.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:42.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:42.110 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:42.110 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:42.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:42.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:42.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:42.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:42.131 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:42.131 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:42.131 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:42.131 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:42.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:42.167 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:42.167 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:42.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:42.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:42.357 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:09:42.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:42.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:42.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:42.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:42.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:42.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:42.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:42.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:42.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:42.521 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:42.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:42.521 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:42.521 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:42.521 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:42.521 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:09:47.523 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:47.524 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:47.525 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:47.526 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:47.526 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:47.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:47.536 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:47.537 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:47.537 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:47.538 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:47.538 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:09:47.542 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:09:47.542 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:09:47.542 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:47.542 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:47.542 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:47.542 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:09:47.542 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:47.542 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:09:47.543 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:47.545 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:09:47.545 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:09:47.545 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:47.545 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:47.545 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:47.545 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:09:47.545 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:47.545 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:09:47.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:47.547 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:09:47.547 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:09:47.547 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:47.548 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:47.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:47.548 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:09:47.548 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:47.548 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:09:47.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:47.550 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:09:47.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:09:47.551 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:09:47.551 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:09:47.551 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:09:47.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:47.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:47.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:47.556 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:09:48.038 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:09:48.075 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:09:48.077 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:09:48.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:48.078 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:09:48.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:48.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:48.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:48.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:48.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:48.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:48.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:48.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:48.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:48.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:48.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:48.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:48.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:48.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:48.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:48.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:48.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.281 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:48.281 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:48.281 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:48.281 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:48.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:48.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:48.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:48.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:48.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:48.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:48.515 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:09:48.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:48.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:48.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:48.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:48.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:48.521 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:48.521 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:48.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:48.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:48.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:48.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:48.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:48.571 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:48.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:48.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:48.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:48.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:48.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:48.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:48.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:48.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.759 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:48.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:48.759 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:48.759 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:48.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:48.806 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:48.806 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:48.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:48.992 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:09:49.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:49.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:49.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:49.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:49.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:49.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:49.158 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:49.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:49.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:49.161 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:49.161 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:49.161 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:49.161 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:49.161 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:49.161 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:09:49.161 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=344 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:49.161 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=344 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:49.161 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=344 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:49.161 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=344 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:49.161 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=344 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:49.162 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=344 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:49.162 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=344 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:54.161 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:54.162 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:54.163 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:54.165 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:54.165 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:54.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:54.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:54.173 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:54.173 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:54.173 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:09:54.173 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:09:54.175 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:09:54.175 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:09:54.175 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:54.176 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:54.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:54.176 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:09:54.176 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:09:54.177 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:09:54.177 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:54.177 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:09:54.177 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:09:54.177 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:54.178 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:54.178 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:54.178 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:09:54.178 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:09:54.178 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:09:54.178 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:54.180 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:09:54.180 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:09:54.180 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:54.180 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:09:54.180 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:54.180 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:09:54.180 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:09:54.180 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:09:54.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:54.182 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:09:54.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:09:54.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:09:54.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:09:54.182 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:09:54.183 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:09:54.183 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:54.183 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:54.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:54.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:09:54.188 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:09:54.672 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:09:54.717 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:09:54.719 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:09:54.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:54.721 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:09:54.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:54.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:54.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:54.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:54.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:54.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:54.750 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:54.750 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:54.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:54.771 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:54.772 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:54.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:54.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:54.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:54.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:54.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:54.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:54.894 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:54.894 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:54.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:54.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:54.895 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:54.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:54.895 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:54.895 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:54.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:54.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:54.907 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:54.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:54.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:55.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:55.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:55.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:55.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:55.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:55.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:55.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:55.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:55.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:55.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:55.077 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:55.077 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:55.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:55.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:55.095 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:55.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:55.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:55.148 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:09:55.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:55.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:55.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:55.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:55.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:55.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:55.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:55.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:55.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:55.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:55.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:09:55.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:55.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:55.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:55.397 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:09:55.397 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:09:55.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:55.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:09:55.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:09:55.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:55.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:55.626 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:09:55.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:09:55.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:09:55.783 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:09:55.783 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:09:55.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:09:55.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:09:55.790 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:09:55.790 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:09:55.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:09:55.790 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:09:55.790 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:09:55.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:09:55.790 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:09:55.790 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:09:55.791 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:09:55.791 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=343 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:09:55.791 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=343 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:00.793 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:00.794 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:00.795 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:00.796 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:00.797 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:00.797 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:00.804 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:00.805 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:00.805 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:00.806 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:00.806 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:10:00.807 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:10:00.808 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:10:00.808 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:00.808 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:00.809 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:00.809 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:10:00.809 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:00.809 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:10:00.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:00.810 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:10:00.810 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:10:00.810 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:00.810 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:00.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:00.810 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:10:00.810 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:00.810 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:10:00.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:00.812 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:10:00.812 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:10:00.812 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:00.812 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:00.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:00.812 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:10:00.812 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:00.812 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:10:00.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:00.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:10:00.816 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:10:00.816 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:10:00.816 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:00.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:00.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:00.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:00.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:00.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:00.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:00.820 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:10:01.305 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:10:01.343 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:10:01.345 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:10:01.347 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:10:01.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:01.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:01.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:01.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:01.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:01.381 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:01.381 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:01.381 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:01.381 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:01.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:01.408 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:01.408 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:01.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:01.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:01.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:01.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:01.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:01.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:01.741 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:01.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:01.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:01.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:01.743 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:01.743 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:01.743 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:01.743 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:01.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:01.781 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:10:01.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:01.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:01.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:01.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:01.818 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:01.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:01.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:01.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:02.260 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:10:02.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:02.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:02.278 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:02.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:02.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:02.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:02.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:02.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:02.293 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:02.293 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:02.293 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:02.293 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:02.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:02.307 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:02.307 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:02.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:02.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:02.737 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:10:02.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:02.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:02.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:02.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:03.215 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:10:03.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:03.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:03.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:03.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:03.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:03.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:03.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:03.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:03.397 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:03.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:03.397 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:03.397 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:03.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:03.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:03.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:03.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:03.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:03.692 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:10:03.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:03.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:03.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:03.824 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:04.170 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:10:04.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:04.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:04.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:04.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:04.499 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:04.499 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:04.499 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:04.499 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:04.500 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:04.500 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:04.500 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:04.500 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:04.500 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:04.500 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:04.500 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:10:04.500 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:04.500 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:04.500 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:09.503 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:09.503 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:09.504 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:09.506 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:09.507 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:09.507 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:09.513 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:09.514 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:09.514 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:09.515 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:09.515 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:10:09.517 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:10:09.517 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:10:09.518 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:09.518 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:09.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:09.518 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:10:09.518 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:09.518 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:10:09.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:09.520 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:10:09.520 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:10:09.521 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:09.521 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:09.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:09.521 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:10:09.521 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:09.521 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:10:09.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:09.523 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:10:09.523 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:10:09.523 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:09.523 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:09.523 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:09.523 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:10:09.523 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:09.523 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:10:09.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:09.526 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:10:09.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:10:09.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:10:09.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:10:09.526 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:10:09.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:10:09.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:10:09.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:10:09.527 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:10:09.527 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:10:09.527 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:09.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:09.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:09.532 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:10:10.013 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:10:10.053 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:10:10.053 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:10:10.055 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:10:10.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:10.077 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:10.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:10.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:10.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:10.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:10.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:10.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:10.082 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:10.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:10.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:10.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:10.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:10.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:10.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:10.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:10.432 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:10.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:10.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:10.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:10.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:10.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:10.453 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:10.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:10.453 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:10.453 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:10.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:10.490 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:10:10.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:10.495 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:10.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:10.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:10.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:10.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:10.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:10.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:10.968 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:10:10.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:10.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:10.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:10.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:10.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:10.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:10.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:10.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:10.996 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:10.996 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:10.996 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:10.996 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:11.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:11.018 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:11.018 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:11.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:11.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:11.445 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:10:11.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:11.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:11.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:11.537 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:11.924 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:10:12.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:12.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:12.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:12.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:12.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:12.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:12.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:12.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:12.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:12.101 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:12.101 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:12.101 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:12.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:12.107 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:12.107 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:12.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:12.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:12.400 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:10:12.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:12.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:12.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:12.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:12.878 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:10:13.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:13.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:13.200 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:13.200 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:13.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:13.204 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:13.204 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:13.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:13.205 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:13.205 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:13.205 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:13.205 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:13.205 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:13.205 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:13.205 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:10:18.208 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:18.208 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:18.210 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:18.211 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:18.212 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:18.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:18.220 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:18.222 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:18.222 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:18.222 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:18.222 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:10:18.225 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:10:18.225 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:10:18.225 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:18.225 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:18.226 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:18.226 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:10:18.226 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:18.226 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:10:18.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:18.227 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:10:18.227 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:10:18.227 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:18.227 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:18.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:18.227 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:10:18.227 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:18.227 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:10:18.227 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:18.229 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:10:18.229 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:10:18.229 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:18.229 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:18.229 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:18.229 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:10:18.229 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:18.229 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:10:18.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:18.231 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:10:18.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:10:18.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:10:18.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:10:18.231 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:10:18.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:10:18.232 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:10:18.232 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:10:18.232 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:18.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:18.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:18.237 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:10:18.720 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:10:18.758 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:10:18.758 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:10:18.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:18.761 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:10:18.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:18.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:18.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:18.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:18.795 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:18.795 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:18.796 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:18.796 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:18.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:18.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:18.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:18.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:18.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:19.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:19.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:19.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:19.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:19.158 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:19.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:19.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:19.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:19.160 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:19.160 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:19.160 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:19.160 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:19.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:19.197 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:10:19.202 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:19.202 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:19.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:19.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:19.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:19.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:19.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:19.239 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:19.675 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:10:19.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:19.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:19.693 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:19.693 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:19.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:19.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:19.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:19.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:19.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:19.709 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:19.709 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:19.709 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:19.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:19.722 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:19.722 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:19.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:19.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:20.152 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:10:20.236 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:20.236 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:20.236 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:20.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:20.631 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:10:20.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:20.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:20.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:20.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:20.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:20.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:20.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:20.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:20.813 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:20.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:20.813 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:20.813 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:20.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:20.878 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:20.878 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:20.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:20.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:21.108 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:10:21.236 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:21.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:21.237 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:21.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:21.586 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:10:21.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:21.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:21.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:21.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:21.917 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:21.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:21.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:21.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:21.921 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:21.921 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:21.921 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:21.921 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:21.922 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:21.922 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:21.922 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:10:21.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:21.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:21.923 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=788 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:21.923 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=788 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:21.923 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:21.923 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:21.923 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:21.923 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:21.923 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:21.923 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:26.921 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:26.921 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:26.923 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:26.924 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:26.926 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:26.928 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:26.936 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:26.937 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:26.937 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:26.938 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:26.938 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:10:26.941 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:10:26.941 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:10:26.941 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:26.942 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:26.942 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:26.942 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:10:26.943 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:26.943 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:10:26.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:26.943 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:10:26.943 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:10:26.943 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:26.943 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:26.944 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:26.944 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:10:26.944 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:26.944 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:10:26.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:26.945 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:10:26.945 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:10:26.945 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:26.945 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:26.946 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:26.946 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:10:26.946 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:26.946 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:10:26.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:26.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:10:26.949 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:10:26.949 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:10:26.949 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:26.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:26.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:26.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:26.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:26.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:26.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:26.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:26.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:26.953 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:10:27.436 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:10:27.479 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:10:27.481 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:10:27.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:27.483 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:10:27.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:27.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:27.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:27.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:27.513 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:27.513 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:27.513 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:27.513 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:27.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:27.534 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:27.534 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:27.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:27.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:27.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:27.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:27.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:27.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:27.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:27.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:27.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:27.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:27.877 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:27.877 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:27.877 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:27.877 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:27.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:27.912 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:10:27.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:27.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:27.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:27.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:27.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:27.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:27.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:27.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:28.390 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:10:28.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:28.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:28.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:28.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:28.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:28.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:28.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:28.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:28.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:28.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:28.418 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:28.418 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:28.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:28.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:28.441 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:28.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:28.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:28.868 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:10:28.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:28.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:28.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:28.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:29.346 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:10:29.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:29.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:29.506 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:29.506 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:29.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:29.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:29.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:29.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:29.528 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:29.528 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:29.528 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:29.528 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:29.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:29.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:29.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:29.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:29.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:29.823 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:10:29.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:29.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:29.955 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:29.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:30.301 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:10:30.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:30.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:30.623 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:30.623 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:30.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:30.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:30.630 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:30.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:30.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:30.631 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:30.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:30.631 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:30.631 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:30.631 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:10:30.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:30.631 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=787 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:30.631 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=787 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:30.631 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=787 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:30.631 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=787 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:30.631 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=787 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:30.631 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=787 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:30.631 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=787 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:35.634 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:35.634 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:35.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:35.636 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:35.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:35.636 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:35.646 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:35.648 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:35.649 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:35.649 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:35.649 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:10:35.654 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:10:35.654 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:10:35.655 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:35.655 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:35.655 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:35.656 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:10:35.656 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:35.657 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:10:35.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:35.658 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:10:35.658 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:10:35.658 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:35.658 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:35.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:35.659 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:10:35.659 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:35.659 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:10:35.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:35.661 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:10:35.661 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:10:35.661 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:35.661 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:35.661 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:35.661 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:10:35.661 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:35.661 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:10:35.662 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:35.664 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:35.665 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:10:35.665 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:10:35.665 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:10:35.666 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:35.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:35.667 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:35.667 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:35.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:35.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:35.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:35.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:35.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:35.670 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:10:36.154 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:10:36.196 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:10:36.198 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:10:36.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:36.200 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:10:36.218 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:36.218 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:36.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:36.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:36.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:36.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:36.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:36.232 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:36.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:36.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:36.233 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:36.233 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:36.233 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:36.233 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:10:36.233 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:36.234 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:41.233 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:41.233 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:41.234 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:41.236 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:41.237 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:41.237 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:41.246 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:41.247 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:41.247 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:41.247 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:41.248 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:10:41.251 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:10:41.251 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:10:41.252 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:41.252 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:41.252 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:41.253 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:10:41.253 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:41.253 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:10:41.254 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:41.254 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:10:41.254 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:10:41.254 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:41.254 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:41.254 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:41.254 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:10:41.255 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:41.255 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:10:41.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:41.256 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:10:41.256 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:10:41.257 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:41.257 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:41.257 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:41.257 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:10:41.257 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:41.257 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:10:41.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:41.260 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:10:41.260 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:10:41.260 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:10:41.261 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:41.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:41.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:41.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:41.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:41.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:41.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:41.265 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:10:41.749 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:10:41.791 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:10:41.793 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:10:41.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:41.795 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:10:41.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:41.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:41.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:41.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:41.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:41.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:41.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:41.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:41.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:41.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:41.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:41.863 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:41.864 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:41.864 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:41.864 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:41.864 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:41.864 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:41.864 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:10:46.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:46.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:46.868 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:46.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:46.871 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:46.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:46.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:46.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:46.883 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:46.883 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:46.883 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:10:46.886 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:10:46.887 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:10:46.887 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:46.887 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:46.888 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:46.888 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:10:46.889 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:46.889 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:10:46.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:46.890 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:10:46.890 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:10:46.890 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:46.890 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:46.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:46.890 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:10:46.890 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:46.890 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:10:46.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:46.892 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:10:46.892 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:10:46.892 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:46.892 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:46.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:46.893 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:10:46.893 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:46.893 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:10:46.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:46.895 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:10:46.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:10:46.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:10:46.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:10:46.896 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:10:46.896 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:10:46.896 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:46.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:46.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:46.901 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:10:47.384 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:10:47.423 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:10:47.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:47.426 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:10:47.428 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:10:47.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:47.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:47.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:47.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:47.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:47.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:47.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:47.470 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:47.470 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:47.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:47.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:47.470 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:47.470 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:47.471 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:10:47.471 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:47.471 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:47.471 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:47.471 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:47.471 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:47.471 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:10:52.470 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:52.470 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:52.474 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:52.474 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:52.474 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:52.474 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:52.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:52.483 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:52.483 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:52.484 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:52.484 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:10:52.486 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:10:52.487 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:10:52.487 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:52.487 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:52.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:52.488 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:10:52.489 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:52.489 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:10:52.489 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:52.490 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:10:52.490 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:10:52.490 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:52.490 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:52.490 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:52.491 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:10:52.491 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:52.491 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:10:52.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:52.492 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:10:52.492 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:10:52.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:52.493 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:52.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:52.493 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:10:52.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:52.493 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:10:52.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:52.496 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:10:52.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:10:52.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:10:52.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:10:52.496 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:10:52.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:10:52.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:10:52.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:10:52.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:10:52.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:10:52.497 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:10:52.497 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:10:52.497 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:52.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:52.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:52.499 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:52.499 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:52.499 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:10:57.503 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:10:57.503 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:10:57.504 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:57.505 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:57.506 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:57.506 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:57.515 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:10:57.517 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:57.517 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:57.517 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:10:57.517 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:10:57.520 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:10:57.521 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:10:57.521 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:57.521 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:57.521 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:10:57.522 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:10:57.522 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:10:57.522 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:10:57.523 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:57.523 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:10:57.524 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:10:57.524 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:57.524 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:57.524 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:10:57.524 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:10:57.524 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:10:57.524 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:10:57.524 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:57.527 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:10:57.527 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:10:57.527 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:57.527 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:10:57.527 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:10:57.527 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:10:57.527 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:10:57.527 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:10:57.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:57.533 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:10:57.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:10:57.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:10:57.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:10:57.533 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:10:57.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:10:57.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:10:57.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:10:57.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:10:57.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:10:57.534 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:10:57.534 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:10:57.534 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:57.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:10:57.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:10:57.539 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:10:58.023 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:10:58.065 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:10:58.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:58.068 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:10:58.071 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:10:58.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:58.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:58.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:58.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:58.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:58.101 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:58.101 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:58.101 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:58.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:58.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:58.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:58.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:58.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:58.500 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:10:58.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:58.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:58.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:58.543 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:58.978 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:10:59.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:59.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:59.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:59.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:59.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:10:59.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:10:59.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:10:59.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:59.109 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:59.109 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:59.109 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:10:59.109 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:10:59.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:10:59.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:10:59.115 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:10:59.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:59.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:10:59.456 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:10:59.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:10:59.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:10:59.543 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:10:59.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:10:59.933 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:11:00.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:00.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:00.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:00.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:00.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:00.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:00.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:00.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:00.081 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:00.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:00.081 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:00.081 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:00.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:00.129 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:00.129 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:00.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:00.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:00.411 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:11:00.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:11:00.541 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:11:00.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:11:00.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:11:00.889 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:11:01.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:01.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:01.048 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:01.048 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:01.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:01.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:01.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:01.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:01.063 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:01.063 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:01.063 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:01.063 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:01.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:01.073 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:01.073 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:01.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:01.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:01.365 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:11:01.541 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:11:01.541 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:11:01.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:11:01.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:11:01.843 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:11:02.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:02.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:02.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:02.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:02.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:02.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:02.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:02.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:02.036 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:02.036 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:02.036 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:02.036 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:02.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:02.090 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:02.090 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:02.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:02.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:02.320 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:11:02.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:11:02.543 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:11:02.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:11:02.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:11:02.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:02.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:02.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:02.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:02.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:02.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:02.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:02.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:02.660 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:02.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:02.661 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:02.661 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:02.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:02.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:02.704 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:02.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:02.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:02.798 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:11:03.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:03.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:03.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:03.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:03.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:03.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:03.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:03.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:03.270 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:03.270 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:03.270 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:03.270 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:03.276 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:11:03.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:03.334 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:03.334 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:03.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:03.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:03.754 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:11:03.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:03.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:03.886 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:03.886 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:03.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:03.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:03.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:03.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:03.900 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:03.900 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:03.900 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:03.900 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:03.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:03.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:03.950 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:03.951 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:03.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:03.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:04.232 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:11:04.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:04.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:04.549 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:04.549 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:04.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:04.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:04.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:04.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:04.569 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:04.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:04.569 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:04.569 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:04.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:04.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:04.615 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:04.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:04.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:04.709 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:11:05.187 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:11:05.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:05.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:05.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:05.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:05.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:05.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:05.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:05.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:05.215 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:05.215 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:05.215 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:05.215 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:05.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:05.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:05.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:05.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:05.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:05.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:05.665 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:11:05.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:05.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:05.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:05.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:05.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:05.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:05.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:05.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:05.813 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:05.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:05.813 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:05.813 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:05.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:05.858 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:05.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:05.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:05.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:06.140 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:11:06.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:06.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:06.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:06.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:06.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:06.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:06.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:06.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:06.474 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:06.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:06.474 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:06.474 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:06.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:06.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:06.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:06.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:06.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:06.618 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:11:07.097 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:11:07.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:07.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:07.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:07.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:07.169 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:07.169 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:07.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:07.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:07.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:07.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:07.171 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:07.171 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:07.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:07.193 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:07.193 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:07.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:07.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:07.574 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:11:08.051 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:11:08.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:08.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:08.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:08.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:08.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:08.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:08.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:08.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:08.067 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:08.067 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:08.067 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:08.067 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:08.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:08.107 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:08.108 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:08.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:08.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:08.528 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:11:09.006 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:11:09.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:09.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:09.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:09.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:09.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:09.046 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:09.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:09.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:09.047 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:09.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:09.047 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:09.047 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:09.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:09.050 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:09.050 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:09.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:09.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:09.484 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:11:09.962 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:11:10.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:10.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:10.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:10.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:10.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:10.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:10.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:10.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:10.026 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:10.026 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:10.026 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:10.026 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:10.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:10.064 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:10.064 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:10.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:10.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:10.439 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:11:10.917 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:11:10.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:10.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:10.984 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:10.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:10.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:10.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:10.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:10.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:10.994 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:10.994 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:10.994 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:10.994 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:11.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:11.011 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:11.011 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:11.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:11.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:11.394 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:11:11.872 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:11:11.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:11.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:11.958 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:11.958 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:11.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:11.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:11.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:11.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:11.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:11.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:11.974 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:11.974 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:12.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:12.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:12.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:12.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:12.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:12.350 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:11:12.827 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:11:12.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:12.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:12.932 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:12.932 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:12.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:12.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:12.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:12.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:12.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:12.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:12.942 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:12.942 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:12.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:12.971 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:12.972 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:12.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:12.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:13.304 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:11:13.782 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:11:13.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:13.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:13.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:13.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:13.918 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:13.918 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:13.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:13.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:13.920 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:13.920 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:13.920 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:13.920 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:13.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:13.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:13.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:13.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:13.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:14.260 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:11:14.737 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:11:14.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:14.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:14.892 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:14.892 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:14.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:11:14.901 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:11:14.901 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:11:14.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:11:14.903 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:11:14.903 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:11:14.903 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:11:14.903 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:11:14.903 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:11:14.903 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:11:14.903 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:11:14.903 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3710 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:14.904 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3710 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:14.904 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3710 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:14.904 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3710 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:14.904 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3710 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:14.904 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3710 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:14.904 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3710 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:14.904 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3710 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:19.905 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:11:19.906 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:11:19.906 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:11:19.906 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:11:19.906 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:11:19.906 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:11:19.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:11:19.912 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:11:19.912 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:11:19.913 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:11:19.913 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:11:19.913 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:11:19.913 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:11:19.913 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:11:19.913 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:11:19.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:11:19.914 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:11:19.914 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:11:19.914 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:11:19.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:11:19.914 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:11:19.914 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:11:19.914 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:11:19.914 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:11:19.914 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:11:19.914 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:11:19.914 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:11:19.914 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:11:19.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:11:19.915 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:11:19.915 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:11:19.915 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:11:19.915 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:11:19.915 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:11:19.915 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:11:19.915 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:11:19.915 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:11:19.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:11:19.917 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:19.918 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:11:19.918 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:11:19.918 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:11:19.918 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:19.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:19.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:19.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:19.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:19.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:19.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:19.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:19.923 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:11:20.407 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:11:20.447 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:11:20.449 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:11:20.450 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:11:20.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:20.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:20.473 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:20.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:20.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:20.478 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:20.479 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:20.480 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:20.480 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:20.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:20.512 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:20.512 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:20.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:20.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:20.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:20.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:20.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:20.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:20.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:20.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:20.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:20.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:20.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:20.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:20.767 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:20.767 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:20.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:20.783 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:20.783 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:20.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:20.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:20.885 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:11:20.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:11:20.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:11:20.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:11:20.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:11:21.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:21.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:21.016 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:21.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:21.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:21.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:21.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:21.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:21.026 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:21.026 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:21.026 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:21.026 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:21.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:21.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:21.080 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:21.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:21.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:21.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:21.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:21.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:21.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:21.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:21.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:21.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:11:21.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:21.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:21.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:21.297 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:11:21.297 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:11:21.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:21.303 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:11:21.303 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:11:21.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:21.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:21.361 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:11:21.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:11:21.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:11:21.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:11:21.540 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:11:21.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:11:21.549 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:11:21.549 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:11:21.549 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:11:21.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:11:21.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:11:21.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:11:21.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:11:21.550 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:11:21.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:11:21.551 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:11:21.551 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=348 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:21.551 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=348 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:21.551 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=348 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:21.551 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=349 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:21.551 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=349 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:21.551 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=349 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:21.552 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=349 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:21.552 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=349 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:21.552 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=349 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:21.552 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=349 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:21.552 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=349 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:26.550 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:11:26.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:11:26.551 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:11:26.553 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:11:26.554 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:11:26.554 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:11:26.559 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:11:26.560 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:11:26.561 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:11:26.561 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:11:26.561 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:11:26.564 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:11:26.564 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:11:26.564 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:11:26.565 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:11:26.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:11:26.565 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:11:26.566 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:11:26.566 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:11:26.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:11:26.566 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:11:26.566 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:11:26.567 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:11:26.567 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:11:26.567 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:11:26.567 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:11:26.567 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:11:26.567 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:11:26.567 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:11:26.569 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:11:26.569 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:11:26.569 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:11:26.569 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:11:26.569 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:11:26.569 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:11:26.569 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:11:26.569 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:11:26.569 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:11:26.572 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:11:26.572 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:11:26.572 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:11:26.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:26.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:26.577 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:11:27.061 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:11:27.542 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:11:28.022 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:11:28.504 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:11:28.986 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:11:29.468 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:11:29.950 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:11:30.430 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:11:30.911 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:11:31.394 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:11:31.877 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:11:32.359 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:11:32.840 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:11:33.318 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:11:33.796 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:11:34.276 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:11:34.758 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:11:35.239 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:11:35.720 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:11:36.202 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:11:36.683 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:11:37.164 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:11:37.647 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:11:38.129 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:11:38.610 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:11:39.091 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:11:39.569 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:11:40.048 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:11:40.526 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:11:41.004 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:11:41.482 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:11:41.960 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:11:42.440 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:11:42.922 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:11:43.403 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:11:43.885 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:11:44.366 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:11:44.845 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:11:45.323 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:11:45.801 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:11:46.279 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:11:46.757 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:11:47.235 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:11:47.713 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:11:48.191 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:11:48.669 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:11:49.147 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:11:49.625 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:11:50.103 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:11:50.581 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:11:50.602 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:11:50.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:11:50.602 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:11:50.602 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:11:50.602 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:11:50.602 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:11:50.602 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:11:50.602 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5106 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:50.602 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5106 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:50.602 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5106 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:50.602 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5106 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:50.602 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5106 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:50.602 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5106 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:50.602 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5106 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:50.602 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5106 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:11:55.606 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:11:55.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:11:55.607 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:11:55.608 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:11:55.608 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:11:55.609 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:11:55.614 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:11:55.615 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:11:55.615 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:11:55.615 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:11:55.615 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:11:55.618 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:11:55.618 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:11:55.619 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:11:55.619 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:11:55.619 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:11:55.620 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:11:55.620 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:11:55.620 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:11:55.620 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:11:55.621 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:11:55.621 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:11:55.621 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:11:55.621 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:11:55.621 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:11:55.621 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:11:55.621 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:11:55.621 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:11:55.621 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:11:55.623 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:11:55.623 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:11:55.623 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:11:55.623 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:11:55.624 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:11:55.624 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:11:55.624 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:11:55.624 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:11:55.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:11:55.627 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:11:55.627 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:11:55.627 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:11:55.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:55.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:11:55.632 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:11:56.117 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:11:56.598 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:11:57.079 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:11:57.560 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:11:58.041 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:11:58.522 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:11:59.004 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:11:59.485 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:11:59.967 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:12:00.461 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:12:00.942 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:12:01.424 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:12:01.905 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:12:02.386 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:12:02.867 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:12:03.347 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:12:03.825 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:12:04.307 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:12:04.788 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:12:05.269 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:12:05.751 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:12:06.233 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:12:06.714 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:12:07.195 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:12:07.676 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:12:08.158 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:12:08.638 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:12:09.118 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:12:09.599 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:12:10.080 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:12:10.562 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:12:11.044 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:12:11.525 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:12:12.006 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:12:12.487 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:12:12.969 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:12:13.450 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:12:13.931 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:12:14.413 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:12:14.893 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:12:15.371 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:12:15.852 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:12:16.334 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:12:16.815 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:12:17.297 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:12:17.777 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:12:18.256 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:12:18.737 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:12:19.218 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:12:19.699 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:12:20.179 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:12:20.660 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:12:21.142 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:12:21.623 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:12:22.104 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:12:22.585 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:12:23.066 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:12:23.546 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:12:24.028 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:12:24.510 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:12:24.991 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:12:25.474 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 02:12:25.955 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 02:12:26.437 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 02:12:26.918 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 02:12:27.397 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 02:12:27.875 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 02:12:28.353 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 02:12:28.830 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 02:12:29.309 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 02:12:29.787 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 02:12:30.265 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 02:12:30.746 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 02:12:31.227 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 02:12:31.709 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 02:12:32.190 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 02:12:32.664 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:12:32.671 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 02:12:33.149 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 02:12:33.630 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 02:12:33.666 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:12:34.110 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 02:12:34.591 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 02:12:34.667 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:12:35.072 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 02:12:35.550 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 02:12:35.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:12:36.028 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 02:12:36.506 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 02:12:36.670 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:12:36.984 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 02:12:37.465 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 02:12:37.668 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:12:37.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:12:37.669 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:12:37.669 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:12:37.669 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:12:37.669 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:12:37.669 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:12:37.669 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:12:42.671 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:12:42.671 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:12:42.672 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:12:42.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:12:42.675 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:12:42.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:12:42.683 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:12:42.683 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:12:42.683 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:12:42.684 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:12:42.684 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:12:42.686 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:12:42.686 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:12:42.686 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:12:42.687 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:12:42.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:12:42.687 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:12:42.688 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:12:42.688 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:12:42.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:12:42.689 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:12:42.689 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:12:42.690 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:12:42.690 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:12:42.690 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:12:42.691 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:12:42.691 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:12:42.691 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:12:42.691 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:12:42.692 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:12:42.692 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:12:42.692 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:12:42.692 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:12:42.692 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:12:42.692 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:12:42.692 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:12:42.692 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:12:42.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:12:42.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:12:42.697 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:12:42.697 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:12:42.697 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:12:42.697 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:12:42.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:12:42.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:12:42.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:12:42.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:12:42.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:12:42.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:12:42.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:12:42.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:12:42.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:12:42.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:12:42.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:12:42.702 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:12:43.184 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:12:43.234 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:12:43.236 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:12:43.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:12:43.238 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:12:43.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:12:43.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:12:43.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:12:43.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:43.273 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:12:43.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:12:43.273 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:12:43.273 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:12:43.324 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:12:43.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:12:43.342 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:12:43.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:12:43.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:43.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:43.661 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:12:43.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:12:43.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:12:43.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:12:43.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:12:44.139 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:12:44.617 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:12:44.643 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:12:44.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:12:44.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:12:44.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:12:44.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:12:45.095 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:12:45.573 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:12:45.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:12:45.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:12:45.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:12:45.707 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:12:46.051 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:12:46.529 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:12:46.703 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:12:46.703 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:12:46.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:12:46.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:12:47.007 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:12:47.485 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:12:47.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:12:47.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:47.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:12:47.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:12:47.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:12:47.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:12:47.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:12:47.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:47.590 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:12:47.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:12:47.590 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:12:47.590 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:12:47.624 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:12:47.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:12:47.639 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:12:47.639 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:12:47.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:47.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:47.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:12:47.704 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:12:47.704 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:12:47.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:12:47.963 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:12:48.441 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:12:48.781 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:12:48.919 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:12:49.398 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:12:49.876 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:12:50.354 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:12:50.832 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:12:51.311 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:12:51.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:12:51.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:51.712 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:12:51.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:12:51.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:12:51.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:12:51.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:12:51.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:51.729 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:12:51.729 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:12:51.729 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:12:51.729 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:12:51.782 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:12:51.789 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:12:51.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:12:51.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:12:51.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:12:51.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:51.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:52.225 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:12:52.267 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:12:52.745 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:12:53.223 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:12:53.700 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:12:54.178 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:12:54.656 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:12:55.134 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:12:55.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:12:55.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:55.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:12:55.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:12:55.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:12:55.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:12:55.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:12:55.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:55.595 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:12:55.595 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:12:55.596 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:12:55.596 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:12:55.601 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:12:55.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:12:55.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:12:55.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:12:55.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:55.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:55.611 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:12:56.088 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:12:56.478 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:12:56.567 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:12:56.957 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:12:57.044 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:12:57.522 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:12:57.912 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:12:58.001 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:12:58.478 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:12:58.957 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:12:59.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:12:59.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:12:59.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:12:59.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:12:59.361 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:12:59.361 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:12:59.362 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:12:59.362 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:12:59.365 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:12:59.365 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:12:59.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:12:59.366 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:12:59.366 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:12:59.366 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:12:59.366 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:12:59.366 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3557 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.366 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3557 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3557 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3557 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3557 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3557 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3557 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3558 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3558 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3558 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3558 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3558 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3558 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3558 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:12:59.368 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3558 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:04.365 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:13:04.365 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:13:04.366 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:13:04.367 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:13:04.367 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:13:04.368 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:13:04.376 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:13:04.378 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:13:04.378 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:13:04.378 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:13:04.379 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:13:04.382 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:13:04.382 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:13:04.383 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:13:04.383 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:13:04.383 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:13:04.384 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:13:04.384 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:13:04.384 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:13:04.385 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:04.385 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:13:04.385 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:13:04.385 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:13:04.385 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:13:04.385 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:13:04.386 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:13:04.386 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:13:04.386 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:13:04.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:04.387 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:13:04.388 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:13:04.388 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:13:04.388 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:13:04.388 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:13:04.388 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:13:04.388 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:13:04.388 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:13:04.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:04.391 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:13:04.391 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:13:04.391 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:13:04.392 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:04.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:04.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:04.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:04.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:04.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:04.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:04.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:04.396 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:13:04.878 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:13:04.917 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:13:04.918 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:04.918 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:13:04.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:04.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:04.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:04.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:13:04.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:04.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:04.957 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:04.957 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:13:04.957 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:13:04.971 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:04.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:04.979 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:04.979 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:04.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:04.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:05.356 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:13:05.357 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:05.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:05.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:05.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:05.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:05.833 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:13:05.850 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:05.853 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:13:06.311 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:13:06.336 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:06.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:06.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:06.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:06.400 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:06.789 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:13:06.824 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:07.268 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:13:07.311 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:07.396 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:07.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:07.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:07.401 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:07.746 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:13:07.798 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:08.223 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:13:08.285 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:08.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:08.397 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:08.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:08.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:08.700 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:13:08.772 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:09.178 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:13:09.259 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:09.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:09.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:09.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:09.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:09.656 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:13:09.746 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:10.134 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:13:10.233 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:10.612 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:13:10.720 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:11.090 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:13:11.207 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:11.568 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:13:11.694 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:12.046 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:13:12.181 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:12.524 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:13:12.669 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:12.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:12.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:12.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:12.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:12.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:12.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:12.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:13:12.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:12.693 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:12.693 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:12.693 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:13:12.693 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:13:12.705 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:12.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:12.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:12.713 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:12.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:12.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:13.001 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:13:13.397 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:13.480 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:13:13.884 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:13.887 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:13:13.958 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:13:14.371 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:14.435 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:13:14.858 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:14.914 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:13:15.345 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:15.392 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:13:15.833 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:15.870 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:13:16.320 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:16.348 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:13:16.808 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:16.827 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:13:17.295 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:17.305 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:13:17.783 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:17.783 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:13:18.261 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:13:18.278 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:18.740 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:13:18.765 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:19.218 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:13:19.253 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:19.696 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:13:19.740 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:20.174 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:13:20.228 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:20.652 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:13:20.715 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:20.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:20.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:20.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:20.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:20.723 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=3485 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:20.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:20.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:20.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:13:20.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:20.740 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:20.740 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:20.740 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:13:20.740 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:13:20.741 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:20.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:20.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:20.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:20.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:20.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:21.088 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:21.128 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:13:21.563 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:21.566 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:13:21.606 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:13:22.041 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:22.083 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:13:22.519 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:22.561 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:13:22.997 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:23.039 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:13:23.475 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:23.517 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:13:23.952 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:23.994 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:13:24.430 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:24.473 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:13:24.908 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:24.950 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:13:25.386 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:25.428 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:13:25.864 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:25.906 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:13:26.342 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:26.384 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:13:26.820 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:26.862 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:13:27.297 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:27.339 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:13:27.775 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:27.817 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:13:28.253 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:28.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:28.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:28.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:28.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:28.275 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:28.275 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:28.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:13:28.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:28.277 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:28.277 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:28.277 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:13:28.277 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:13:28.285 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:28.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:28.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:28.289 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:28.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:28.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:28.295 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:13:28.685 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:28.773 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:13:29.163 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:29.165 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:13:29.250 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:13:29.640 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:29.643 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:13:29.727 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:13:30.117 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:30.205 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:13:30.595 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:30.598 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:13:30.683 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:13:31.073 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:31.161 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:13:31.552 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:31.640 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:13:32.030 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:32.118 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:13:32.508 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:32.596 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:13:32.986 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:33.073 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:13:33.464 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:33.551 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:13:33.941 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:34.030 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 02:13:34.420 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:34.507 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 02:13:34.898 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:34.986 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 02:13:35.376 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:35.464 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 02:13:35.855 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:35.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:35.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:35.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:35.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:35.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:35.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:35.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:35.862 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:35.863 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:13:35.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:13:35.863 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:13:35.863 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:13:35.863 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:13:35.863 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:13:35.863 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:13:40.866 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:13:40.866 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:13:40.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:13:40.868 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:13:40.869 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:13:40.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:13:40.874 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:13:40.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:13:40.876 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:13:40.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:13:40.876 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:13:40.879 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:13:40.880 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:13:40.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:13:40.880 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:13:40.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:13:40.881 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:13:40.881 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:13:40.882 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:13:40.882 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:40.882 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:13:40.883 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:13:40.883 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:13:40.883 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:13:40.883 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:13:40.883 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:13:40.883 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:13:40.883 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:13:40.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:40.885 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:13:40.885 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:13:40.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:13:40.885 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:13:40.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:13:40.885 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:13:40.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:13:40.885 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:13:40.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:40.887 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:13:40.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:13:40.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:13:40.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:13:40.887 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:13:40.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:13:40.888 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:13:40.888 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:13:40.888 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:40.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:40.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:40.893 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:13:41.375 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:13:41.418 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:13:41.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:41.422 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:41.424 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:13:41.446 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:41.447 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:41.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:13:41.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:41.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:41.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:41.452 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:13:41.452 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:13:41.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:41.479 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:41.479 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:41.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:41.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:41.853 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:13:41.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:41.891 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:41.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:41.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:42.331 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:13:42.809 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:13:42.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:42.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:42.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:42.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:43.287 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:13:43.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:43.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:43.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:43.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:43.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:43.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:43.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:13:43.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:43.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:43.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:43.606 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:13:43.606 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:13:43.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:43.613 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:43.613 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:43.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:43.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:43.765 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:13:43.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:43.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:43.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:43.897 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:44.242 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:13:44.720 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:13:44.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:44.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:44.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:44.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:45.197 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:13:45.675 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:13:45.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:45.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:45.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:45.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:45.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:45.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:45.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:13:45.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:45.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:45.741 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:45.741 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:13:45.741 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:13:45.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:45.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:45.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:45.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:45.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:45.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:45.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:45.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:45.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:46.153 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:13:46.631 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:13:47.108 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:13:47.586 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:13:47.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:47.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:47.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:47.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:47.880 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:47.880 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:47.880 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:47.880 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:47.883 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:13:47.883 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:13:47.883 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:13:47.883 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:13:47.884 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:13:47.884 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:13:47.884 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:13:47.884 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:47.884 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:47.884 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:47.884 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:47.885 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:47.885 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:47.885 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:52.882 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:13:52.882 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:13:52.883 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:13:52.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:13:52.886 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:13:52.886 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:13:52.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:13:52.894 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:13:52.894 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:13:52.894 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:13:52.894 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:13:52.896 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:13:52.896 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:13:52.897 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:13:52.897 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:13:52.897 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:13:52.897 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:13:52.897 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:13:52.897 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:13:52.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:52.899 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:13:52.899 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:13:52.899 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:13:52.899 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:13:52.899 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:13:52.899 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:13:52.900 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:13:52.900 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:13:52.900 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:52.901 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:13:52.901 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:13:52.902 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:13:52.902 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:13:52.902 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:13:52.902 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:13:52.902 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:13:52.902 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:13:52.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:52.904 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:13:52.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:13:52.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:13:52.905 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:13:52.905 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:13:52.905 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:13:52.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:13:52.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:52.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:52.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:52.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:13:52.910 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:13:53.393 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:13:53.424 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:13:53.425 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:13:53.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:53.427 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:13:53.444 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:53.444 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:53.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:13:53.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:53.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:53.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:53.449 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:13:53.449 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:13:53.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:53.497 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:53.497 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:53.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:53.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:53.867 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:13:53.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:53.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:53.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:53.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:54.345 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:13:54.823 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:13:54.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:54.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:54.911 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:54.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:55.302 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:13:55.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:55.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:55.601 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:55.601 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:55.619 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:55.619 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:55.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:13:55.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:55.620 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:55.620 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:55.620 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:13:55.620 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:13:55.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:55.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:13:55.629 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:13:55.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:55.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:55.776 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:13:55.911 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:55.911 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:55.912 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:55.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:56.254 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:13:56.732 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:13:56.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:56.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:56.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:56.916 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:57.210 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:13:57.688 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:13:57.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:13:57.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:13:57.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:13:57.733 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:13:57.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:13:57.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:13:57.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:13:57.739 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:13:57.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:13:57.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:13:57.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:13:57.740 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:13:57.740 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:13:57.740 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:13:57.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:13:57.740 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:57.740 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:57.740 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:57.740 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:57.740 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:57.740 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:57.740 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:13:57.740 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:02.743 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:02.743 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:02.744 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:02.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:02.746 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:02.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:02.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:02.756 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:02.756 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:02.757 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:02.757 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:14:02.760 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:14:02.760 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:14:02.760 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:02.761 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:02.761 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:02.762 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:14:02.762 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:02.762 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:14:02.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:02.764 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:14:02.764 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:14:02.764 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:02.764 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:02.764 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:02.764 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:14:02.765 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:02.765 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:14:02.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:02.767 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:14:02.767 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:14:02.767 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:02.767 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:02.768 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:02.768 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:14:02.768 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:02.768 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:14:02.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:02.771 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:14:02.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:14:02.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:02.772 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:14:02.772 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:14:02.772 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:14:02.773 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:14:02.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:02.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:02.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:02.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:14:02.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:02.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:02.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:02.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:02.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:02.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:02.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:02.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:02.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:02.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:02.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:02.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:02.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:02.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:02.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:02.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:02.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:02.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:02.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:02.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:02.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:02.777 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:14:03.260 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:14:03.302 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:14:03.304 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:14:03.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:03.307 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:14:03.328 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:03.329 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:03.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:14:03.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:03.334 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:03.335 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:03.335 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:14:03.335 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:14:03.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:03.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:03.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:03.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:03.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:03.738 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:14:03.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:03.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:03.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:03.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:04.216 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:14:04.694 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:14:04.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:04.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:04.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:04.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:05.173 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:14:05.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:05.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:05.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:05.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:05.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:05.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:05.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:14:05.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:05.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:05.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:05.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:14:05.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:14:05.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:05.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:05.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:05.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:05.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:05.648 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:14:05.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:05.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:05.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:05.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:06.125 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:14:06.602 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:14:06.779 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:06.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:06.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:06.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:07.080 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:14:07.557 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:14:07.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:07.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:07.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:07.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:07.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:07.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:07.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:14:07.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:07.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:07.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:07.605 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:14:07.605 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:14:07.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:07.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:07.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:07.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:07.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:07.779 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:07.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:07.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:07.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:08.034 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:14:08.511 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:14:08.989 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:14:09.467 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:14:09.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:09.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:09.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:09.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:09.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:09.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:09.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:09.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:09.765 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:09.765 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:09.765 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:09.765 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:09.765 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:09.765 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:09.765 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:14:09.765 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:09.765 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:09.765 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:09.765 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:09.765 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:09.765 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:09.765 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1494 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:14.766 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:14.766 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:14.767 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:14.769 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:14.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:14.770 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:14.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:14.781 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:14.781 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:14.781 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:14.781 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:14:14.783 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:14:14.784 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:14:14.784 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:14.784 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:14.784 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:14.784 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:14:14.784 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:14.784 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:14:14.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:14.786 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:14:14.786 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:14:14.786 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:14.786 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:14.786 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:14:14.786 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:14.787 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:14.787 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:14:14.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:14.788 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:14:14.788 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:14:14.788 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:14.788 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:14.788 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:14:14.788 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:14.788 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:14.788 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:14:14.789 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:14.790 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:14:14.791 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:14:14.791 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:14:14.791 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:14.796 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:14:15.278 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:14:15.314 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:14:15.316 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:14:15.316 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:14:15.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:15.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:15.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:15.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:14:15.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:15.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:15.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:15.332 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:14:15.332 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:14:15.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:15.381 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:15.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:15.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:15.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:15.755 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:14:15.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:15.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:15.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:15.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:16.234 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:14:16.712 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:14:16.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:16.795 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:16.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:16.795 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:17.190 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:14:17.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:17.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:17.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:17.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:17.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:17.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:17.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:14:17.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:17.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:17.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:17.529 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:14:17.529 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:14:17.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:17.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:17.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:17.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:17.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:17.667 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:14:17.795 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:17.795 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:17.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:17.796 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:18.146 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:14:18.624 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:14:18.795 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:18.796 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:18.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:18.796 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:19.102 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:14:19.580 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:14:19.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:19.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:19.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:19.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:19.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:19.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:19.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:19.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:19.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:19.698 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:19.698 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:19.698 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:19.698 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:19.698 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:19.698 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1046 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1046 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1046 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1046 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1046 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1046 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1047 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1047 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1047 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1047 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1047 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1047 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1047 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:19.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1047 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:24.697 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:24.698 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:24.699 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:24.700 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:24.701 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:24.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:24.708 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:24.709 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:24.709 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:24.709 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:24.709 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:14:24.711 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:14:24.711 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:14:24.711 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:24.711 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:24.712 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:24.712 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:14:24.712 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:24.712 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:14:24.712 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:24.714 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:14:24.714 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:14:24.714 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:24.714 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:24.714 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:24.714 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:14:24.714 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:24.714 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:14:24.714 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:24.716 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:14:24.716 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:14:24.716 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:24.716 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:24.716 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:24.716 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:14:24.716 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:24.716 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:14:24.716 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:24.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:14:24.720 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:14:24.720 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:14:24.720 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:24.720 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:24.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:24.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:24.721 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:24.721 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:24.721 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:24.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:24.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:24.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:24.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:24.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:24.725 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:14:25.206 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:14:25.242 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:14:25.242 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:14:25.243 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:14:25.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:25.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:25.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:25.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:14:25.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:25.269 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:25.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:25.270 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:14:25.270 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:14:25.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:25.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:25.314 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:25.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:25.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:25.686 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:14:25.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:25.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:25.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:25.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:26.164 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:14:26.642 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:14:26.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:26.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:26.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:26.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:27.120 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:14:27.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:27.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:27.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:27.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:27.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:27.489 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:27.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:27.489 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:27.493 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:27.493 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:27.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:27.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:27.493 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:27.493 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:27.493 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:14:27.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=592 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:27.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=592 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:27.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=592 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:27.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=592 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:27.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=592 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:27.494 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=592 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:32.492 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:32.492 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:32.493 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:32.496 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:32.496 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:32.496 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:32.504 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:32.504 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:32.504 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:32.504 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:32.505 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:14:32.507 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:14:32.507 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:14:32.507 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:32.507 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:32.508 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:32.508 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:14:32.508 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:32.508 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:14:32.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:32.510 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:14:32.510 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:14:32.510 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:32.510 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:32.510 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:32.510 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:14:32.510 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:32.510 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:14:32.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:32.512 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:14:32.512 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:14:32.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:32.512 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:32.513 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:32.513 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:14:32.513 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:32.513 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:14:32.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:32.515 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:14:32.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:14:32.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:14:32.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:14:32.515 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:14:32.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:14:32.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:14:32.516 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:14:32.516 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:14:32.516 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:32.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:32.521 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:14:33.004 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:14:33.038 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:14:33.039 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:14:33.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:33.040 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:14:33.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:33.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:33.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:14:33.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:33.065 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:33.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:33.066 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:14:33.066 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:14:33.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:33.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:33.112 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:33.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:33.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:33.482 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:14:33.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:33.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:33.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:33.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:33.961 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:14:34.439 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:14:34.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:34.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:34.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:34.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:34.917 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:14:35.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:35.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:35.314 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:35.315 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:35.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:35.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:35.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:35.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:35.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:35.326 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:35.326 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:35.326 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:35.326 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:35.326 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:35.326 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:14:35.326 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:35.326 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:35.326 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:35.326 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:40.327 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:40.327 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:40.328 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:40.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:40.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:40.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:40.334 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:40.336 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:40.336 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:40.336 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:40.336 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:14:40.339 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:14:40.339 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:14:40.340 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:40.340 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:40.340 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:40.340 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:14:40.341 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:40.341 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:14:40.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:40.342 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:14:40.342 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:14:40.343 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:40.343 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:40.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:40.343 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:14:40.343 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:40.343 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:14:40.343 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:40.344 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:14:40.345 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:14:40.345 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:40.345 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:40.345 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:40.345 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:14:40.345 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:40.345 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:14:40.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:40.347 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:14:40.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:14:40.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:14:40.348 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:14:40.348 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:14:40.348 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:14:40.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:40.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:40.353 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:14:40.837 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:14:40.873 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:14:40.874 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:14:40.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:40.876 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:14:40.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:40.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:40.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:14:40.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:40.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:40.939 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:40.939 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:14:40.939 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:14:40.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:40.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:40.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:40.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:40.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:41.311 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:14:41.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:41.351 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:41.353 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:41.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:41.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:41.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:41.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:41.364 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:41.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:41.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:41.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:14:41.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:41.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:41.390 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:41.390 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:14:41.390 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:14:41.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:41.399 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:41.399 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:41.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:41.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:41.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:41.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:41.780 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:41.780 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:41.785 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:14:41.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:41.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:41.789 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:41.789 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:41.792 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:41.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:41.792 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:41.792 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:41.792 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:41.792 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:41.792 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:14:46.791 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:46.791 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:46.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:46.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:46.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:46.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:46.801 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:46.802 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:46.802 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:46.803 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:46.803 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:14:46.805 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:14:46.805 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:14:46.805 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:46.805 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:46.805 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:46.805 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:14:46.806 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:46.806 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:14:46.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:46.807 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:14:46.807 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:14:46.807 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:46.807 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:46.807 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:46.808 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:14:46.808 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:46.808 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:14:46.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:46.809 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:14:46.809 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:14:46.809 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:46.809 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:46.809 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:46.810 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:14:46.810 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:46.810 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:14:46.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:46.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:14:46.813 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:14:46.813 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:14:46.813 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:46.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:46.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:46.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:46.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:46.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:46.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:46.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:46.817 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:14:47.299 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:14:47.335 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:14:47.337 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:14:47.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:47.337 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:14:47.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:47.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:47.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:14:47.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:47.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:47.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:47.402 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:14:47.402 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:14:47.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:47.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:47.446 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:47.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:47.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:47.775 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:14:47.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:47.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:47.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:47.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:47.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:47.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:47.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:47.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:47.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:47.845 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:47.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:14:47.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:47.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:47.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:47.855 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:14:47.855 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:14:47.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:47.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:47.868 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:47.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:47.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:48.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:48.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:48.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:48.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:48.252 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:14:48.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:48.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:48.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:48.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:48.258 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:48.258 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:48.258 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:48.258 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:48.258 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:48.258 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:48.258 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:14:53.258 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:53.259 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:53.260 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:53.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:53.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:53.262 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:53.266 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:53.267 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:53.268 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:53.268 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:53.268 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:14:53.271 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:14:53.271 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:14:53.271 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:53.271 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:53.272 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:53.272 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:14:53.273 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:53.273 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:14:53.273 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:53.274 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:14:53.274 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:14:53.274 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:53.274 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:53.274 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:53.274 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:14:53.274 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:53.274 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:14:53.274 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:53.276 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:14:53.276 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:14:53.276 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:53.276 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:53.276 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:53.276 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:14:53.276 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:53.276 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:14:53.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:53.279 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:14:53.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:14:53.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:14:53.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:14:53.279 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:14:53.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:14:53.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:14:53.280 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:14:53.280 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:14:53.280 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:53.280 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:53.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:53.285 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:14:53.765 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:14:53.810 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:14:53.812 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:14:53.815 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:14:53.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:53.840 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:53.840 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:53.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:14:53.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:53.878 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:53.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:53.879 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:14:53.879 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:14:53.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:53.914 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:53.914 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:53.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:53.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:54.244 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:14:54.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:54.283 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:54.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:54.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:54.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:54.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:54.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:54.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:54.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:54.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:54.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:14:54.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:54.327 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:54.327 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:54.327 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:14:54.327 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:14:54.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:54.336 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:14:54.336 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:14:54.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:54.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:54.720 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:14:54.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:14:54.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:14:54.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:14:54.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:14:54.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:54.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:54.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:54.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:54.774 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:54.774 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:54.774 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:54.774 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:54.774 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:54.774 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:54.774 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:14:54.774 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:54.774 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:54.774 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:54.774 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:54.774 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:54.774 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:14:59.775 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:14:59.775 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:14:59.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:59.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:59.777 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:59.778 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:59.785 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:14:59.785 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:59.785 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:59.786 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:14:59.786 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:14:59.788 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:14:59.788 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:14:59.788 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:59.788 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:59.788 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:14:59.788 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:14:59.788 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:14:59.788 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:14:59.789 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:14:59.791 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:14:59.791 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:14:59.791 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:59.791 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:59.791 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:14:59.791 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:14:59.791 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:14:59.791 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:14:59.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:14:59.794 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:14:59.794 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:14:59.794 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:59.794 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:14:59.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:14:59.794 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:14:59.795 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:14:59.795 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:14:59.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:14:59.798 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:14:59.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:14:59.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:14:59.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:14:59.798 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:14:59.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:14:59.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:14:59.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:14:59.799 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:14:59.799 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:14:59.799 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:59.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:14:59.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:59.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:59.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:14:59.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:59.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:59.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:14:59.804 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:15:00.286 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:15:00.349 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:15:00.350 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:15:00.352 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:15:00.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:00.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:00.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:00.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:15:00.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:00.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:00.416 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:00.416 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:15:00.416 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:15:00.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:00.433 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:00.433 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:00.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:00.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:00.759 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:15:00.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:00.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:00.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:00.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:01.237 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:15:01.715 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:15:01.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:01.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:01.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:01.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:02.193 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:15:02.671 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:15:02.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:02.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:02.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:02.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:03.150 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:15:03.628 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:15:03.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:03.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:03.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:03.814 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:04.106 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:15:04.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:04.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:04.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:04.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:04.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:04.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:04.441 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:04.441 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:04.441 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:04.441 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:04.441 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:04.441 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:04.441 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:15:09.443 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:09.443 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:09.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:09.446 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:09.446 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:09.447 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:09.460 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:09.461 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:09.461 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:09.461 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:09.461 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:15:09.463 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:15:09.463 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:15:09.463 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:09.464 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:09.464 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:09.464 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:15:09.464 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:09.464 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:15:09.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:09.465 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:15:09.465 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:15:09.465 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:09.465 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:09.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:09.465 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:15:09.466 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:09.466 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:15:09.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:09.467 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:15:09.467 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:15:09.467 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:09.467 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:09.467 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:15:09.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:09.467 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:09.467 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:15:09.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:15:09.469 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:15:09.469 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:15:09.469 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:09.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:09.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:09.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:09.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:09.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:09.474 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:15:09.955 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:15:09.989 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:15:09.991 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:15:09.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:09.992 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:15:10.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:10.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:10.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:15:10.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:10.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:10.041 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:10.041 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:15:10.041 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:15:10.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:10.057 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:10.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:10.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:10.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:10.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:10.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:10.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:10.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:10.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:10.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:10.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:15:10.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:10.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:10.313 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:10.313 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:15:10.313 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:15:10.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:10.334 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:10.335 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:10.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:10.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:10.428 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:15:10.472 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:10.472 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:10.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:10.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:10.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:10.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:10.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:10.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:10.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:10.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:10.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:10.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:10.569 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:10.569 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:10.569 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:10.569 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:10.570 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:10.570 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:10.570 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:15:10.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.571 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.571 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.571 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:10.571 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:15.568 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:15.569 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:15.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:15.571 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:15.571 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:15.571 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:15.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:15.581 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:15.581 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:15.581 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:15.582 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:15:15.585 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:15:15.585 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:15:15.586 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:15.586 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:15.586 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:15.587 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:15:15.587 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:15.587 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:15:15.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:15.588 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:15:15.588 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:15:15.588 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:15.588 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:15.588 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:15.589 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:15:15.589 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:15.589 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:15:15.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:15.591 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:15:15.591 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:15:15.591 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:15.591 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:15.591 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:15.591 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:15:15.591 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:15.591 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:15:15.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:15.594 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:15:15.595 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:15:15.595 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:15:15.595 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:15.595 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:15.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:15.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:15.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:15.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:15.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:15.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:15.600 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:15:16.083 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:15:16.119 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:15:16.121 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:15:16.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:16.122 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:15:16.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:16.135 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:16.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:15:16.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:16.169 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:16.169 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:16.169 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:15:16.169 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:15:16.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:16.183 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:16.183 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:16.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:16.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:16.559 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:15:16.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:16.598 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:16.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:16.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:17.037 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:15:17.515 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:15:17.598 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:17.599 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:17.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:17.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:17.993 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:15:18.471 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:15:18.600 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:18.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:18.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:18.603 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:18.949 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:15:19.426 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:15:19.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:19.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:19.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:19.604 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:19.904 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:15:20.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:20.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:20.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:20.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:20.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:20.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:20.191 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:20.191 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:20.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:20.191 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:20.191 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:20.191 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:15:20.191 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:20.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=982 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:20.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=982 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:20.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=982 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:20.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=982 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:20.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=982 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:20.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=982 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:20.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=982 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:20.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=982 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:25.194 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:25.194 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:25.196 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:25.197 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:25.198 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:25.198 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:25.206 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:25.206 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:25.206 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:25.206 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:25.206 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:15:25.208 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:15:25.208 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:15:25.208 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:25.208 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:25.209 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:25.209 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:15:25.209 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:25.209 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:15:25.210 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:25.210 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:15:25.210 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:15:25.210 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:25.210 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:25.210 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:25.210 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:15:25.211 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:25.211 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:15:25.211 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:25.212 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:15:25.212 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:15:25.212 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:25.212 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:25.212 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:25.212 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:15:25.212 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:25.212 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:15:25.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:15:25.215 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:15:25.215 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:15:25.215 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:25.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:25.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:25.220 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:15:25.702 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:15:25.741 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:15:25.742 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:15:25.743 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:15:25.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:25.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:25.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:25.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:15:25.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:25.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:25.779 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:25.779 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:15:25.780 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:15:25.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:25.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:25.804 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:25.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:25.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:26.179 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:15:26.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:26.218 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:26.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:26.222 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:26.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:26.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:26.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:26.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:26.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:26.525 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:26.525 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:26.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:26.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:26.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:26.527 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:26.527 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:26.527 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:15:26.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:26.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:26.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:26.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:26.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:26.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:26.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:26.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:26.528 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:31.527 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:31.527 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:31.528 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:31.530 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:31.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:31.531 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:31.539 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:31.540 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:31.540 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:31.540 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:31.540 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:15:31.542 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:15:31.542 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:15:31.542 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:31.542 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:31.543 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:31.543 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:15:31.543 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:31.543 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:15:31.543 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:31.544 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:15:31.544 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:15:31.544 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:31.544 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:31.544 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:31.544 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:15:31.544 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:31.544 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:15:31.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:31.545 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:15:31.546 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:15:31.546 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:31.546 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:31.546 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:31.546 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:15:31.546 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:31.546 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:15:31.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:15:31.548 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:15:31.548 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:15:31.548 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:31.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:31.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:31.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:31.549 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:31.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:31.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:31.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:31.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:31.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:31.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:31.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:31.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:31.553 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:15:32.037 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:15:32.071 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:15:32.073 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:15:32.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:32.074 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:15:32.089 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:32.089 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:32.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:15:32.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:32.128 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:32.128 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:32.128 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:15:32.128 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:15:32.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:32.185 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:32.186 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:32.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:32.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:32.514 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:15:32.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:32.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:32.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:32.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:32.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:32.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:32.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:32.910 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:32.919 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:32.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:32.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:32.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:32.923 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:32.923 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:32.923 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:32.924 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:32.924 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:15:32.924 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:32.924 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:32.924 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:32.924 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:32.924 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:32.925 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:32.925 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:32.925 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:32.925 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:37.923 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:37.923 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:37.924 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:37.925 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:37.926 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:37.926 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:37.933 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:37.934 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:37.934 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:37.934 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:37.934 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:15:37.936 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:15:37.936 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:15:37.937 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:37.937 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:37.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:37.937 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:15:37.938 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:37.938 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:15:37.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:37.938 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:15:37.939 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:15:37.939 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:37.939 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:37.939 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:37.939 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:15:37.939 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:37.939 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:15:37.939 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:37.941 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:15:37.941 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:15:37.941 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:37.941 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:37.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:37.941 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:15:37.941 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:37.941 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:15:37.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:37.943 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:15:37.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:15:37.943 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:15:37.943 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:15:37.943 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:15:37.943 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:15:37.944 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:15:37.944 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:15:37.944 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:37.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:37.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:37.949 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:15:38.430 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:15:38.471 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:15:38.472 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:15:38.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:38.473 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:15:38.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:38.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:38.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:15:38.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:38.541 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:38.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:38.541 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:15:38.542 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:15:38.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:38.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:38.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:38.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:38.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:38.903 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:15:38.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:38.947 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:38.948 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:38.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:39.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:39.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:39.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:39.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:39.306 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:39.306 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:39.306 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:39.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:39.309 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:39.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:39.309 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:39.310 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:39.310 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:39.310 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:39.310 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:15:39.310 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:39.310 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:39.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:39.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:39.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:39.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:39.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:39.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:39.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:39.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:39.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:39.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:39.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:39.312 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:44.309 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:44.309 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:44.311 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:44.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:44.313 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:44.313 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:44.321 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:44.322 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:44.323 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:44.323 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:44.323 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:15:44.325 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:15:44.326 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:15:44.326 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:44.326 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:44.327 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:44.327 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:15:44.327 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:44.327 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:15:44.328 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:44.328 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:15:44.328 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:15:44.328 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:44.328 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:44.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:44.328 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:15:44.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:44.329 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:15:44.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:44.330 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:15:44.330 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:15:44.330 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:44.330 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:44.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:44.331 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:15:44.331 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:44.331 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:15:44.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:15:44.334 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:15:44.334 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:15:44.334 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:44.334 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:44.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:44.339 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:15:44.822 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:15:44.861 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:15:44.863 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:15:44.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:44.864 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:15:44.883 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:44.883 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:44.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:15:44.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:44.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:44.933 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:44.934 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:15:44.934 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:15:44.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:44.969 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:44.970 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:44.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:44.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:45.300 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:15:45.337 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:45.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:45.338 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:45.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:45.778 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:15:45.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:45.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:45.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:45.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:45.844 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:45.845 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:45.845 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:45.845 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:45.848 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:45.848 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:45.848 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:45.849 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:45.849 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:45.849 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:15:45.849 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:45.849 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.849 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.850 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.850 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.850 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.850 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.850 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.850 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.850 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.850 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.850 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.850 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.850 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:45.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:50.848 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:50.848 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:50.849 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:50.851 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:50.851 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:50.852 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:50.859 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:50.860 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:50.860 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:50.860 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:50.860 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:15:50.862 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:15:50.863 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:15:50.863 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:50.863 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:50.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:50.864 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:15:50.864 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:50.864 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:15:50.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:50.865 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:15:50.865 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:15:50.865 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:50.865 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:50.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:50.865 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:15:50.865 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:50.866 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:15:50.866 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:50.869 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:15:50.869 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:15:50.869 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:50.869 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:50.869 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:15:50.869 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:50.869 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:15:50.869 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:50.869 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:50.873 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:15:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:15:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:15:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:15:50.873 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:15:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:15:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:15:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:15:50.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:15:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:50.873 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:50.873 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:15:50.874 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:15:50.874 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:15:50.874 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:50.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:50.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:50.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:50.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:50.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:50.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:50.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:50.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:50.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:50.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:50.879 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:15:51.361 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:15:51.407 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:15:51.409 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:15:51.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:51.411 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:15:51.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:51.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:51.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:15:51.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:51.486 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:51.487 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:51.487 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:15:51.487 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:15:51.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:51.508 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:51.508 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:51.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:51.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:51.839 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:15:51.877 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:51.878 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:51.879 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:51.882 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:52.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:52.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:52.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:52.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:52.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:52.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:52.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:52.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:52.246 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:52.246 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:52.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:52.246 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:52.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:52.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:52.247 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:15:52.247 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:52.247 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:52.247 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:52.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:52.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:52.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:52.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:52.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:52.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:52.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:52.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:57.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:57.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:57.250 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:57.250 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:57.250 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:57.250 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:57.257 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:57.257 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:57.257 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:57.257 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:15:57.257 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:15:57.259 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:15:57.259 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:15:57.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:57.259 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:57.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:57.259 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:15:57.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:15:57.259 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:15:57.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:57.262 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:15:57.262 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:15:57.262 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:57.262 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:57.262 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:57.262 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:15:57.262 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:15:57.263 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:15:57.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:57.265 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:15:57.265 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:15:57.265 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:57.265 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:15:57.265 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:57.265 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:15:57.265 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:15:57.265 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:15:57.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:57.268 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:15:57.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:15:57.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:15:57.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:15:57.268 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:15:57.268 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:15:57.268 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:15:57.268 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:15:57.269 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:15:57.269 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:15:57.269 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:57.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:57.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:15:57.274 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:15:57.758 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:15:57.797 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:15:57.798 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:15:57.799 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:15:57.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:57.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:57.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:57.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:15:57.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:57.858 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:57.859 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:57.859 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:15:57.859 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:15:57.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:57.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:15:57.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:15:57.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:57.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:58.232 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:15:58.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:58.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:58.274 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:58.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:58.711 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:15:58.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:15:58.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:15:58.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:15:58.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:15:58.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:15:58.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:15:58.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:15:58.777 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:15:58.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:15:58.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:15:58.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:15:58.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:15:58.780 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:15:58.780 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:15:58.780 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:15:58.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:58.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:58.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:58.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:58.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:15:58.780 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:03.778 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:16:03.779 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:16:03.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:16:03.781 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:16:03.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:16:03.782 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:16:03.788 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:16:03.789 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:16:03.790 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:03.790 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:16:03.790 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:16:03.793 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:16:03.793 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:16:03.794 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:16:03.794 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:03.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:16:03.795 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:16:03.795 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:16:03.795 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:16:03.796 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:03.797 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:16:03.797 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:16:03.798 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:16:03.798 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:03.798 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:16:03.798 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:16:03.799 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:16:03.799 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:16:03.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:03.800 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:16:03.800 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:16:03.800 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:16:03.800 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:03.801 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:16:03.801 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:16:03.801 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:16:03.801 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:16:03.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:03.804 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:16:03.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:16:03.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:16:03.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:03.805 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:16:03.805 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:16:03.805 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:16:03.806 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:16:03.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:03.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:03.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:03.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:16:03.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:03.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:03.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:03.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:03.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:03.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:03.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:03.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:03.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:03.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:03.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:03.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:03.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:03.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:03.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:03.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:03.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:03.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:03.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:03.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:03.810 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:16:04.293 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:16:04.337 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:16:04.339 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:16:04.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:16:04.341 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:16:04.367 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:16:04.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:16:04.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:16:04.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:04.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:16:04.373 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:16:04.373 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:16:04.373 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:16:04.770 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:16:04.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:04.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:04.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:04.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:05.248 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:16:05.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:16:05.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:16:05.523 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:16:05.523 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:16:05.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:16:05.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:16:05.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:16:05.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:05.544 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:16:05.544 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:16:05.544 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:16:05.544 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:16:05.725 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:16:05.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:05.811 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:05.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:05.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:06.203 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:16:06.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:16:06.681 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:16:06.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:16:06.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:16:06.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:16:06.729 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:06.730 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:06.730 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:06.730 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:06.733 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:16:06.733 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:16:06.733 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:16:06.733 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:16:06.733 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:16:06.733 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:16:06.733 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=624 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=624 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=624 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=624 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=624 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=624 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:06.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:11.734 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:16:11.734 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:16:11.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:16:11.737 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:16:11.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:16:11.741 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:16:11.757 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:16:11.758 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:16:11.758 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:11.759 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:16:11.759 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:16:11.762 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:16:11.762 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:16:11.762 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:16:11.762 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:11.762 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:16:11.763 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:16:11.763 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:16:11.763 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:16:11.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:11.765 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:16:11.765 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:16:11.765 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:16:11.765 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:11.766 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:16:11.766 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:16:11.766 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:16:11.766 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:16:11.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:11.768 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:16:11.768 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:16:11.768 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:16:11.768 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:11.768 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:16:11.768 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:16:11.768 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:16:11.768 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:16:11.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:16:11.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:16:11.772 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:16:11.772 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:16:11.772 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:11.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:11.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:11.777 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:16:12.261 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:16:12.298 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:16:12.300 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:16:12.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:16:12.301 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:16:12.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:16:12.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:16:12.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:16:12.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:12.320 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:16:12.320 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:16:12.320 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:16:12.320 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:16:12.739 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:16:12.775 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:12.775 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:12.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:12.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:13.213 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:16:13.691 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:16:13.775 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:13.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:13.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:13.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:14.169 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:16:14.643 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:16:14.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:14.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:14.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:14.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:15.117 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:16:15.594 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:16:15.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:15.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:15.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:15.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:16.072 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:16:16.549 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:16:16.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:16.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:16.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:16.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:17.027 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:16:17.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:16:17.059 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:16:17.059 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:16:17.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:17.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:17.505 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:16:17.984 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:16:18.462 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:16:18.940 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:16:19.419 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:16:19.900 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:16:20.379 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:16:20.858 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:16:21.336 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:16:21.814 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:16:22.293 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:16:22.771 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:16:23.250 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:16:23.724 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:16:24.203 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:16:24.684 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:16:25.164 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:16:25.643 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:16:26.122 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:16:26.601 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:16:27.080 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:16:27.558 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:16:28.036 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:16:28.281 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:16:28.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:28.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:16:28.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:16:28.295 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:28.296 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:28.296 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:28.296 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:28.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:16:28.299 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:16:28.299 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:16:28.299 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:16:28.299 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:16:28.299 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:16:28.299 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:16:28.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3526 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:28.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3526 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:28.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3526 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:28.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3526 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:28.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3526 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:28.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3526 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:28.299 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3526 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:33.299 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:16:33.299 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:16:33.300 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:16:33.302 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:16:33.303 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:16:33.303 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:16:33.311 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:16:33.312 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:16:33.312 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:33.313 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:16:33.313 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:16:33.316 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:16:33.316 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:16:33.317 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:16:33.317 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:33.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:16:33.318 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:16:33.318 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:16:33.318 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:16:33.319 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:33.319 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:16:33.319 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:16:33.319 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:16:33.319 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:33.319 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:16:33.319 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:16:33.319 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:16:33.319 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:16:33.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:33.321 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:16:33.321 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:16:33.321 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:16:33.321 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:33.322 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:16:33.322 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:16:33.322 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:16:33.322 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:16:33.322 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:33.324 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:16:33.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:16:33.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:16:33.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:16:33.324 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:16:33.325 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:16:33.325 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:16:33.325 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:33.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:33.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:33.330 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:16:33.812 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:16:33.849 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:16:33.851 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:16:33.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:16:33.852 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:16:33.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:16:33.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:16:33.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:16:33.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:33.878 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:16:33.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:16:33.879 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:16:33.879 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:16:34.289 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:16:34.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:34.328 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:34.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:34.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:34.767 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:16:35.245 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:16:35.328 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:35.328 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:35.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:35.333 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:35.723 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:16:36.200 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:16:36.330 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:36.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:36.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:36.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:36.678 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:16:37.156 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:16:37.331 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:37.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:37.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:37.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:37.634 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:16:38.112 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:16:38.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:38.332 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:38.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:38.337 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:38.589 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:16:38.610 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:16:38.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:16:38.617 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:16:38.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:38.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:39.067 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:16:39.546 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:16:40.025 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:16:40.504 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:16:40.989 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:16:41.468 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:16:41.946 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:16:42.424 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:16:42.896 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:16:43.367 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:16:43.838 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:16:44.313 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:16:44.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:16:44.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:44.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:16:44.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:16:44.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:44.469 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:44.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:44.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:44.472 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:16:44.472 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:16:44.472 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:16:44.472 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:16:44.472 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:16:44.472 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:16:44.472 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:16:44.472 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2381 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:44.472 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2381 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:44.472 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2381 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:44.472 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2381 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:44.472 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2382 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:44.472 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2382 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:44.472 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2382 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:44.472 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2382 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:44.472 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2382 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:44.472 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2382 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:44.472 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2382 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:44.472 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2382 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:49.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:16:49.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:16:49.475 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:16:49.476 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:16:49.476 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:16:49.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:16:49.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:16:49.482 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:16:49.483 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:49.483 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:16:49.483 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:16:49.487 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:16:49.487 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:16:49.488 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:16:49.488 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:49.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:16:49.489 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:16:49.489 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:16:49.489 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:16:49.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:49.490 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:16:49.490 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:16:49.490 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:16:49.490 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:49.491 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:16:49.491 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:16:49.491 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:16:49.491 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:16:49.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:49.493 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:16:49.493 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:16:49.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:16:49.493 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:16:49.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:16:49.493 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:16:49.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:16:49.493 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:16:49.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:49.496 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:16:49.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:16:49.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:16:49.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:16:49.497 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:16:49.497 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:16:49.497 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:16:49.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:49.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:49.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:49.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:49.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:16:49.502 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:16:49.986 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:16:50.024 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:16:50.026 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:16:50.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:16:50.028 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:16:50.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:16:50.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:16:50.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:16:50.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:50.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:16:50.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:16:50.053 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:16:50.053 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:16:50.463 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:16:50.500 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:50.501 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:50.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:50.505 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:50.941 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:16:51.419 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:16:51.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:51.501 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:51.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:51.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:51.897 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:16:52.375 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:16:52.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:52.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:52.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:52.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:52.852 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:16:53.330 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:16:53.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:53.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:53.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:53.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:53.807 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:16:54.282 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:16:54.503 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:54.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:54.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:54.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:54.760 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:16:54.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:16:54.788 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:16:54.788 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:16:54.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:54.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:55.241 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:16:55.719 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:16:56.199 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:16:56.680 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:16:57.158 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:16:57.636 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:16:58.114 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:16:58.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:16:58.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:16:58.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:16:58.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:16:58.222 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:16:58.225 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:16:58.225 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:16:58.225 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:16:58.226 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:16:58.226 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:16:58.226 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:16:58.226 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:16:58.226 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:16:58.227 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:16:58.227 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:16:58.227 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:58.227 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:58.227 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:58.227 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:58.227 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:16:58.228 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:03.226 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:17:03.226 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:17:03.227 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:03.228 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:03.228 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:03.229 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:03.238 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:03.239 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:17:03.239 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:03.239 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:17:03.240 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:17:03.244 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:17:03.244 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:17:03.244 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:17:03.245 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:03.245 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:03.245 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:17:03.246 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:17:03.246 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:17:03.246 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:03.246 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:17:03.247 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:17:03.247 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:17:03.247 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:03.247 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:03.247 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:17:03.247 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:17:03.247 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:17:03.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:03.249 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:17:03.249 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:17:03.249 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:17:03.249 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:03.249 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:03.249 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:17:03.249 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:17:03.249 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:17:03.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:03.252 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:17:03.252 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:17:03.253 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:17:03.253 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:17:03.253 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:03.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:03.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:03.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:17:03.253 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:03.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:03.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:03.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:03.253 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:03.253 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:03.253 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:03.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:03.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:03.254 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:03.254 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:03.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:03.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:03.254 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:03.254 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:03.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:03.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:03.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:03.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:03.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:03.257 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:17:03.740 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:17:03.786 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:17:03.788 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:17:03.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:17:03.790 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:17:03.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:17:03.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:17:03.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:17:03.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:17:03.814 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:17:03.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:17:03.815 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:17:03.815 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:17:04.217 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:17:04.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:04.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:04.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:04.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:04.695 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:17:05.172 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:17:05.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:05.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:05.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:05.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:05.650 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:17:06.128 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:17:06.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:06.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:06.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:06.266 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:06.605 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:17:07.083 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:17:07.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:07.263 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:07.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:07.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:07.561 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:17:08.039 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:17:08.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:08.264 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:08.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:08.268 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:08.516 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:17:08.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:17:08.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:17:08.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:17:08.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:17:08.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:17:08.994 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:17:09.472 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:17:09.950 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:17:10.428 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:17:10.907 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:17:11.385 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:17:11.863 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:17:11.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:17:11.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:17:11.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:17:11.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:17:11.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:11.972 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:11.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:11.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:11.975 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:11.976 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:11.976 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:11.976 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:11.976 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:17:11.976 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:17:11.976 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1861 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1861 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1861 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1861 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1861 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1861 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1861 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:11.976 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:16.976 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:17:16.977 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:17:16.997 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:16.997 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:16.997 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:16.997 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:17.000 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:17.002 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:17:17.002 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:17.002 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:17:17.002 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:17:17.008 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:17:17.008 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:17:17.008 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:17:17.008 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:17.008 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:17.009 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:17:17.009 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:17:17.009 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:17:17.009 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:17.012 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:17:17.012 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:17:17.012 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:17:17.013 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:17.013 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:17.013 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:17:17.013 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:17:17.013 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:17:17.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:17.016 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:17:17.016 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:17:17.016 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:17:17.016 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:17.016 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:17.016 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:17:17.016 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:17:17.016 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:17:17.017 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:17.019 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:17:17.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:17:17.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:17.020 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:17:17.020 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:17:17.020 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:17:17.020 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:17.021 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:17.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:17.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:17.025 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:17:17.508 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:17:17.543 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:17:17.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:17:17.545 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:17:17.545 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:17:17.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:17:17.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:17:17.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:17:17.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:17:17.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:17:17.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:17:17.573 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:17:17.573 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:17:17.985 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:17:18.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:18.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:18.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:18.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:18.463 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:17:18.940 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:17:19.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:19.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:19.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:19.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:19.418 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:17:19.896 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:17:20.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:20.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:20.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:20.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:20.374 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:17:20.851 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:17:21.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:21.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:21.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:21.031 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:21.329 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:17:21.807 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:17:22.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:22.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:22.030 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:22.032 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:22.285 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:17:22.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:17:22.312 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:17:22.312 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:17:22.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:17:22.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:17:22.763 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:17:23.242 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:17:23.720 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:17:24.200 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:17:24.678 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:17:25.157 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:17:25.635 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:17:25.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:17:25.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:17:25.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:17:25.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:17:25.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:25.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:25.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:25.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:25.749 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:25.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:25.749 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:25.749 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:25.749 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:17:25.749 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:17:25.749 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:17:25.749 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:25.749 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:25.749 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:25.749 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:25.749 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:25.749 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:25.749 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:30.747 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:17:30.747 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:17:30.748 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:30.750 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:30.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:30.751 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:30.759 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:30.760 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:17:30.760 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:30.761 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:17:30.761 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:17:30.764 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:17:30.765 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:17:30.765 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:17:30.765 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:30.766 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:30.766 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:17:30.766 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:17:30.766 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:17:30.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:30.767 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:17:30.768 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:17:30.768 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:17:30.768 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:30.768 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:30.768 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:17:30.768 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:17:30.769 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:17:30.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:30.770 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:17:30.770 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:17:30.770 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:17:30.770 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:30.770 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:30.770 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:17:30.770 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:17:30.770 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:17:30.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:30.773 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:17:30.773 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:17:30.773 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:17:30.773 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:30.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:30.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:30.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:30.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:30.778 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:17:31.260 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:17:31.301 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:17:31.303 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:17:31.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:17:31.305 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:17:31.732 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:17:31.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:31.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:31.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:31.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:32.212 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:17:32.692 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:17:32.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:32.779 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:32.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:32.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:33.173 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:17:33.651 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:17:33.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:33.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:33.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:33.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:34.130 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:17:34.610 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:17:34.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:34.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:34.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:34.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:35.091 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:17:35.572 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:17:35.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:35.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:35.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:35.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:36.050 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:17:36.529 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:17:37.006 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:17:37.485 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:17:37.963 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:17:38.441 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:17:38.922 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:17:39.403 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:17:39.883 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:17:40.361 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:17:40.839 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:17:41.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:41.317 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:17:41.317 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:41.317 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:41.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:41.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:41.318 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:41.318 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:41.318 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:41.318 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:17:41.318 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:17:41.318 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:17:41.318 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2247 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:41.318 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2247 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:41.318 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2247 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:41.318 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2247 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:41.318 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2247 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:41.318 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2247 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:41.318 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2247 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:17:46.321 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:17:46.321 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:17:46.322 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:46.324 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:46.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:46.325 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:46.333 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:46.335 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:17:46.335 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:46.335 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:17:46.336 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:17:46.340 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:17:46.340 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:17:46.340 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:17:46.340 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:46.340 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:46.341 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:17:46.341 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:17:46.341 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:17:46.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:46.343 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:17:46.344 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:17:46.344 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:17:46.344 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:46.344 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:46.344 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:17:46.344 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:17:46.344 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:17:46.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:46.346 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:17:46.347 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:17:46.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:17:46.347 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:46.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:46.347 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:17:46.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:17:46.347 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:17:46.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:46.350 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:17:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:17:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:17:46.350 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:17:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:17:46.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:17:46.351 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:17:46.351 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:17:46.351 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:46.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:46.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:46.353 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:46.353 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:46.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:46.353 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:46.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:46.353 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:46.353 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:17:46.353 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:17:46.353 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:17:51.357 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:17:51.357 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:17:51.358 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:51.360 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:51.361 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:51.361 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:51.368 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:51.369 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:17:51.369 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:51.369 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:17:51.369 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:17:51.372 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:17:51.372 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:17:51.373 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:17:51.373 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:51.373 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:51.373 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:17:51.374 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:17:51.374 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:17:51.374 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:51.375 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:17:51.375 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:17:51.375 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:17:51.375 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:51.375 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:51.375 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:17:51.375 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:17:51.375 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:17:51.375 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:51.377 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:17:51.377 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:17:51.377 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:17:51.377 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:17:51.377 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:51.377 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:17:51.377 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:17:51.377 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:17:51.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:51.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:17:51.381 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:17:51.381 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:17:51.381 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:51.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:51.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:51.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:17:51.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:17:51.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:17:51.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:51.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:51.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:51.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:51.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:17:51.386 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:17:51.870 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:17:51.908 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:17:51.910 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:17:51.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:17:51.912 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:17:51.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:17:51.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:17:51.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:17:51.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:17:51.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:17:51.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:17:51.916 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:17:51.916 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:17:52.347 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:17:52.384 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:52.384 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:52.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:52.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:52.824 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:17:53.302 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:17:53.384 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:53.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:53.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:53.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:53.779 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:17:54.257 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:17:54.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:54.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:54.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:54.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:54.735 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:17:55.213 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:17:55.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:55.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:55.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:55.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:55.690 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:17:56.168 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:17:56.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:56.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:56.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:56.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:56.646 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:17:57.125 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:17:57.602 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:17:58.080 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:17:58.558 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:17:59.035 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:17:59.513 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:17:59.965 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:17:59.965 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:17:59.968 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:17:59.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:17:59.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:17:59.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:17:59.969 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:17:59.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:17:59.969 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:17:59.969 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:17:59.969 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:17:59.969 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:17:59.969 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:18:04.975 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:18:04.976 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:18:04.976 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:04.976 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:04.976 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:04.976 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:04.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:04.983 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:18:04.983 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:04.983 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:18:04.984 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:18:04.985 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:18:04.985 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:18:04.986 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:18:04.986 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:04.986 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:04.986 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:18:04.986 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:18:04.986 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:18:04.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:04.987 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:18:04.987 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:18:04.987 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:18:04.987 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:04.987 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:04.988 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:18:04.988 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:18:04.988 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:18:04.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:04.989 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:18:04.989 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:18:04.989 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:18:04.989 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:04.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:04.989 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:18:04.989 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:18:04.989 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:18:04.990 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:04.992 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:18:04.992 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:18:04.992 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:18:04.993 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:18:04.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:04.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:04.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:04.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:18:04.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:04.994 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:18:04.994 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:18:04.994 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:18:09.998 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:18:09.998 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:18:09.999 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:10.001 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:10.002 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:10.002 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:10.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:10.010 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:18:10.010 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:10.010 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:18:10.010 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:18:10.011 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:18:10.012 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:18:10.012 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:18:10.012 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:10.012 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:10.013 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:18:10.013 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:18:10.013 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:18:10.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:10.013 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:18:10.014 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:18:10.014 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:18:10.014 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:10.014 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:10.014 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:18:10.014 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:18:10.014 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:18:10.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:10.015 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:18:10.015 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:18:10.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:18:10.016 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:10.016 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:10.016 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:18:10.016 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:18:10.016 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:18:10.016 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:10.018 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:18:10.018 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:18:10.018 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:18:10.019 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:10.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:10.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:10.023 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:18:10.507 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:18:10.547 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:18:10.549 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:18:10.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:18:10.551 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:18:10.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:18:10.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:18:10.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:18:10.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:18:10.554 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:18:10.554 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:18:10.554 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:18:10.554 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:18:10.985 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:18:11.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:11.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:11.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:11.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:11.462 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:18:11.940 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:18:12.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:12.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:12.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:12.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:12.418 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:18:12.896 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:18:13.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:13.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:13.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:13.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:13.374 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:18:13.851 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:18:14.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:14.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:14.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:14.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:14.329 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:18:14.807 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:18:15.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:15.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:15.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:15.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:15.285 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:18:15.762 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:18:16.240 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:18:16.718 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:18:17.196 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:18:17.673 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:18:18.151 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:18:18.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:18:18.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:18:18.608 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:18.608 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:18.608 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:18.609 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:18.612 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:18.612 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:18.612 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:18.612 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:18:18.612 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:18:18.613 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:18:18.613 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:18.613 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:18:18.613 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:18:18.613 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:18:18.613 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:18:18.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:18:18.614 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:18:23.610 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:18:23.611 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:18:23.612 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:23.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:23.614 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:23.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:23.623 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:23.624 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:18:23.624 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:23.625 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:18:23.625 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:18:23.628 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:18:23.628 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:18:23.629 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:18:23.629 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:23.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:23.630 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:18:23.630 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:18:23.630 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:18:23.631 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:23.631 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:18:23.631 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:18:23.631 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:18:23.631 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:23.632 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:23.632 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:18:23.632 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:18:23.632 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:18:23.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:23.633 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:18:23.633 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:18:23.633 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:18:23.634 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:23.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:23.634 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:18:23.634 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:18:23.634 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:18:23.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:23.636 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:18:23.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:18:23.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:18:23.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:18:23.637 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:18:23.637 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:18:23.637 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:23.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:23.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:18:23.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:23.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:23.639 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:18:23.639 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:18:23.639 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:18:28.641 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:18:28.658 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:18:28.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:28.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:28.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:28.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:28.662 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:28.664 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:18:28.664 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:28.665 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:18:28.665 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:18:28.670 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:18:28.670 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:18:28.671 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:18:28.671 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:28.671 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:28.672 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:18:28.672 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:18:28.673 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:18:28.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:28.674 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:18:28.674 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:18:28.674 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:18:28.675 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:28.675 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:28.675 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:18:28.676 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:18:28.676 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:18:28.676 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:28.677 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:18:28.677 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:18:28.677 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:18:28.677 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:28.677 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:28.677 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:18:28.677 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:18:28.677 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:18:28.677 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:28.680 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:18:28.680 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:28.681 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:18:28.681 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:18:28.681 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:18:28.681 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:28.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:28.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:28.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:28.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:28.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:28.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:28.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:28.686 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:18:29.169 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:18:29.214 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:18:29.216 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:18:29.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:18:29.218 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:18:29.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:18:29.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:18:29.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:18:29.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:18:29.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:18:29.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:18:29.221 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:18:29.221 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:18:29.647 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:18:29.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:29.685 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:29.686 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:29.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:30.124 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:18:30.601 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:18:30.685 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:30.686 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:30.686 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:30.690 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:31.080 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:18:31.557 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:18:31.686 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:31.686 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:31.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:31.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:32.035 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:18:32.512 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:18:32.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:32.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:32.687 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:32.692 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:32.990 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:18:33.468 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:18:33.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:33.688 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:33.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:33.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:33.946 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:18:34.424 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:18:34.902 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:18:35.380 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:18:35.857 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:18:36.335 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:18:36.813 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:18:37.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:18:37.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:18:37.267 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:37.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:37.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:37.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:37.268 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:37.268 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:37.268 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:37.268 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:37.268 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:18:37.268 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:18:37.268 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:18:42.270 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:18:42.270 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:18:42.271 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:42.273 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:42.274 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:42.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:42.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:42.287 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:18:42.287 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:42.287 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:18:42.287 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:18:42.289 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:18:42.290 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:18:42.290 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:18:42.290 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:42.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:42.290 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:18:42.291 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:18:42.291 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:18:42.291 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:42.292 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:18:42.292 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:18:42.292 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:18:42.292 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:42.292 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:42.292 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:18:42.292 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:18:42.292 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:18:42.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:42.294 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:18:42.294 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:18:42.294 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:18:42.294 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:42.294 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:42.294 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:18:42.294 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:18:42.294 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:18:42.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:18:42.296 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:18:42.296 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:18:42.296 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:42.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:42.297 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:42.298 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:42.298 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:42.298 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:18:42.298 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:18:42.298 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:18:47.301 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:18:47.302 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:18:47.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:47.305 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:47.306 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:47.306 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:47.319 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:47.321 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:18:47.321 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:47.322 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:18:47.322 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:18:47.328 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:18:47.329 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:18:47.329 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:18:47.329 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:47.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:47.330 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:18:47.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:18:47.331 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:18:47.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:47.333 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:18:47.333 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:18:47.334 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:18:47.334 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:47.334 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:47.334 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:18:47.335 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:18:47.335 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:18:47.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:47.336 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:18:47.336 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:18:47.336 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:18:47.336 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:18:47.336 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:47.337 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:18:47.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:18:47.337 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:18:47.337 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:47.340 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:18:47.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:47.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:47.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:47.342 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:18:47.342 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:18:47.342 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:18:47.342 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:18:47.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:47.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:47.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:47.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:18:47.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:47.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:47.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:47.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:47.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:47.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:18:47.347 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:18:47.832 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:18:47.879 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:18:47.881 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:18:47.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:18:47.883 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:18:47.886 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:18:47.886 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:18:47.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:18:47.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:18:47.887 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:18:47.887 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:18:47.887 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:18:47.887 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:18:48.309 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:18:48.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:48.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:48.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:48.351 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:48.786 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:18:49.264 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:18:49.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:49.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:49.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:49.352 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:49.741 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:18:50.219 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:18:50.347 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:50.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:50.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:50.353 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:50.697 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:18:51.175 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:18:51.349 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:51.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:51.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:51.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:51.652 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:18:52.130 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:18:52.350 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:52.351 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:52.352 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:52.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:52.607 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:18:53.084 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:18:53.561 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:18:54.038 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:18:54.516 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:18:54.993 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:18:55.467 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:18:55.925 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:18:55.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:18:55.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:18:55.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:18:55.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:18:55.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:18:55.932 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:18:55.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:18:55.932 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:18:55.932 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:18:55.932 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:18:55.932 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:18:55.932 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:18:55.932 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:18:55.932 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:18:55.932 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:18:55.933 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:18:55.933 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:18:55.933 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:00.933 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:19:00.934 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:19:00.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:00.937 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:00.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:00.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:00.947 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:00.949 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:19:00.949 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:00.950 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:19:00.950 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:19:00.954 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:19:00.954 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:19:00.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:19:00.955 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:00.955 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:00.955 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:19:00.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:19:00.955 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:19:00.955 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:00.958 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:19:00.958 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:19:00.958 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:19:00.958 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:00.958 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:00.958 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:19:00.958 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:19:00.958 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:19:00.959 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:00.960 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:19:00.961 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:19:00.961 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:19:00.961 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:00.961 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:00.961 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:19:00.961 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:19:00.961 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:19:00.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:00.964 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:19:00.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:19:00.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:19:00.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:19:00.964 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:19:00.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:19:00.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:19:00.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:19:00.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:19:00.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:00.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:00.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:19:00.965 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:19:00.965 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:19:00.965 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:19:00.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:00.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:00.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:00.967 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:19:00.967 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:19:00.967 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:19:05.970 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:19:05.970 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:19:05.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:05.974 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:05.974 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:05.974 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:05.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:05.985 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:19:05.985 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:05.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:19:05.986 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:19:05.990 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:19:05.990 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:19:05.991 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:19:05.991 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:05.991 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:05.992 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:19:05.992 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:19:05.992 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:19:05.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:05.993 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:19:05.993 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:19:05.994 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:19:05.994 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:05.994 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:05.994 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:19:05.995 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:19:05.995 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:19:05.995 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:05.996 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:19:05.996 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:19:05.996 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:19:05.996 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:05.997 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:05.997 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:19:05.997 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:19:05.997 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:19:05.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:06.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:19:06.001 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:19:06.001 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:19:06.001 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:06.001 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:06.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:06.006 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:19:06.489 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:19:06.530 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:19:06.532 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:19:06.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:19:06.534 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:19:06.537 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:19:06.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:19:06.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:19:06.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:19:06.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:19:06.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:19:06.539 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:19:06.539 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:19:06.967 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:19:07.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:07.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:07.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:07.009 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:07.444 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:19:07.922 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:19:08.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:08.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:08.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:08.009 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:08.400 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:19:08.878 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:19:09.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:09.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:09.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:09.011 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:09.355 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:19:09.832 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:19:10.008 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:10.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:10.008 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:10.012 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:10.310 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:19:10.788 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:19:11.009 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:11.009 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:11.010 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:11.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:11.266 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:19:11.743 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:19:12.221 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:19:12.698 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:19:13.176 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:19:13.654 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:19:14.132 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:19:14.610 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:19:15.088 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:19:15.565 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:19:16.043 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:19:16.521 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:19:16.998 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:19:17.476 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:19:17.953 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:19:18.431 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:19:18.909 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:19:19.386 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:19:19.864 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:19:20.342 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:19:20.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:19:20.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:19:20.584 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=3114 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:20.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:20.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:20.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:20.591 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:20.591 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:20.591 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:20.592 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:19:20.592 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:19:20.592 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:19:20.592 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:20.592 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3115 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.592 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.592 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.592 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.593 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.593 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.593 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.593 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.593 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.593 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.593 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.593 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.593 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.593 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.593 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:20.594 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:25.591 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:19:25.592 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:19:25.593 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:25.595 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:25.595 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:25.596 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:25.603 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:25.605 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:19:25.605 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:25.605 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:19:25.606 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:19:25.609 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:19:25.609 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:19:25.610 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:19:25.610 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:25.610 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:25.611 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:19:25.611 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:19:25.611 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:19:25.611 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:25.612 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:19:25.612 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:19:25.612 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:19:25.612 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:25.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:25.613 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:19:25.613 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:19:25.613 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:19:25.613 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:25.614 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:19:25.614 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:19:25.615 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:19:25.615 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:25.615 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:25.615 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:19:25.615 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:19:25.615 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:19:25.615 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:25.617 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:25.618 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:19:25.618 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:19:25.618 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:19:25.618 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:19:25.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:25.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:25.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:25.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:19:25.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:25.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:25.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:25.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:25.620 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:19:25.620 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:19:25.620 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:19:30.626 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:19:30.626 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:19:30.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:30.626 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:30.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:30.626 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:30.633 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:30.633 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:19:30.633 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:30.634 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:19:30.634 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:19:30.637 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:19:30.637 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:19:30.638 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:19:30.638 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:30.638 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:30.639 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:19:30.639 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:19:30.639 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:19:30.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:30.643 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:19:30.643 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:19:30.643 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:19:30.643 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:30.644 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:30.644 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:19:30.644 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:19:30.644 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:19:30.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:30.646 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:19:30.646 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:19:30.646 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:19:30.646 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:30.647 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:30.647 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:19:30.647 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:19:30.647 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:19:30.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:30.650 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:19:30.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:19:30.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:19:30.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:19:30.650 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:19:30.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:19:30.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:19:30.651 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:19:30.651 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:19:30.651 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:30.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:30.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:30.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:30.656 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:19:31.140 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:19:31.169 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:19:31.170 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:19:31.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:19:31.171 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:19:31.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:19:31.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:19:31.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:19:31.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:19:31.174 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:19:31.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:19:31.175 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:19:31.175 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:19:31.617 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:19:31.654 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:31.655 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:31.655 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:31.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:32.095 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:19:32.572 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:19:32.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:32.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:32.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:32.660 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:33.050 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:19:33.529 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:19:33.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:33.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:33.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:33.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:34.006 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:19:34.485 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:19:34.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:34.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:34.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:34.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:34.962 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:19:35.440 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:19:35.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:35.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:35.659 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:35.662 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:35.918 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:19:36.395 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:19:36.874 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:19:37.351 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:19:37.826 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:19:38.304 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:19:38.781 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:19:39.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:19:39.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:19:39.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:39.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:39.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:39.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:39.195 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:39.195 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:39.195 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:39.195 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:19:39.196 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:19:39.196 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:19:39.196 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:39.196 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:39.196 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:39.196 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:39.196 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:39.197 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:39.197 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:39.197 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:39.197 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:44.198 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:19:44.198 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:19:44.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:44.198 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:44.198 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:44.198 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:44.207 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:44.209 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:19:44.209 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:44.210 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:19:44.210 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:19:44.214 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:19:44.214 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:19:44.214 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:19:44.214 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:44.214 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:44.215 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:19:44.215 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:19:44.215 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:19:44.215 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:44.217 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:19:44.218 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:19:44.218 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:19:44.219 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:44.219 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:44.219 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:19:44.220 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:19:44.220 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:19:44.220 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:44.221 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:19:44.221 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:19:44.221 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:19:44.221 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:44.222 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:44.222 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:19:44.222 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:19:44.222 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:19:44.222 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:44.224 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:19:44.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:19:44.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:19:44.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:19:44.224 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:44.225 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:19:44.225 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:19:44.225 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:19:44.225 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:44.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:44.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:44.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:44.228 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:44.228 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:44.228 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:19:44.228 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:19:44.228 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:19:49.231 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:19:49.232 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:19:49.233 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:49.235 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:49.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:49.236 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:49.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:49.246 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:19:49.246 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:49.247 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:19:49.247 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:19:49.252 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:19:49.252 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:19:49.253 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:19:49.253 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:49.253 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:49.254 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:19:49.254 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:19:49.254 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:19:49.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:49.255 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:19:49.256 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:19:49.256 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:19:49.256 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:49.256 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:49.256 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:19:49.256 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:19:49.256 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:19:49.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:49.258 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:19:49.258 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:19:49.258 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:19:49.258 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:19:49.258 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:49.258 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:19:49.258 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:19:49.258 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:19:49.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:49.261 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:19:49.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:19:49.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:19:49.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:19:49.261 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:19:49.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:19:49.262 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:19:49.262 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:19:49.262 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:49.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:49.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:19:49.267 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:19:49.748 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:19:49.788 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:19:49.789 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:19:49.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:19:49.790 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:19:49.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:19:49.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:19:49.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:19:49.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:19:49.791 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:19:49.791 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:19:49.792 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:19:49.792 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:19:50.226 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:19:50.265 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:50.266 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:50.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:50.271 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:50.704 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:19:51.181 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:19:51.266 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:51.266 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:51.268 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:51.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:51.660 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:19:52.138 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:19:52.267 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:52.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:52.268 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:52.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:52.615 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:19:53.093 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:19:53.268 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:53.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:53.269 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:53.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:53.570 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:19:54.048 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:19:54.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:54.270 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:54.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:54.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:54.526 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:19:55.004 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:19:55.481 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:19:55.959 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:19:56.437 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:19:56.914 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:19:57.392 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:19:57.870 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:19:58.347 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:19:58.825 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:19:59.302 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:19:59.780 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:19:59.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:19:59.845 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:19:59.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:19:59.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:19:59.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:19:59.850 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:19:59.853 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:19:59.853 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:19:59.853 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:19:59.853 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:19:59.853 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:19:59.854 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:19:59.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:19:59.854 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:59.854 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:59.854 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:59.854 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:59.855 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:59.855 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:59.855 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:59.855 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:19:59.855 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2262 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:20:04.854 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:20:04.854 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:20:04.855 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:04.857 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:04.858 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:04.858 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:04.867 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:04.868 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:20:04.869 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:04.869 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:20:04.869 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:20:04.871 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:20:04.871 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:20:04.872 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:20:04.872 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:04.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:04.872 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:20:04.872 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:20:04.872 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:20:04.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:04.875 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:20:04.875 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:20:04.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:20:04.875 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:04.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:04.875 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:20:04.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:20:04.875 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:20:04.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:04.878 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:20:04.878 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:20:04.878 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:20:04.878 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:04.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:04.878 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:20:04.878 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:20:04.878 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:20:04.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:04.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:04.883 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:04.883 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:20:04.883 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:20:04.883 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:20:04.883 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:20:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:04.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:20:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:04.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:04.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:04.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:04.885 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:20:04.885 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:20:04.885 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:20:09.889 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:20:09.889 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:20:09.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:09.892 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:09.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:09.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:09.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:09.903 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:20:09.903 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:09.903 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:20:09.904 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:20:09.908 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:20:09.908 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:20:09.909 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:20:09.909 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:09.909 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:09.909 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:20:09.910 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:20:09.910 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:20:09.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:09.913 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:20:09.913 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:20:09.913 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:20:09.913 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:09.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:09.913 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:20:09.913 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:20:09.913 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:20:09.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:09.916 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:20:09.916 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:20:09.916 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:20:09.916 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:09.916 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:20:09.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:09.916 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:20:09.916 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:20:09.916 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:09.919 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:20:09.919 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:20:09.919 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:20:09.919 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:20:09.919 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:20:09.920 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:20:09.920 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:20:09.920 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:09.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:09.925 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:20:10.409 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:20:10.445 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:20:10.446 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:20:10.447 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:20:10.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:20:10.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:20:10.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:20:10.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:20:10.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:20:10.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:20:10.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:20:10.452 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:20:10.452 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:20:10.886 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:20:10.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:10.923 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:10.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:10.927 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:11.364 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:20:11.841 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:20:11.924 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:11.924 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:11.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:11.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:12.319 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:20:12.797 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:20:12.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:12.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:12.925 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:12.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:13.275 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:20:13.752 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:20:13.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:13.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:13.925 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:13.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:14.227 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:20:14.705 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:20:14.927 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:14.927 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:14.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:14.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:15.183 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:20:15.661 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:20:16.139 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:20:16.617 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:20:17.095 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:20:17.572 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:20:18.050 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:20:18.528 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:20:19.006 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:20:19.484 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:20:19.962 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:20:20.440 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:20:20.917 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:20:21.394 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:20:21.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:20:21.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:20:21.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:21.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:21.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:21.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:21.511 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:21.511 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:21.511 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:21.511 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:21.511 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:20:21.511 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:20:21.511 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:20:21.511 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2475 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:20:21.511 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2475 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:20:21.511 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2475 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:20:21.511 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2475 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:20:21.511 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2475 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:20:21.511 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2475 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:20:26.511 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:20:26.511 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:20:26.512 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:26.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:26.515 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:26.515 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:26.523 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:26.525 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:20:26.525 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:26.525 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:20:26.525 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:20:26.528 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:20:26.529 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:20:26.529 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:20:26.529 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:26.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:26.530 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:20:26.530 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:20:26.530 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:20:26.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:26.532 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:20:26.532 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:20:26.532 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:20:26.532 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:26.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:26.532 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:20:26.533 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:20:26.533 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:20:26.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:26.534 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:20:26.534 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:20:26.534 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:20:26.534 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:26.534 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:26.534 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:20:26.534 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:20:26.534 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:20:26.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:26.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:26.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:26.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:26.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:26.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:26.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:26.538 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:20:26.538 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:20:26.538 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:20:26.538 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:20:26.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:26.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:26.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:26.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:26.539 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:26.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:26.540 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:26.540 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:26.540 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:20:26.540 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:20:26.540 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:20:31.543 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:20:31.543 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:20:31.544 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:31.545 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:31.545 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:31.546 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:31.555 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:31.556 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:20:31.557 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:31.557 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:20:31.557 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:20:31.560 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:20:31.560 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:20:31.560 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:20:31.561 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:31.561 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:31.561 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:20:31.562 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:20:31.562 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:20:31.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:31.562 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:20:31.563 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:20:31.563 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:20:31.563 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:31.563 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:31.563 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:20:31.563 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:20:31.563 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:20:31.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:31.565 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:20:31.565 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:20:31.565 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:20:31.565 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:31.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:31.565 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:20:31.565 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:20:31.565 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:20:31.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:31.568 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:20:31.568 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:20:31.569 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:20:31.569 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:31.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:31.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:31.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:31.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:31.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:31.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:31.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:31.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:31.573 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:20:32.058 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:20:32.091 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:20:32.092 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:20:32.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:20:32.094 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:20:32.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:20:32.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:20:32.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:20:32.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:20:32.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:20:32.095 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:20:32.095 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:20:32.095 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:20:32.535 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:20:32.572 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:32.573 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:32.573 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:32.576 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:33.013 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:20:33.491 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:20:33.573 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:33.573 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:33.574 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:33.577 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:33.969 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:20:34.446 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:20:34.574 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:34.574 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:34.574 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:34.578 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:34.924 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:20:35.402 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:20:35.574 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:35.575 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:35.575 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:35.579 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:35.880 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:20:36.357 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:20:36.575 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:36.575 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:36.576 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:36.580 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:36.835 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:20:37.313 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:20:37.792 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:20:38.270 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:20:38.747 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:20:39.224 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:20:39.702 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:20:40.179 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:20:40.657 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:20:41.135 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:20:41.613 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:20:42.091 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:20:42.568 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:20:43.046 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:20:43.523 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:20:43.998 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:20:44.471 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:20:44.949 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:20:45.427 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:20:45.905 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:20:46.382 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:20:46.861 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:20:47.338 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:20:47.816 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:20:48.294 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:20:48.772 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:20:49.249 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:20:49.727 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:20:50.205 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:20:50.683 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:20:51.160 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:20:51.638 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:20:52.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:20:52.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:20:52.116 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:20:52.116 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:52.116 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:52.116 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:52.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:52.117 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:52.117 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:52.117 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:52.117 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:20:52.117 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:20:52.117 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:20:52.117 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:57.120 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:20:57.120 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:20:57.121 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:57.122 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:57.123 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:57.123 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:57.133 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:57.134 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:20:57.134 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:57.135 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:20:57.135 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:20:57.138 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:20:57.138 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:20:57.139 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:20:57.139 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:57.139 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:57.140 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:20:57.140 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:20:57.140 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:20:57.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:20:57.141 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:20:57.141 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:20:57.141 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:20:57.141 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:57.142 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:57.142 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:20:57.142 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:20:57.142 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:20:57.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:20:57.144 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:20:57.144 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:20:57.144 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:20:57.144 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:20:57.144 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:57.144 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:20:57.144 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:20:57.144 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:20:57.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:20:57.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:57.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:57.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:57.148 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:20:57.148 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:20:57.148 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:20:57.148 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:20:57.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:57.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:57.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:57.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:57.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:57.150 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:20:57.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:20:57.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:20:57.150 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:20:57.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:20:57.150 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:20:57.150 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:20:57.150 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:21:02.152 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:21:02.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:21:02.154 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:02.155 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:02.155 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:02.155 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:02.162 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:02.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:21:02.162 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:02.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:21:02.162 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:21:02.164 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:21:02.165 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:21:02.165 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:21:02.165 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:02.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:02.166 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:21:02.166 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:21:02.166 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:21:02.167 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:02.167 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:21:02.168 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:21:02.168 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:21:02.168 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:02.168 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:02.169 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:21:02.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:21:02.169 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:21:02.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:02.170 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:21:02.170 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:21:02.170 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:21:02.170 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:02.170 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:02.171 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:21:02.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:21:02.171 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:21:02.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:02.173 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:21:02.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:02.174 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:21:02.174 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:21:02.174 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:21:02.174 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:02.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:02.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:02.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:02.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:02.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:02.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:02.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:02.179 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:21:02.664 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:21:02.708 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:21:02.710 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:21:02.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:21:02.712 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:21:03.144 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:21:03.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:03.180 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:03.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:03.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:03.625 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:21:04.106 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:21:04.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:04.181 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:04.182 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:04.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:04.586 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:21:05.063 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:21:05.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:05.182 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:05.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:05.188 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:05.542 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:21:06.020 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:21:06.182 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:06.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:06.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:06.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:06.502 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:21:06.983 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:21:07.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:07.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:07.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:07.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:07.464 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:21:07.946 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:21:08.426 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:21:08.908 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:21:09.390 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:21:09.871 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:21:10.352 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:21:10.834 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:21:11.313 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:21:11.790 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:21:12.269 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:21:12.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:12.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:12.722 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:12.722 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:12.725 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:12.725 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:12.725 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:12.725 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:12.725 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:21:12.725 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:21:12.725 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:21:12.725 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2242 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:12.725 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2242 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:12.725 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2242 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:12.725 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2242 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:12.725 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2242 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:12.725 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2242 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:12.725 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2242 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:17.725 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:21:17.726 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:21:17.727 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:17.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:17.729 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:17.730 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:17.736 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:17.737 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:21:17.737 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:17.737 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:21:17.737 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:21:17.739 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:21:17.739 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:21:17.739 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:21:17.740 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:17.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:17.740 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:21:17.741 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:21:17.741 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:21:17.741 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:17.741 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:21:17.741 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:21:17.741 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:21:17.741 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:17.742 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:17.742 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:21:17.742 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:21:17.742 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:21:17.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:17.743 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:21:17.743 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:21:17.744 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:21:17.744 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:17.744 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:17.744 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:21:17.744 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:21:17.744 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:21:17.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:17.746 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:21:17.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:21:17.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:21:17.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:21:17.746 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:21:17.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:21:17.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:21:17.747 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:21:17.747 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:21:17.747 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:21:17.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:17.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:17.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:17.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:17.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:17.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:17.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:17.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:17.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:17.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:17.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:17.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:17.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:17.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:17.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:17.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:17.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:17.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:17.749 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:17.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:17.749 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:17.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:17.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:17.749 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:17.749 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:21:17.749 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:21:17.749 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:21:22.751 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:21:22.752 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:21:22.753 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:22.754 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:22.756 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:22.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:22.762 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:22.763 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:21:22.763 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:22.763 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:21:22.763 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:21:22.765 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:21:22.766 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:21:22.766 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:21:22.766 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:22.767 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:22.767 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:21:22.767 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:21:22.767 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:21:22.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:22.768 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:21:22.768 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:21:22.768 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:21:22.768 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:22.768 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:22.769 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:21:22.769 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:21:22.769 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:21:22.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:22.770 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:21:22.770 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:21:22.770 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:21:22.770 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:22.771 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:22.771 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:21:22.771 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:21:22.771 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:21:22.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:21:22.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:21:22.774 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:21:22.774 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:21:22.774 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:22.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:22.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:22.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:22.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:22.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:22.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:22.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:22.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:22.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:22.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:22.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:22.779 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:21:23.262 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:21:23.306 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:21:23.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:21:23.309 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:21:23.312 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:21:23.739 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:21:23.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:23.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:23.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:23.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:24.216 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:21:24.694 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:21:24.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:24.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:24.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:24.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:25.175 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:21:25.656 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:21:25.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:25.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:25.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:25.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:26.136 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:21:26.618 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:21:26.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:26.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:26.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:26.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:27.099 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:21:27.578 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:21:27.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:27.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:27.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:27.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:28.060 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:21:28.542 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:21:29.023 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:21:29.504 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:21:29.982 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:21:30.451 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:21:30.920 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:21:31.402 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:21:31.883 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:21:32.365 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:21:32.846 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:21:33.328 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:21:33.809 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:21:34.290 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:21:34.770 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:21:35.252 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:21:35.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:35.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:35.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:35.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:35.328 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:35.328 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:35.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:35.328 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:35.328 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:21:35.328 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:21:35.328 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:21:35.328 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2670 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:35.328 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2670 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:35.328 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2670 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:35.328 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2670 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:35.328 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2670 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:35.328 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2670 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:35.328 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2670 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:40.331 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:21:40.331 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:21:40.332 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:40.333 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:40.333 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:40.334 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:40.341 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:40.342 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:21:40.342 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:40.342 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:21:40.342 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:21:40.344 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:21:40.344 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:21:40.345 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:21:40.345 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:40.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:40.345 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:21:40.345 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:21:40.345 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:21:40.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:40.347 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:21:40.347 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:21:40.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:21:40.347 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:40.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:40.347 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:21:40.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:21:40.347 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:21:40.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:40.348 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:21:40.348 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:21:40.348 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:21:40.348 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:40.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:40.348 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:21:40.348 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:21:40.348 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:21:40.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:40.349 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:21:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:21:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:21:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:21:40.349 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:21:40.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:21:40.350 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:21:40.350 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:21:40.350 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:40.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:40.351 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:21:40.351 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:21:40.351 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:21:45.355 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:21:45.355 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:21:45.356 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:45.358 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:45.359 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:45.359 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:45.368 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:45.369 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:21:45.370 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:45.370 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:21:45.370 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:21:45.373 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:21:45.373 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:21:45.374 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:21:45.374 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:45.374 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:45.374 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:21:45.374 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:21:45.374 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:21:45.375 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:45.376 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:21:45.376 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:21:45.376 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:21:45.376 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:45.377 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:45.377 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:21:45.377 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:21:45.377 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:21:45.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:45.379 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:21:45.379 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:21:45.379 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:21:45.379 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:45.379 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:45.379 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:21:45.379 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:21:45.379 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:21:45.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:45.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:21:45.383 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:21:45.383 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:21:45.383 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:45.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:45.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:45.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:45.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:45.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:45.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:45.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:45.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:45.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:45.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:45.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:45.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:45.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:45.388 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:21:45.872 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:21:45.910 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:21:45.911 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:21:45.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:21:45.913 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:21:45.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:21:45.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:21:45.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:21:45.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:21:45.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:21:45.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:21:45.916 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:21:45.916 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:21:45.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:21:45.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:21:45.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:21:45.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:21:46.349 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:21:46.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:46.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:46.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:46.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:46.827 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:21:47.305 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:21:47.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:47.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:47.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:47.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:47.783 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:21:48.260 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:21:48.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:48.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:48.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:48.392 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:48.738 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:21:49.216 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:21:49.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:49.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:49.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:49.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:49.694 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:21:50.171 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:21:50.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:50.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:50.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:50.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:50.649 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:21:51.127 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:21:51.605 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:21:52.083 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:21:52.561 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:21:53.038 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:21:53.515 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:21:53.966 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:21:53.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:21:53.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:53.969 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:53.969 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:53.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:53.969 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:53.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:53.969 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:53.969 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:53.969 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:21:53.969 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:21:53.969 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:21:53.970 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:53.970 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:53.970 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:53.970 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:53.970 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:53.970 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:53.970 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:21:58.972 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:21:58.973 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:21:58.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:58.977 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:58.977 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:58.977 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:58.985 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:58.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:21:58.986 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:58.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:21:58.986 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:21:58.988 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:21:58.989 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:21:58.989 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:21:58.989 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:58.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:58.990 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:21:58.990 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:21:58.990 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:21:58.990 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:21:58.991 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:21:58.991 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:21:58.991 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:21:58.991 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:58.991 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:58.991 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:21:58.991 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:21:58.992 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:21:58.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:21:58.993 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:21:58.993 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:21:58.994 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:21:58.994 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:21:58.994 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:58.994 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:21:58.994 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:21:58.994 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:21:58.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:58.997 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:21:58.997 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:21:58.997 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:21:58.997 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:21:58.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:58.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:58.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:58.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:21:58.999 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:21:58.999 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:21:58.999 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:22:04.002 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:22:04.003 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:22:04.004 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:04.006 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:04.007 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:04.007 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:04.015 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:04.016 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:04.016 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:04.017 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:04.017 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:22:04.019 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:22:04.020 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:22:04.020 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:04.020 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:04.021 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:04.021 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:22:04.021 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:04.021 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:22:04.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:04.023 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:22:04.023 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:22:04.023 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:04.023 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:04.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:04.023 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:22:04.023 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:04.023 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:22:04.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:04.026 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:22:04.026 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:22:04.026 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:04.026 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:04.026 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:04.026 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:22:04.026 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:04.026 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:22:04.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:04.029 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:04.030 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:22:04.030 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:22:04.030 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:22:04.031 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:22:04.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:04.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:04.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:04.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:22:04.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:04.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:04.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:04.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:04.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:04.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:04.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:04.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:04.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:04.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:04.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:04.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:04.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:04.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:04.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:04.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:04.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:04.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:04.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:04.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:04.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:04.035 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:22:04.520 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:22:04.563 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:22:04.565 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:22:04.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:22:04.567 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:22:04.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:22:04.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:22:04.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:22:04.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:22:04.570 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:22:04.570 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:22:04.570 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:22:04.570 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:22:04.610 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:22:04.610 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:22:04.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:22:04.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:22:04.997 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:22:05.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:05.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:05.037 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:05.041 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:05.474 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:22:05.952 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:22:06.035 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:06.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:06.038 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:06.042 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:06.430 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:22:06.908 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:22:07.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:07.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:07.039 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:07.043 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:07.386 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:22:07.863 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:22:08.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:08.037 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:08.041 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:08.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:08.340 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:22:08.817 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:22:09.038 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:09.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:09.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:09.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:09.295 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:22:09.773 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:22:10.250 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:22:10.728 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:22:11.206 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:22:11.683 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:22:12.161 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:22:12.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:22:12.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:22:12.618 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:12.618 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:12.618 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:12.618 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:12.618 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:12.618 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:12.618 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:12.618 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:12.618 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:22:12.618 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:22:12.618 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:22:12.618 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:12.618 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:12.618 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:12.619 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:12.619 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:12.619 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:12.619 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:12.619 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:17.622 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:22:17.622 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:22:17.623 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:17.625 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:17.625 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:17.626 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:17.633 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:17.633 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:17.633 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:17.633 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:17.633 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:22:17.634 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:22:17.634 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:22:17.634 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:17.634 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:17.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:17.634 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:22:17.634 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:17.634 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:22:17.634 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:17.636 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:22:17.636 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:22:17.636 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:17.636 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:17.636 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:17.636 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:22:17.637 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:17.637 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:22:17.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:17.638 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:22:17.638 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:22:17.638 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:17.638 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:17.638 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:17.638 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:22:17.638 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:17.638 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:22:17.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:17.641 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:22:17.641 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:22:17.641 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:22:17.642 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:22:17.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:17.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:17.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:17.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:17.643 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:22:17.643 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:22:17.643 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:22:22.645 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:22:22.646 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:22:22.649 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:22.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:22.649 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:22.649 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:22.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:22.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:22.661 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:22.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:22.661 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:22:22.666 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:22:22.666 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:22:22.666 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:22.667 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:22.667 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:22.667 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:22:22.667 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:22.667 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:22:22.667 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:22.670 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:22:22.670 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:22:22.670 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:22.670 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:22.670 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:22.670 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:22:22.670 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:22.670 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:22:22.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:22.673 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:22:22.673 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:22:22.673 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:22.673 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:22.673 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:22.673 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:22:22.673 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:22.673 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:22:22.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:22.676 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:22:22.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:22:22.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:22:22.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:22:22.676 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:22:22.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:22:22.677 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:22:22.677 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:22:22.677 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:22:22.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:22.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:22.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:22.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:22.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:22.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:22.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:22.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:22.682 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:22:23.166 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:22:23.203 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:22:23.204 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:22:23.205 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:22:23.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:22:23.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:22:23.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:22:23.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:22:23.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:22:23.208 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:22:23.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:22:23.209 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:22:23.209 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:22:23.255 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:22:23.256 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:22:23.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:22:23.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:22:23.643 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:22:23.680 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:23.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:23.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:23.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:24.121 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:22:24.599 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:22:24.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:24.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:24.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:24.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:25.077 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:22:25.555 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:22:25.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:25.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:25.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:25.690 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:26.033 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:22:26.510 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:22:26.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:26.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:26.686 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:26.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:26.988 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:22:27.466 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:22:27.685 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:27.685 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:27.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:27.692 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:27.943 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:22:28.421 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:22:28.898 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:22:29.376 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:22:29.854 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:22:30.332 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:22:30.809 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:22:31.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:22:31.260 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:22:31.264 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:31.264 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:31.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:31.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:31.266 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:31.266 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:31.266 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:31.267 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:31.267 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:22:31.267 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:22:31.267 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:31.267 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:36.271 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:22:36.271 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:22:36.271 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:36.271 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:36.271 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:36.271 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:36.279 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:36.281 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:36.281 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:36.281 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:36.282 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:22:36.287 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:22:36.288 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:22:36.288 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:36.288 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:36.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:36.288 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:22:36.289 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:36.289 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:22:36.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:36.292 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:22:36.292 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:22:36.292 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:36.292 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:36.292 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:36.292 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:22:36.292 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:36.292 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:22:36.293 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:36.295 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:22:36.295 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:22:36.295 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:36.295 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:36.295 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:36.295 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:22:36.296 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:36.296 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:22:36.296 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:36.299 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:22:36.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:22:36.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:22:36.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:22:36.299 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:22:36.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:22:36.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:22:36.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:22:36.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:22:36.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:36.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:36.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:36.299 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:22:36.300 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:22:36.300 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:22:36.300 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:36.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:36.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:36.302 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:22:36.302 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:22:36.302 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:22:41.306 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:22:41.306 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:22:41.310 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:41.310 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:41.310 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:41.310 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:41.316 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:41.316 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:41.316 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:41.317 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:41.317 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:22:41.317 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:22:41.317 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:22:41.317 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:41.317 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:41.318 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:41.318 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:22:41.318 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:41.318 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:22:41.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:41.318 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:22:41.318 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:22:41.318 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:41.318 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:41.318 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:41.318 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:22:41.318 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:41.318 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:22:41.318 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:41.319 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:22:41.319 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:22:41.319 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:41.319 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:41.319 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:41.319 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:22:41.319 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:41.319 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:22:41.319 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:41.320 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:22:41.320 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:22:41.320 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:22:41.321 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:41.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:41.325 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:22:41.809 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:22:41.845 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:22:41.846 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:22:41.848 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:22:41.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:22:41.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:22:41.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:22:41.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:22:41.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:22:41.852 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:22:41.852 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:22:41.852 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:22:41.852 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:22:41.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:22:41.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:22:41.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:22:41.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:22:42.286 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:22:42.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:42.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:42.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:42.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:42.764 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:22:43.242 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:22:43.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:43.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:43.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:43.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:43.719 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:22:44.197 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:22:44.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:44.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:44.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:44.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:44.675 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:22:45.153 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:22:45.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:45.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:45.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:45.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:45.631 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:22:46.109 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:22:46.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:46.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:46.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:46.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:46.586 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:22:47.064 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:22:47.542 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:22:48.020 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:22:48.498 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:22:48.976 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:22:49.453 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:22:49.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:22:49.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:22:49.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:49.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:49.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:49.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:49.911 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:49.911 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:49.912 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:49.912 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:49.912 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:22:49.912 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:22:49.912 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:22:49.912 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:49.912 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:49.912 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:49.912 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:49.912 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:49.912 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:22:54.911 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:22:54.911 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:22:54.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:54.914 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:54.914 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:54.915 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:54.919 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:54.920 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:54.920 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:54.920 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:54.920 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:22:54.924 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:22:54.924 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:22:54.924 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:54.924 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:54.924 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:54.925 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:22:54.925 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:54.925 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:22:54.925 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:54.926 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:22:54.926 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:22:54.927 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:54.927 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:54.927 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:54.927 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:22:54.927 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:54.927 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:22:54.927 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:54.928 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:22:54.929 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:22:54.929 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:54.929 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:54.929 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:54.929 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:22:54.929 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:54.929 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:22:54.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:54.932 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:22:54.932 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:22:54.932 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:22:54.932 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:22:54.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:54.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:54.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:54.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:54.934 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:22:54.934 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:22:54.934 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:22:59.937 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:22:59.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:22:59.941 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:59.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:59.941 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:59.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:59.949 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:22:59.950 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:59.950 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:59.951 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:22:59.951 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:22:59.953 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:22:59.954 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:22:59.954 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:59.954 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:59.955 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:22:59.955 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:22:59.956 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:22:59.956 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:22:59.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:22:59.956 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:22:59.957 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:22:59.957 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:59.957 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:59.957 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:22:59.958 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:22:59.958 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:22:59.958 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:22:59.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:22:59.959 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:22:59.959 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:22:59.959 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:59.959 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:22:59.960 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:22:59.960 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:22:59.960 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:22:59.960 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:22:59.960 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:59.963 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:22:59.963 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:22:59.963 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:22:59.964 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:59.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:59.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:59.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:22:59.968 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:23:00.454 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:23:00.485 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:23:00.486 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:23:00.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:23:00.488 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:23:00.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:23:00.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:23:00.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:23:00.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:23:00.491 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:23:00.491 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:23:00.492 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:23:00.492 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:23:00.497 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:23:00.498 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:23:00.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:23:00.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:23:00.931 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:23:00.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:00.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:00.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:00.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:01.409 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:23:01.887 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:23:01.967 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:01.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:01.969 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:01.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:02.365 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:23:02.843 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:23:02.968 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:02.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:02.970 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:02.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:03.321 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:23:03.799 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:23:03.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:03.969 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:03.971 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:03.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:04.276 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:23:04.754 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:23:04.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:04.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:04.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:04.974 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:05.232 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:23:05.710 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:23:06.188 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:23:06.666 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:23:07.144 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:23:07.622 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:23:08.098 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:23:08.575 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:23:09.053 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:23:09.530 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:23:10.008 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:23:10.486 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:23:10.964 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:23:11.442 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:23:11.920 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:23:12.398 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:23:12.875 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:23:13.353 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:23:13.831 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:23:14.309 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:23:14.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:23:14.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:23:14.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:14.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:14.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:14.505 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:14.505 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:14.505 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:14.505 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:14.505 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:14.505 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:23:14.505 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:23:14.506 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:23:19.509 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:23:19.509 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:23:19.512 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:19.512 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:19.512 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:19.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:19.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:19.522 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:23:19.522 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:19.522 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:23:19.523 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:23:19.525 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:23:19.525 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:23:19.526 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:23:19.526 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:19.526 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:19.526 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:23:19.527 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:23:19.527 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:23:19.527 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:19.528 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:23:19.528 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:23:19.528 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:23:19.528 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:19.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:19.528 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:23:19.528 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:23:19.528 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:23:19.528 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:19.530 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:23:19.530 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:23:19.530 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:23:19.530 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:19.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:19.531 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:23:19.531 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:23:19.531 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:23:19.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:19.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:19.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:19.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:19.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:19.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:19.534 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:23:19.534 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:23:19.534 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:23:19.534 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:23:19.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:19.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:19.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:19.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:23:19.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:19.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:19.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:19.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:19.535 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:19.536 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:23:19.536 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:23:19.536 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:23:24.539 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:23:24.539 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:23:24.540 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:24.541 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:24.542 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:24.542 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:24.563 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:24.565 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:23:24.565 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:24.566 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:23:24.566 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:23:24.570 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:23:24.570 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:23:24.571 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:23:24.571 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:24.572 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:24.572 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:23:24.573 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:23:24.573 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:23:24.573 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:24.574 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:23:24.575 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:23:24.575 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:23:24.575 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:24.576 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:24.576 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:23:24.576 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:23:24.576 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:23:24.577 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:24.578 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:23:24.578 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:23:24.578 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:23:24.578 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:24.578 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:24.578 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:23:24.579 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:23:24.579 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:23:24.579 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:24.582 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:23:24.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:23:24.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:23:24.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:23:24.582 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:23:24.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:23:24.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:23:24.583 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:23:24.583 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:23:24.583 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:24.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:24.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:24.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:24.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:24.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:24.588 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:23:25.072 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:23:25.120 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:23:25.123 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:23:25.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:23:25.125 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:23:25.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:23:25.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:23:25.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:23:25.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:23:25.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:23:25.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:23:25.132 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:23:25.132 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:23:25.162 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:23:25.162 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:23:25.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:23:25.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:23:25.550 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:23:25.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:25.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:25.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:25.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:26.028 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:23:26.506 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:23:26.588 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:26.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:26.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:26.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:26.984 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:23:27.462 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:23:27.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:27.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:27.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:27.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:27.940 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:23:28.417 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:23:28.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:28.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:28.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:28.597 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:28.895 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:23:29.372 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:23:29.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:29.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:29.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:29.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:29.850 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:23:30.328 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:23:30.805 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:23:31.283 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:23:31.761 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:23:32.238 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:23:32.716 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:23:33.167 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:23:33.167 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:23:33.169 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:33.169 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:33.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:33.169 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:33.170 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:33.170 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:33.170 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:33.170 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:33.170 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:23:33.170 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:23:33.170 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:23:33.170 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:33.170 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:33.170 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:33.170 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:33.170 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:33.170 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:33.170 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1834 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:38.173 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:23:38.173 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:23:38.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:38.176 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:38.176 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:38.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:38.184 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:38.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:23:38.184 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:38.185 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:23:38.185 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:23:38.187 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:23:38.187 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:23:38.187 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:23:38.187 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:38.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:38.188 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:23:38.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:23:38.189 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:23:38.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:38.190 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:23:38.190 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:23:38.190 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:23:38.190 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:38.190 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:38.190 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:23:38.190 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:23:38.190 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:23:38.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:38.191 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:23:38.191 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:23:38.191 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:23:38.191 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:38.191 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:38.191 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:23:38.191 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:23:38.191 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:23:38.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:38.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:38.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:38.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:38.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:38.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:38.193 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:23:38.193 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:23:38.193 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:23:38.193 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:23:38.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:38.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:38.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:38.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:23:38.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:38.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:38.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:38.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:38.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:38.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:38.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:38.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:23:38.195 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:23:38.195 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:23:38.195 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:43.198 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:23:43.198 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:23:43.199 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:43.201 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:43.201 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:43.202 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:43.210 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:43.211 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:23:43.212 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:43.212 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:23:43.212 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:23:43.215 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:23:43.216 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:23:43.216 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:23:43.217 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:43.217 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:43.217 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:23:43.218 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:23:43.218 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:23:43.218 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:43.219 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:23:43.219 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:23:43.219 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:23:43.219 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:43.219 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:43.219 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:23:43.219 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:23:43.219 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:23:43.220 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:43.221 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:23:43.221 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:23:43.221 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:23:43.221 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:43.221 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:43.222 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:23:43.222 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:23:43.222 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:23:43.222 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:43.224 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:23:43.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:23:43.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:23:43.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:23:43.225 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:23:43.225 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:23:43.225 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:43.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:43.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:43.230 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:23:43.714 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:23:43.754 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:23:43.757 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:23:43.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:23:43.761 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:23:43.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:23:43.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:23:43.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:23:43.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:23:43.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:23:43.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:23:43.768 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:23:43.768 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:23:44.191 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:23:44.228 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:44.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:44.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:44.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:44.670 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:23:45.147 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:23:45.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:45.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:45.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:45.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:45.626 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:23:46.104 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:23:46.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:46.231 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:46.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:46.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:46.582 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:23:47.059 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:23:47.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:47.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:47.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:47.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:47.537 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:23:48.015 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:23:48.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:48.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:48.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:48.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:48.493 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:23:48.970 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:23:49.448 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:23:49.925 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:23:50.403 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:23:50.880 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:23:51.358 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:23:51.836 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:23:52.314 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:23:52.791 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:23:53.269 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:23:53.746 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:23:53.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:23:53.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:23:53.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:53.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:53.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:53.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:53.817 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:53.817 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:53.817 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:53.817 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:23:53.817 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:23:53.817 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:23:53.817 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:53.817 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:53.817 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:53.817 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:53.817 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:53.817 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:53.817 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:53.817 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:53.817 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2261 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:23:58.819 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:23:58.819 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:23:58.821 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:58.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:58.823 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:58.824 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:58.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:58.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:23:58.833 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:58.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:23:58.833 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:23:58.836 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:23:58.837 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:23:58.837 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:23:58.837 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:58.838 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:58.838 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:23:58.838 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:23:58.838 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:23:58.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:23:58.839 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:23:58.839 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:23:58.839 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:23:58.839 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:58.840 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:58.840 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:23:58.840 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:23:58.840 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:23:58.840 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:23:58.842 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:23:58.842 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:23:58.842 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:23:58.842 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:23:58.842 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:58.842 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:23:58.842 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:23:58.842 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:23:58.842 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:23:58.845 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:23:58.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:23:58.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:23:58.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:23:58.845 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:23:58.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:23:58.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:23:58.846 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:23:58.846 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:23:58.846 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:58.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:23:58.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:58.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:58.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:58.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:58.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:58.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:58.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:58.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:58.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:58.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:23:58.848 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:23:58.848 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:23:58.848 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:24:03.854 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:24:03.854 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:24:03.854 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:03.854 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:03.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:03.854 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:03.863 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:03.865 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:24:03.865 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:03.866 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:24:03.866 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:24:03.869 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:24:03.870 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:24:03.870 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:24:03.870 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:03.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:03.870 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:24:03.870 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:24:03.871 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:24:03.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:03.873 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:24:03.873 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:24:03.874 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:24:03.874 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:03.874 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:03.874 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:24:03.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:24:03.875 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:24:03.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:03.876 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:24:03.876 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:24:03.876 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:24:03.876 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:03.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:03.876 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:24:03.876 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:24:03.876 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:24:03.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:03.877 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:24:03.877 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:24:03.877 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:24:03.877 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:24:03.877 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:24:03.877 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:24:03.877 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:24:03.878 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:24:03.878 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:24:03.878 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:03.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:03.883 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:24:04.366 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:24:04.399 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:24:04.400 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:24:04.402 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:24:04.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:24:04.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:24:04.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:24:04.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:24:04.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:24:04.406 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:24:04.406 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:24:04.407 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:24:04.407 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:24:04.410 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:24:04.410 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:24:04.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:24:04.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:24:04.843 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:24:04.880 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:04.881 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:04.881 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:04.882 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:05.321 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:24:05.799 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:24:05.881 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:05.881 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:05.881 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:05.882 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:06.277 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:24:06.755 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:24:06.882 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:06.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:06.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:06.883 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:07.233 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:24:07.711 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:24:07.883 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:07.883 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:07.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:07.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:08.188 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:24:08.665 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:24:08.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:08.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:08.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:08.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:09.142 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:24:09.620 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:24:10.097 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:24:10.575 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:24:11.053 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:24:11.531 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:24:12.009 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:24:12.486 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:24:12.964 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:24:13.442 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:24:13.919 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:24:14.397 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:24:14.875 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:24:15.353 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:24:15.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:24:15.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:24:15.419 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:15.419 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:15.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:15.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:15.422 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:15.422 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:15.422 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:15.422 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:15.422 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:24:15.422 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:24:15.422 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:24:15.422 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2464 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:15.422 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2464 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:15.422 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2464 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:15.422 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2464 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:15.422 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2464 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:15.422 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2464 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:15.422 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2464 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:20.423 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:24:20.423 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:24:20.424 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:20.425 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:20.426 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:20.426 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:20.433 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:20.434 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:24:20.434 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:20.435 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:24:20.435 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:24:20.437 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:24:20.437 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:24:20.437 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:24:20.437 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:20.438 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:20.438 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:24:20.438 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:24:20.439 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:24:20.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:20.439 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:24:20.439 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:24:20.439 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:24:20.439 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:20.439 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:20.440 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:24:20.440 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:24:20.440 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:24:20.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:20.441 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:24:20.441 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:24:20.441 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:24:20.441 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:20.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:20.442 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:24:20.442 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:24:20.442 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:24:20.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:20.444 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:24:20.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:24:20.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:24:20.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:24:20.444 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:24:20.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:24:20.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:24:20.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:24:20.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:24:20.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:20.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:20.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:24:20.445 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:24:20.445 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:24:20.445 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:20.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:20.446 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:20.447 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:24:20.447 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:24:20.447 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:24:25.449 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:24:25.450 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:24:25.454 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:25.454 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:25.454 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:25.454 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:25.460 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:25.461 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:24:25.461 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:25.461 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:24:25.461 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:24:25.463 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:24:25.464 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:24:25.464 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:24:25.464 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:25.464 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:25.464 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:24:25.464 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:24:25.464 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:24:25.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:25.467 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:24:25.467 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:24:25.467 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:24:25.468 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:25.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:25.468 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:24:25.468 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:24:25.468 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:24:25.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:25.470 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:24:25.470 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:24:25.471 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:24:25.471 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:25.471 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:25.471 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:24:25.471 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:24:25.471 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:24:25.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:25.474 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:24:25.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:24:25.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:25.475 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:24:25.475 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:24:25.475 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:24:25.476 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:24:25.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:25.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:25.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:25.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:24:25.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:25.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:25.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:25.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:25.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:25.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:25.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:25.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:25.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:25.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:25.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:25.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:25.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:25.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:25.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:25.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:25.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:25.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:25.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:25.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:25.480 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:24:25.962 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:24:26.010 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:24:26.012 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:24:26.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:24:26.014 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:24:26.443 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:24:26.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:26.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:26.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:26.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:26.924 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:24:27.405 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:24:27.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:27.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:27.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:27.488 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:27.885 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:24:28.363 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:24:28.483 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:28.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:28.485 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:28.488 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:28.841 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:24:29.319 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:24:29.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:29.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:29.486 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:29.489 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:29.797 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:24:30.275 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:24:30.485 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:30.486 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:30.486 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:30.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:30.753 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:24:31.231 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:24:31.709 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:24:32.186 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:24:32.664 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:24:33.142 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:24:33.620 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:24:34.098 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:24:34.577 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:24:35.054 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:24:35.533 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:24:36.011 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:24:36.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:36.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:36.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:36.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:36.027 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:36.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:36.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:36.027 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:24:36.027 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:24:36.027 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:24:36.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:36.027 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2249 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:36.027 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2249 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:36.027 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:36.027 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2249 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:36.027 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2249 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:41.028 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:24:41.028 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:24:41.029 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:41.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:41.031 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:41.032 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:41.042 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:41.042 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:24:41.042 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:41.043 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:24:41.043 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:24:41.044 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:24:41.044 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:24:41.044 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:24:41.045 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:41.045 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:41.045 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:24:41.045 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:24:41.045 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:24:41.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:41.046 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:24:41.046 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:24:41.046 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:24:41.046 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:41.046 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:24:41.046 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:41.046 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:24:41.046 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:24:41.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:41.048 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:24:41.048 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:24:41.048 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:24:41.048 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:41.048 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:24:41.049 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:24:41.049 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:24:41.049 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:41.049 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:41.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:41.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:41.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:41.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:41.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:41.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:41.053 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:24:41.053 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:24:41.053 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:24:41.053 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:24:41.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:41.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:41.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:41.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:41.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:41.055 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:41.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:41.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:41.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:41.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:41.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:41.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:41.055 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:41.055 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:41.055 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:41.055 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:24:41.055 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:24:41.055 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:24:46.058 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:24:46.058 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:24:46.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:46.062 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:46.062 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:46.062 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:46.068 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:46.069 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:24:46.069 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:46.069 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:24:46.069 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:24:46.070 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:24:46.070 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:24:46.071 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:24:46.071 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:46.071 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:46.072 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:24:46.072 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:24:46.072 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:24:46.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:46.073 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:24:46.073 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:24:46.073 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:24:46.073 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:46.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:46.073 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:24:46.074 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:24:46.074 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:24:46.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:46.076 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:24:46.076 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:24:46.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:24:46.076 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:24:46.076 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:46.076 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:24:46.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:24:46.076 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:24:46.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:46.079 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:24:46.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:24:46.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:24:46.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:24:46.079 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:24:46.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:24:46.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:24:46.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:24:46.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:24:46.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:46.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:46.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:24:46.080 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:24:46.080 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:24:46.080 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:46.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:46.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:24:46.085 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:24:46.569 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:24:46.610 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:24:46.612 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:24:46.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:24:46.613 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:24:47.038 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:24:47.084 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:47.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:47.086 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:47.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:47.507 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:24:47.982 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:24:48.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:48.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:48.088 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:48.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:48.462 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:24:48.940 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:24:49.087 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:49.087 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:49.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:49.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:49.418 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:24:49.900 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:24:50.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:50.089 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:50.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:50.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:50.381 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:24:50.862 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:24:51.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:51.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:51.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:51.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:51.343 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:24:51.824 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:24:52.302 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:24:52.783 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:24:53.263 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:24:53.743 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:24:54.226 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:24:54.706 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:24:55.174 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:24:55.645 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:24:56.126 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:24:56.606 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:24:57.087 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:24:57.567 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:24:58.048 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:24:58.529 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:24:58.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:24:58.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:24:58.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:24:58.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:24:58.627 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:24:58.627 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:24:58.627 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:24:58.627 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:24:58.627 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:24:58.627 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:24:58.627 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:24:58.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2675 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:58.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2675 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:58.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2675 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:58.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2675 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:58.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2675 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:58.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2675 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:24:58.627 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2675 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:03.627 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:25:03.628 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:25:03.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:03.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:03.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:03.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:03.640 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:03.642 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:25:03.642 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:03.642 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:25:03.642 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:25:03.645 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:25:03.645 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:25:03.646 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:25:03.646 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:03.646 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:03.646 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:25:03.646 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:25:03.646 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:25:03.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:03.649 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:25:03.649 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:25:03.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:25:03.649 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:03.650 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:03.650 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:25:03.650 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:25:03.650 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:25:03.650 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:03.652 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:25:03.652 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:25:03.652 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:25:03.652 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:03.652 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:03.653 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:25:03.653 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:25:03.653 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:25:03.653 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:03.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:03.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:03.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:03.658 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:25:03.658 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:25:03.658 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:25:03.658 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:25:03.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:03.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:03.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:03.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:25:03.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:03.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:03.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:03.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:03.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:03.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:03.663 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:25:04.145 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:25:04.184 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:25:04.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:04.187 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:25:04.188 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:25:04.191 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:04.191 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:04.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:04.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:04.192 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:04.193 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:04.193 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:25:04.194 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:25:04.622 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:25:04.662 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:04.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:04.681 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:04.681 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:05.100 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:25:05.577 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:25:05.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:05.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:05.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:05.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:06.055 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:25:06.533 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:25:06.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:06.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:06.683 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:06.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:07.011 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:25:07.488 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:25:07.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:07.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:07.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:07.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:07.966 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:25:08.443 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:25:08.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:08.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:08.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:08.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:08.921 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:25:09.398 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:25:09.876 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:25:10.354 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:25:10.832 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:25:11.309 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:25:11.787 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:25:12.265 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:25:12.742 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:25:13.220 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:25:13.697 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:25:14.175 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:25:14.653 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:25:15.131 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:25:15.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:15.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:15.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:15.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:15.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:15.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:15.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:15.245 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:15.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:15.245 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:25:15.245 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:25:15.245 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:25:15.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:15.245 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:15.245 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:15.245 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:15.245 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:15.245 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:15.245 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:15.245 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:20.248 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:25:20.248 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:25:20.249 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:20.250 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:20.251 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:20.251 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:20.262 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:20.263 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:25:20.263 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:20.263 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:25:20.263 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:25:20.264 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:25:20.265 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:25:20.265 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:25:20.265 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:20.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:20.265 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:25:20.266 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:25:20.266 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:25:20.266 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:20.266 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:25:20.266 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:25:20.266 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:25:20.266 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:20.266 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:20.266 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:25:20.266 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:25:20.267 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:25:20.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:20.267 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:25:20.267 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:25:20.267 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:25:20.268 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:20.268 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:20.268 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:25:20.268 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:25:20.268 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:25:20.268 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:20.269 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:25:20.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:25:20.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:25:20.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:25:20.269 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:25:20.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:25:20.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:25:20.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:25:20.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:25:20.269 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:20.269 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:20.269 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:25:20.270 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:25:20.270 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:25:20.270 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:20.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:20.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:20.274 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:25:20.759 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:25:20.797 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:25:20.799 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:25:20.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:20.801 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:25:20.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:20.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:20.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:20.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:20.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:20.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:20.805 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:25:20.805 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:25:21.236 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:25:21.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:21.273 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:21.274 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:21.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:21.714 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:25:22.191 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:25:22.274 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:22.274 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:22.275 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:22.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:22.669 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:25:23.147 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:25:23.275 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:23.275 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:23.276 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:23.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:23.624 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:25:24.101 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:25:24.276 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:24.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:24.276 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:24.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:24.579 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:25:25.057 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:25:25.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:25.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:25.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:25.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:25.535 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:25:26.012 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:25:26.490 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:25:26.968 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:25:27.446 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:25:27.924 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:25:28.402 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:25:28.880 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:25:29.358 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:25:29.835 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:25:30.313 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:25:30.791 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:25:31.269 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:25:31.746 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:25:32.225 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:25:32.702 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:25:33.180 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:25:33.657 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:25:34.136 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:25:34.614 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:25:35.090 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:25:35.568 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:25:35.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:35.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:35.859 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:35.859 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:35.860 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:35.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:35.861 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:35.861 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:35.861 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:35.861 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:35.861 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:25:35.861 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:25:35.861 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:25:40.862 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:25:40.862 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:25:40.866 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:40.866 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:40.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:40.866 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:40.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:40.877 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:25:40.877 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:40.877 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:25:40.878 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:25:40.881 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:25:40.882 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:25:40.882 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:25:40.882 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:40.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:40.882 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:25:40.882 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:25:40.883 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:25:40.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:40.885 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:25:40.885 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:25:40.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:25:40.886 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:40.886 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:40.887 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:25:40.887 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:25:40.887 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:25:40.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:40.888 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:25:40.888 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:25:40.889 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:25:40.889 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:40.889 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:40.889 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:25:40.889 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:25:40.889 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:25:40.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:40.892 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:25:40.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:25:40.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:25:40.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:25:40.892 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:25:40.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:25:40.892 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:25:40.892 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:25:40.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:25:40.892 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:25:40.893 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:25:40.893 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:25:40.893 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:40.893 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:40.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:40.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:40.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:40.898 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:25:41.382 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:25:41.426 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:25:41.427 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:25:41.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:41.429 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:25:41.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:41.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:41.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:41.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:41.434 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:41.434 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:41.434 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:25:41.434 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:25:41.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:41.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:41.483 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:41.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:41.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:41.483 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:41.486 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:41.486 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:41.486 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:41.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:41.486 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:25:41.486 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:25:41.486 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:25:41.486 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:41.486 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:41.486 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:41.486 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:41.486 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:41.486 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:41.486 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:46.487 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:25:46.487 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:25:46.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:46.490 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:46.491 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:46.491 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:46.502 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:46.503 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:25:46.503 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:46.503 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:25:46.503 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:25:46.505 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:25:46.505 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:25:46.506 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:25:46.506 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:46.506 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:46.506 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:25:46.507 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:25:46.507 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:25:46.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:46.507 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:25:46.507 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:25:46.507 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:25:46.507 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:46.508 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:25:46.508 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:46.508 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:25:46.508 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:25:46.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:46.510 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:25:46.510 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:25:46.510 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:25:46.510 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:46.510 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:46.510 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:25:46.510 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:25:46.510 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:25:46.510 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:46.513 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:25:46.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:25:46.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:25:46.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:25:46.513 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:25:46.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:25:46.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:25:46.514 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:25:46.514 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:25:46.514 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:46.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:46.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:46.519 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:25:47.004 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:25:47.040 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:25:47.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:47.044 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:25:47.047 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:25:47.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:47.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:47.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:47.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:47.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:47.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:47.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:47.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:47.079 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:47.079 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:25:47.079 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:25:47.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:47.095 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:47.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:47.206 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:47.206 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:47.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:47.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:47.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:47.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:47.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:47.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:47.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:47.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.234 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:47.234 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:47.234 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:25:47.234 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:25:47.236 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:47.236 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:47.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:47.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:47.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:47.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:47.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:47.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:47.429 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:47.429 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:47.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:47.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:47.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.431 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:47.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:47.431 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:25:47.431 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:25:47.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:47.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:47.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.476 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:25:47.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:47.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:47.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:47.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:47.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:47.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:47.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:47.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:47.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:47.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:47.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:47.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:47.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:47.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:47.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:47.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:47.898 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:25:47.898 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:25:47.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:47.945 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:47.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:47.951 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:25:48.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:48.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:48.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:48.275 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:48.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:48.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:48.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:48.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:48.288 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:48.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:48.289 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:48.289 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:48.289 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:25:48.289 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:25:48.289 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:25:48.289 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=380 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:48.289 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=380 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:48.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=380 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:48.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=380 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:48.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=380 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:48.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=380 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:48.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=381 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:48.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=381 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:48.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=381 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:48.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=381 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:48.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=381 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:48.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=381 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:48.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=381 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:48.291 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=381 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:25:53.291 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:25:53.291 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:25:53.292 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:53.292 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:53.292 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:53.292 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:53.301 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:25:53.303 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:25:53.303 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:53.303 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:25:53.303 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:25:53.308 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:25:53.308 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:25:53.308 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:25:53.309 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:53.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:25:53.309 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:25:53.310 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:25:53.310 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:25:53.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:53.311 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:25:53.312 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:25:53.312 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:25:53.312 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:53.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:25:53.312 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:25:53.312 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:25:53.312 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:25:53.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:53.314 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:25:53.314 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:25:53.314 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:25:53.314 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:25:53.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:25:53.314 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:25:53.315 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:25:53.315 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:25:53.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:53.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:25:53.318 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:25:53.318 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:25:53.318 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:53.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:53.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:25:53.323 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:25:53.804 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:25:53.842 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:25:53.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:53.846 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:25:53.847 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:25:53.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:53.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:53.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:53.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:53.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:53.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:53.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:53.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:53.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:53.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:53.899 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:25:53.899 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:25:53.941 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:53.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:53.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:53.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:54.280 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:25:54.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:54.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:54.321 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:54.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:54.758 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:25:55.236 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:25:55.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:55.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:55.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:55.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:55.714 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:25:56.192 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:25:56.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:56.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:56.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:56.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:56.670 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:25:57.148 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:25:57.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:57.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:57.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:57.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:57.626 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:25:58.104 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:25:58.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:25:58.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:25:58.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:25:58.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:25:58.582 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:25:58.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:58.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:58.950 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:58.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:58.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:58.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:58.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:58.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:25:58.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:25:58.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:25:58.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:25:58.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:58.977 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:58.977 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:58.977 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:25:58.977 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:25:59.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:25:59.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:25:59.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:59.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:25:59.059 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:25:59.537 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:26:00.015 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:26:00.493 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:26:00.971 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:26:01.449 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:26:01.927 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:26:02.405 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:26:02.884 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:26:03.362 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:26:03.840 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:26:04.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:04.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:04.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:04.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:04.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:04.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:04.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:04.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:04.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:04.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:04.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:04.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:04.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:04.040 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:04.040 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:26:04.040 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:26:04.075 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:04.075 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:04.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:04.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:04.318 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:26:04.795 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:26:05.273 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:26:05.752 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:26:06.229 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:26:06.707 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:26:07.185 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:26:07.662 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:26:08.140 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:26:08.617 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:26:09.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:09.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:09.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:09.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:09.095 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:26:09.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:09.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:09.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:09.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:09.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:09.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:09.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:09.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:09.110 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:09.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:09.111 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:26:09.111 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:26:09.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:09.141 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:09.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:09.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:09.572 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:26:10.050 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:26:10.529 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:26:11.006 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:26:11.484 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:26:11.961 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:26:12.439 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:26:12.916 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:26:13.394 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:26:13.872 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:26:14.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:14.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:14.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:14.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:14.161 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:14.161 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:14.161 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:14.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:14.165 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:26:14.165 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:26:14.165 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:26:14.165 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:26:14.165 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:26:14.165 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:26:14.165 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:26:14.166 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4450 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.166 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4450 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.166 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4450 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.166 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4450 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.166 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4450 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.166 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4450 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.166 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4450 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.166 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:14.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:26:19.164 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:26:19.165 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:26:19.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:26:19.167 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:26:19.167 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:26:19.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:26:19.177 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:26:19.178 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:26:19.178 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:26:19.178 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:26:19.179 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:26:19.182 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:26:19.182 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:26:19.182 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:26:19.182 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:26:19.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:26:19.183 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:26:19.183 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:26:19.183 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:26:19.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:19.186 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:26:19.187 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:26:19.187 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:26:19.187 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:26:19.187 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:26:19.187 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:26:19.187 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:26:19.187 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:26:19.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:19.192 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:26:19.192 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:26:19.192 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:26:19.192 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:26:19.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:26:19.192 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:26:19.192 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:26:19.192 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:26:19.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:19.197 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:26:19.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:26:19.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:26:19.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:26:19.198 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:26:19.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:26:19.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:26:19.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:26:19.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:26:19.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:19.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:19.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:19.198 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:26:19.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:19.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:19.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:19.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:19.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:19.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:19.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:19.199 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:26:19.199 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:26:19.199 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:26:19.199 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:26:19.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:19.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:19.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:19.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:26:19.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:19.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:19.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:19.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:19.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:19.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:19.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:19.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:19.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:19.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:19.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:19.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:19.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:19.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:19.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:19.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:19.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:19.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:19.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:19.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:19.204 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:26:19.686 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:26:19.732 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:26:19.733 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:26:19.735 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:26:19.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:19.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:19.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:19.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:19.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:19.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:19.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:19.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:19.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:19.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:19.779 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:19.779 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:26:19.779 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:26:19.824 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:19.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:19.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:19.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:20.164 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:26:20.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:20.204 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:20.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:20.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:20.642 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:26:21.120 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:26:21.204 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:21.204 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:21.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:21.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:21.598 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:26:22.076 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:26:22.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:22.206 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:22.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:22.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:22.554 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:26:23.032 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:26:23.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:23.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:23.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:23.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:23.509 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:26:23.987 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:26:24.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:24.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:24.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:24.215 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:24.465 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:26:24.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:24.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:24.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:24.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:24.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:24.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:24.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:24.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:24.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:24.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:24.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:24.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:24.860 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:24.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:24.860 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:26:24.860 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:26:24.884 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:24.885 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:24.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:24.885 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:24.943 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:26:25.421 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:26:25.899 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:26:26.377 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:26:26.856 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:26:27.334 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:26:27.812 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:26:28.290 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:26:28.768 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:26:29.246 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:26:29.724 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:26:29.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:29.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:29.895 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:29.895 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:29.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:29.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:29.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:29.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:29.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:29.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:29.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:29.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:29.923 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:29.923 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:29.923 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:26:29.923 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:26:29.959 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:29.959 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:29.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:29.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:30.201 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:26:30.680 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:26:31.158 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:26:31.635 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:26:32.113 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:26:32.590 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:26:33.068 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:26:33.545 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:26:34.023 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:26:34.501 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:26:34.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:34.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:34.970 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:34.970 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:34.979 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:26:34.987 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:34.987 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:34.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:34.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:34.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:34.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:34.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:34.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:34.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:34.995 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:34.995 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:26:34.995 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:26:35.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:35.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:35.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:35.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:35.455 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:26:35.933 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:26:36.412 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:26:36.890 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:26:37.369 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:26:37.846 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:26:38.325 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:26:38.803 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:26:39.280 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:26:39.759 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:26:40.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:40.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:40.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:40.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:40.039 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:40.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:40.039 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:40.039 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:40.040 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:26:40.040 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:26:40.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:26:40.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:26:40.040 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:26:40.040 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:26:40.040 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:26:45.043 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:26:45.043 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:26:45.044 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:26:45.045 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:26:45.046 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:26:45.046 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:26:45.053 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:26:45.054 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:26:45.054 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:26:45.054 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:26:45.055 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:26:45.056 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:26:45.056 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:26:45.057 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:26:45.057 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:26:45.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:26:45.057 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:26:45.058 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:26:45.058 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:26:45.058 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:45.059 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:26:45.059 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:26:45.059 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:26:45.059 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:26:45.059 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:26:45.059 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:26:45.059 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:26:45.059 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:26:45.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:45.061 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:26:45.061 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:26:45.061 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:26:45.061 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:26:45.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:26:45.061 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:26:45.061 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:26:45.061 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:26:45.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:26:45.064 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:26:45.064 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:26:45.064 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:45.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:45.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:26:45.069 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:26:45.552 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:26:45.593 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:26:45.594 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:26:45.595 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:26:45.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:45.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:45.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:45.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:45.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:45.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:45.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:45.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:45.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:45.643 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:45.643 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:45.643 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:26:45.643 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:26:45.690 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:45.691 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:45.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:45.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:46.030 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:26:46.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:46.067 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:46.068 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:46.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:46.508 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:26:46.986 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:26:47.068 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:47.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:47.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:47.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:47.463 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:26:47.942 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:26:48.069 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:48.069 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:48.070 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:48.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:48.420 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:26:48.898 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:26:49.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:49.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:49.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:49.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:49.376 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:26:49.854 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:26:50.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:26:50.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:26:50.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:26:50.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:26:50.331 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:26:50.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:50.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:50.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:50.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:50.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:50.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:50.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:50.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:50.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:50.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:50.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:50.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:50.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:50.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:50.727 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:26:50.727 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:26:50.751 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:50.751 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:50.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:50.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:50.809 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:26:51.287 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:26:51.765 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:26:52.244 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:26:52.722 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:26:53.199 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:26:53.676 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:26:54.154 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:26:54.632 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:26:55.110 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:26:55.588 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:26:55.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:55.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:55.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:55.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:55.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:55.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:55.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:55.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:26:55.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:26:55.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:26:55.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:26:55.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:55.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:55.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:55.785 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:26:55.785 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:26:55.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:26:55.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:26:55.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:55.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:26:56.066 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:26:56.543 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:26:57.021 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:26:57.498 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:26:57.976 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:26:58.454 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:26:58.932 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:26:59.410 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:26:59.887 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:27:00.365 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:27:00.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:00.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:00.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:00.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:00.843 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:27:00.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:00.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:00.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:00.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:00.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:00.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:00.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:00.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:00.858 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:00.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:00.858 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:27:00.858 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:27:00.888 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:00.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:00.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:00.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:01.320 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:27:01.798 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:27:02.275 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:27:02.753 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:27:03.231 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:27:03.709 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:27:04.187 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:27:04.664 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:27:05.142 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:27:05.619 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:27:05.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:05.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:05.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:05.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:05.911 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:05.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:05.912 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:05.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:05.915 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:27:05.915 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:27:05.916 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:27:05.916 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:27:05.916 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:27:05.916 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:27:05.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:27:05.916 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.916 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.917 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.917 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.917 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.917 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.917 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4451 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.917 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4452 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.917 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4452 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.917 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4452 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.917 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4452 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.917 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4452 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.917 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4452 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.918 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4452 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:05.918 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4452 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:10.915 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:27:10.915 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:27:10.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:27:10.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:27:10.919 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:27:10.919 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:27:10.927 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:27:10.927 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:27:10.927 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:27:10.927 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:27:10.928 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:27:10.929 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:27:10.930 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:27:10.930 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:27:10.930 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:27:10.930 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:27:10.931 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:27:10.931 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:27:10.931 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:27:10.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:10.932 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:27:10.932 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:27:10.932 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:27:10.932 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:27:10.932 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:27:10.932 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:27:10.932 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:27:10.932 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:27:10.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:10.934 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:27:10.934 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:27:10.934 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:27:10.934 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:27:10.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:27:10.935 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:27:10.935 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:27:10.935 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:27:10.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:10.937 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:27:10.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:27:10.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:27:10.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:27:10.937 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:27:10.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:27:10.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:27:10.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:27:10.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:27:10.938 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:27:10.938 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:27:10.938 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:10.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:10.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:10.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:10.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:10.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:10.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:10.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:10.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:10.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:10.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:10.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:10.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:10.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:10.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:10.943 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:27:11.426 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:27:11.461 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:27:11.462 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:27:11.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:11.464 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:27:11.477 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:11.477 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:11.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:11.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:11.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:11.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:11.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:11.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:11.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:11.488 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:11.488 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:27:11.488 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:27:11.519 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:11.519 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:11.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:11.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:11.903 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:27:11.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:11.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:11.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:11.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:12.378 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:27:12.856 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:27:12.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:12.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:12.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:12.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:13.335 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:27:13.813 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:27:13.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:13.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:13.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:13.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:14.291 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:27:14.769 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:27:14.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:14.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:14.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:14.948 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:15.247 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:27:15.725 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:27:15.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:15.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:15.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:15.949 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:16.203 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:27:16.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:16.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:16.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:16.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:16.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:16.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:16.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:16.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:16.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:16.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:16.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:16.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:16.546 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:16.546 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:16.546 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:27:16.546 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:27:16.575 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:16.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:16.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:16.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:16.678 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:27:17.156 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:27:17.634 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:27:18.112 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:27:18.591 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:27:19.069 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:27:19.548 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:27:20.026 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:27:20.504 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:27:20.982 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:27:21.461 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:27:21.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:21.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:21.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:21.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:21.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:21.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:21.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:21.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:21.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:21.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:21.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:21.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:21.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:21.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:21.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:27:21.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:27:21.645 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:21.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:21.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:21.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:21.936 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:27:22.413 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:27:22.891 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:27:23.369 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:27:23.847 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:27:24.324 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:27:24.802 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:27:25.280 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:27:25.758 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:27:26.236 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:27:26.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:26.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:26.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:26.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:26.671 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:26.671 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:26.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:26.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:26.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:26.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:26.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:26.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:26.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:26.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:26.679 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:27:26.679 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:27:26.706 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:26.706 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:26.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:26.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:26.713 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:27:27.190 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:27:27.668 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:27:28.146 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:27:28.624 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:27:29.103 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:27:29.581 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:27:30.058 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:27:30.537 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:27:31.015 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:27:31.492 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:27:31.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:31.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:31.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:31.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:31.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:31.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:31.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:31.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:31.729 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:27:31.729 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:27:31.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:27:31.729 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:27:31.729 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:27:31.729 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:27:31.729 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:27:31.729 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4439 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:31.729 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4439 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:31.729 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4439 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:31.729 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4439 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:31.729 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4439 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:31.729 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4439 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:31.729 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4439 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:36.730 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:27:36.731 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:27:36.732 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:27:36.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:27:36.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:27:36.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:27:36.742 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:27:36.744 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:27:36.744 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:27:36.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:27:36.745 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:27:36.748 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:27:36.748 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:27:36.748 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:27:36.749 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:27:36.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:27:36.749 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:27:36.750 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:27:36.750 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:27:36.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:36.751 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:27:36.751 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:27:36.751 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:27:36.751 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:27:36.751 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:27:36.751 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:27:36.751 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:27:36.752 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:27:36.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:36.753 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:27:36.753 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:27:36.753 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:27:36.753 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:27:36.753 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:27:36.754 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:27:36.754 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:27:36.754 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:27:36.754 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:36.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:27:36.760 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:27:36.760 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:27:36.760 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:36.760 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:36.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:36.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:36.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:36.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:36.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:36.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:36.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:36.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:36.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:36.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:36.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:36.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:36.765 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:27:37.248 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:27:37.284 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:27:37.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:37.288 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:27:37.291 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:27:37.315 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:37.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:37.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:37.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:37.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:37.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:37.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:37.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:37.337 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:37.337 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:37.337 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:27:37.337 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:27:37.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:37.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:37.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:37.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:37.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:37.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:37.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:37.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:37.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:37.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:37.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:37.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:37.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:37.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:37.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:37.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:37.660 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:37.660 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:37.660 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:27:37.660 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:27:37.665 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:37.665 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:37.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:37.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:37.723 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:27:37.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:37.763 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:37.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:37.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:38.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:38.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:38.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:38.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:38.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:38.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:38.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:38.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:38.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:38.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:38.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:38.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:38.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:38.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:38.077 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:27:38.077 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:27:38.091 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:38.091 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:38.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:38.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:38.201 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:27:38.678 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:27:38.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:38.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:38.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:38.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:38.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:38.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:38.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:38.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:38.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:38.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:38.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:38.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:38.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:38.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:38.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:38.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:38.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:38.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:38.866 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:27:38.866 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:27:38.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:38.912 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:38.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:38.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:39.154 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:27:39.632 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:27:39.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:39.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:39.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:39.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:39.730 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:39.730 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:39.730 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:39.730 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:39.734 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:27:39.734 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:27:39.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:27:39.734 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:27:39.734 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:27:39.734 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:27:39.734 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:27:39.735 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=635 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:39.735 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=635 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:39.735 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=635 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:39.735 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=635 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:39.735 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=635 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:39.735 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=635 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:39.735 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=636 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:39.736 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=636 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:39.736 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=636 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:39.736 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=636 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:39.736 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=636 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:39.736 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=636 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:39.736 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=636 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:39.736 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=636 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:27:44.733 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:27:44.734 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:27:44.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:27:44.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:27:44.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:27:44.737 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:27:44.739 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:27:44.740 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:27:44.740 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:27:44.740 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:27:44.740 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:27:44.742 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:27:44.742 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:27:44.742 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:27:44.742 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:27:44.742 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:27:44.742 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:27:44.743 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:27:44.743 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:27:44.743 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:44.745 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:27:44.745 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:27:44.745 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:27:44.745 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:27:44.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:27:44.745 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:27:44.745 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:27:44.745 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:27:44.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:44.747 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:27:44.747 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:27:44.747 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:27:44.747 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:27:44.747 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:27:44.747 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:27:44.747 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:27:44.747 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:27:44.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:44.750 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:27:44.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:27:44.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:27:44.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:27:44.750 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:27:44.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:27:44.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:27:44.751 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:27:44.751 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:27:44.751 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:44.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:44.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:27:44.756 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:27:45.240 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:27:45.285 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:27:45.287 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:27:45.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:45.289 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:27:45.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:45.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:45.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:45.334 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:27:45.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:27:45.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:27:45.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:27:45.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:45.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:45.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:45.339 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:27:45.339 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:27:45.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:27:45.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:27:45.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:45.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:27:45.717 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:27:45.754 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:45.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:45.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:45.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:46.195 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:27:46.672 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:27:46.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:46.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:46.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:46.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:47.150 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:27:47.628 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:27:47.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:47.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:47.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:47.761 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:48.106 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:27:48.584 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:27:48.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:48.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:48.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:48.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:49.061 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:27:49.539 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:27:49.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:27:49.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:27:49.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:27:49.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:27:50.017 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:27:50.496 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:27:50.974 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:27:51.452 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:27:51.929 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:27:52.407 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:27:52.885 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:27:53.363 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:27:53.840 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:27:54.318 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:27:54.796 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:27:55.273 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:27:55.751 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:27:56.229 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:27:56.707 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:27:57.185 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:27:57.663 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:27:58.141 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:27:58.619 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:27:59.097 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:27:59.575 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:28:00.053 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:28:00.532 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:28:01.010 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:28:01.488 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:28:01.966 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:28:02.439 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:28:02.910 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:28:03.377 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:28:03.846 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:28:04.317 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:28:04.795 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:28:05.274 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:28:05.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:28:05.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:28:05.386 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:28:05.386 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:28:05.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:28:05.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:28:05.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:28:05.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:28:05.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:28:05.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:28:05.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:28:05.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:28:05.410 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:28:05.410 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:28:05.410 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:28:05.410 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:28:05.458 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:28:05.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:28:05.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:28:05.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:28:05.751 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:28:06.229 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:28:06.707 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:28:07.185 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:28:07.663 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:28:08.141 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:28:08.619 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:28:09.096 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:28:09.574 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:28:10.050 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:28:10.528 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:28:11.006 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:28:11.484 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:28:11.962 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:28:12.441 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:28:12.919 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:28:13.397 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:28:13.876 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:28:14.354 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 02:28:14.832 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 02:28:15.310 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 02:28:15.788 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 02:28:16.266 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 02:28:16.744 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 02:28:17.222 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 02:28:17.700 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 02:28:18.179 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 02:28:18.657 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 02:28:19.135 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 02:28:19.619 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 02:28:20.097 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 02:28:20.575 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 02:28:21.053 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 02:28:21.531 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 02:28:22.009 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 02:28:22.487 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 02:28:22.966 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 02:28:23.443 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 02:28:23.921 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 02:28:24.400 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 02:28:24.878 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 02:28:25.356 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 02:28:25.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:28:25.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:28:25.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:28:25.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:28:25.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:28:25.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:28:25.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:28:25.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:28:25.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:28:25.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:28:25.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:28:25.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:28:25.492 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:28:25.492 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:28:25.492 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:28:25.492 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:28:25.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:28:25.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:28:25.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:28:25.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:28:25.833 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 02:28:26.311 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 02:28:26.789 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 02:28:27.266 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 02:28:27.743 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 02:28:28.222 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 02:28:28.699 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 02:28:29.177 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 02:28:29.655 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 02:28:30.132 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 02:28:30.610 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 02:28:31.088 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 02:28:31.566 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 02:28:32.043 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 02:28:32.521 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 02:28:32.999 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 02:28:33.477 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 02:28:33.955 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 02:28:34.433 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 02:28:34.910 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 02:28:35.388 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 02:28:35.866 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 02:28:36.344 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 02:28:36.822 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 02:28:37.300 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 02:28:37.778 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 02:28:38.256 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 02:28:38.734 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 02:28:39.211 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 02:28:39.689 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 02:28:40.167 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 02:28:40.645 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 02:28:41.123 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 02:28:41.601 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 02:28:42.079 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 02:28:42.556 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 02:28:43.034 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 02:28:43.511 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 02:28:43.989 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 02:28:44.467 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 02:28:44.945 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 02:28:45.422 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-05 02:28:45.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:28:45.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:28:45.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:28:45.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:28:45.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:28:45.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:28:45.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:28:45.574 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:28:45.574 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:28:45.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:28:45.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:28:45.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:28:45.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:28:45.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:28:45.576 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:28:45.576 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:28:45.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:28:45.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:28:45.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:28:45.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:28:45.900 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-05 02:28:46.377 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-05 02:28:46.855 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-05 02:28:47.332 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-05 02:28:47.810 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-05 02:28:48.284 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-05 02:28:48.761 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-05 02:28:49.239 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-05 02:28:49.717 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-05 02:28:50.195 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-05 02:28:50.673 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-05 02:28:51.151 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-05 02:28:51.630 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-05 02:28:52.108 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-05 02:28:52.586 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-05 02:28:53.063 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-05 02:28:53.540 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-05 02:28:54.018 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-05 02:28:54.495 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-05 02:28:54.973 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-05 02:28:55.450 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-05 02:28:55.928 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-05 02:28:56.405 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-05 02:28:56.884 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-05 02:28:57.361 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-05 02:28:57.839 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-05 02:28:58.317 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-05 02:28:58.795 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-05 02:28:59.272 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-05 02:28:59.750 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-05 02:29:00.228 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-05 02:29:00.706 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-05 02:29:01.184 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-05 02:29:01.662 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-05 02:29:02.140 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-05 02:29:02.618 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-05 02:29:03.096 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-05 02:29:03.575 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-05 02:29:04.053 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-05 02:29:04.531 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-05 02:29:05.009 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-05 02:29:05.487 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-05 02:29:05.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:05.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:05.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:05.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:05.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:05.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:05.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:05.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:05.635 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:29:05.635 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:29:05.635 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:29:05.635 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:29:05.635 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:29:05.635 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:29:05.635 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17271 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17271 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17271 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17271 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17271 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17271 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17272 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17272 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17272 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17272 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17272 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17272 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17272 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:05.635 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=17272 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:10.635 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:29:10.636 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:29:10.637 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:29:10.638 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:29:10.638 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:29:10.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:29:10.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:29:10.648 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:29:10.649 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:10.649 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:29:10.649 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:29:10.652 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:29:10.653 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:29:10.653 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:29:10.653 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:10.654 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:29:10.654 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:29:10.655 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:29:10.655 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:29:10.655 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:10.656 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:29:10.656 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:29:10.656 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:29:10.656 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:10.656 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:29:10.656 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:29:10.656 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:29:10.656 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:29:10.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:10.658 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:29:10.658 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:29:10.658 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:29:10.658 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:10.658 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:29:10.658 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:29:10.659 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:29:10.659 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:29:10.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:10.661 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:29:10.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:29:10.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:29:10.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:29:10.661 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:29:10.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:29:10.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:29:10.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:29:10.662 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:29:10.662 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:29:10.662 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:10.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:29:10.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:10.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:10.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:10.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:10.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:10.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:10.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:29:10.664 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:29:10.664 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:29:10.664 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:29:15.667 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:29:15.667 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:29:15.668 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:29:15.670 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:29:15.671 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:29:15.671 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:29:15.685 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:29:15.687 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:29:15.687 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:15.688 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:29:15.688 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:29:15.691 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:29:15.692 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:29:15.692 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:29:15.692 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:15.693 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:29:15.693 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:29:15.693 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:29:15.693 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:29:15.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:15.695 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:29:15.695 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:29:15.695 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:29:15.695 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:15.695 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:29:15.695 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:29:15.696 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:29:15.696 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:29:15.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:15.697 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:29:15.697 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:29:15.697 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:29:15.697 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:15.697 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:29:15.697 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:29:15.697 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:29:15.697 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:29:15.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:15.700 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:29:15.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:29:15.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:29:15.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:29:15.700 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:29:15.700 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:29:15.700 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:29:15.700 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:29:15.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:29:15.701 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:29:15.701 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:29:15.701 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:15.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:15.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:15.706 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:29:16.188 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:29:16.232 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:29:16.234 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:29:16.235 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:29:16.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:16.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:16.256 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:16.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:16.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:16.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:16.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:16.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:16.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:16.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:16.279 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:16.279 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:16.280 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:16.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:16.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:16.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:16.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:16.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:16.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:16.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:16.529 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:16.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:16.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:16.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:16.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:16.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:16.546 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:16.547 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:16.547 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:16.547 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:16.559 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:16.559 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:16.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:16.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:16.663 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:29:16.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:16.704 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:16.705 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:16.708 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:16.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:16.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:16.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:16.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:16.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:16.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:16.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:16.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:16.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:16.784 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:16.784 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:16.785 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:16.785 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:16.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:16.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:16.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:16.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:17.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:17.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:17.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:17.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:17.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:17.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:17.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:17.031 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:17.031 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:17.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:17.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:17.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:17.033 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:17.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:17.033 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:17.033 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:17.078 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:17.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:17.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:17.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:17.137 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:29:17.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:17.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:17.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:17.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:17.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:17.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:17.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:17.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:17.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:17.415 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:17.415 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:17.415 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:17.415 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:17.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:17.465 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:17.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:17.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:17.615 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:29:17.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:17.705 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:17.706 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:17.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:17.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:17.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:17.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:17.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:17.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:17.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:17.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:17.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:17.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:17.779 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:17.779 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:17.779 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:17.779 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:17.797 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:17.798 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:17.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:17.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:18.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:18.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:18.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:18.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:18.094 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:29:18.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:18.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:18.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:18.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:18.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:18.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:18.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:18.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:18.110 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:18.110 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:18.111 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:18.111 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:18.139 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:18.139 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:18.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:18.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:18.571 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:29:18.705 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:18.706 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:18.708 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:18.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:19.048 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:29:19.526 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:29:19.707 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:19.707 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:19.708 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:19.711 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:20.004 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:29:20.482 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:29:20.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:20.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:20.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:20.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:20.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:20.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:20.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:20.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:20.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:20.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:20.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:20.661 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:20.661 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:20.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:20.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:20.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:20.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:20.708 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:20.708 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:20.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:20.711 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:20.958 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:29:21.435 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:29:21.913 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:29:22.391 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:29:22.869 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:29:23.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:23.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:23.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:23.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:23.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:23.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:23.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:23.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:23.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:23.284 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:23.284 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:23.284 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:23.284 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:23.285 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:23.285 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:23.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:23.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:23.346 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:29:23.822 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:29:24.301 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:29:24.778 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:29:25.256 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:29:25.734 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:29:25.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:25.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:25.894 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:25.894 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:25.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:25.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:25.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:25.909 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:25.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:25.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:25.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:25.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:25.911 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:25.911 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:25.911 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:25.911 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:25.914 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:25.914 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:25.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:25.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:26.210 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:29:26.687 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:29:27.165 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:29:27.643 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:29:28.120 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:29:28.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:28.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:28.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:28.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:28.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:28.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:28.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:28.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:28.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:28.462 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:28.462 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:28.462 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:28.462 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:28.492 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:28.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:28.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:28.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:28.597 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:29:29.075 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:29:29.553 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:29:30.031 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:29:30.509 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:29:30.987 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:29:31.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:31.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:31.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:31.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:31.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:31.090 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:31.090 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:31.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:31.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:31.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:31.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:31.092 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:31.092 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:31.125 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:31.125 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:31.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:31.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:31.465 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:29:31.942 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:29:32.420 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:29:32.898 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:29:33.376 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:29:33.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:33.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:33.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:33.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:33.709 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:33.709 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:33.710 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:33.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:33.713 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:29:33.713 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:29:33.713 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:29:33.713 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:29:33.714 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:29:33.714 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:29:33.714 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:29:33.714 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3848 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.714 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3848 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.715 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3848 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.715 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3848 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.715 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3848 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.715 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3848 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.715 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3848 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.715 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3849 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.715 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3849 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.715 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3849 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.715 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3849 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.715 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3849 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.715 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3849 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.716 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3849 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:33.716 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3849 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:38.713 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:29:38.714 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:29:38.715 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:29:38.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:29:38.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:29:38.718 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:29:38.725 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:29:38.726 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:29:38.726 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:38.727 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:29:38.727 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:29:38.730 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:29:38.730 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:29:38.730 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:29:38.730 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:38.731 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:29:38.731 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:29:38.732 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:29:38.732 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:29:38.732 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:38.733 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:29:38.733 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:29:38.733 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:29:38.733 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:38.733 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:29:38.733 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:29:38.733 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:29:38.733 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:29:38.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:38.735 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:29:38.735 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:29:38.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:29:38.735 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:38.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:29:38.735 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:29:38.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:29:38.735 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:29:38.736 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:38.738 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:29:38.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:29:38.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:29:38.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:29:38.738 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:29:38.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:29:38.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:29:38.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:29:38.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:29:38.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:29:38.739 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:29:38.739 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:38.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:38.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:38.744 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:29:39.228 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:29:39.272 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:29:39.274 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:29:39.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:39.276 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:29:39.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:39.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:39.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:39.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:39.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:39.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:39.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:39.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:39.330 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:39.330 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:39.330 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:39.330 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:39.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:39.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:39.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:39.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:39.704 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:29:39.741 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:39.742 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:39.743 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:39.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:40.182 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:29:40.660 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:29:40.742 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:40.743 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:40.744 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:40.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:41.138 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:29:41.616 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:29:41.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:41.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:41.744 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:41.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:42.093 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:29:42.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:42.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:42.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:42.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:42.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:42.498 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:42.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:42.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:42.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:42.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:42.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:42.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:42.506 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:42.506 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:42.506 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:42.506 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:42.510 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:42.510 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:42.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:42.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:42.570 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:29:42.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:42.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:42.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:42.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:43.048 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:29:43.526 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:29:43.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:43.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:43.747 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:43.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:44.004 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:29:44.482 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:29:44.961 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:29:45.438 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:29:45.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:45.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:45.696 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:45.696 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:45.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:45.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:45.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:45.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:45.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:45.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:45.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:45.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:45.713 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:45.713 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:45.713 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:45.713 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:45.716 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:45.716 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:45.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:45.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:45.914 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:29:46.392 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:29:46.869 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:29:47.347 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:29:47.825 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:29:48.303 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:29:48.781 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:29:48.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:48.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:48.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:48.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:48.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:48.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:48.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:48.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:48.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:48.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:48.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:48.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:48.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:48.931 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:48.931 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:48.931 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:48.965 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:48.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:48.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:48.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:49.258 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:29:49.737 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:29:50.219 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:29:50.697 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:29:51.174 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:29:51.652 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:29:52.129 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:29:52.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:52.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:52.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:52.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:52.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:52.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:52.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:52.186 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:52.190 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:29:52.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:29:52.190 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:29:52.190 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:29:52.190 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:29:52.190 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:29:52.190 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2870 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2870 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2870 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2870 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2870 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2870 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2870 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2870 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2871 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2871 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2871 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2871 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2871 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2871 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2871 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:52.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2871 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:29:57.190 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:29:57.190 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:29:57.191 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:29:57.193 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:29:57.193 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:29:57.194 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:29:57.202 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:29:57.203 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:29:57.203 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:57.204 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:29:57.204 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:29:57.207 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:29:57.207 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:29:57.207 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:29:57.207 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:57.208 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:29:57.208 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:29:57.208 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:29:57.208 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:29:57.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:57.210 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:29:57.210 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:29:57.210 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:29:57.210 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:57.210 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:29:57.210 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:29:57.210 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:29:57.211 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:29:57.211 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:57.212 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:29:57.212 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:29:57.212 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:29:57.212 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:29:57.212 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:29:57.212 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:29:57.213 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:29:57.213 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:29:57.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:57.215 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:29:57.216 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:29:57.216 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:57.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:57.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:29:57.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:29:57.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:57.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:29:57.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:57.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:29:57.221 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:29:57.704 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:29:57.745 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:29:57.748 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:29:57.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:57.749 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:29:57.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:57.763 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:57.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:57.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:57.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:57.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:57.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:57.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:57.781 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:57.781 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:57.781 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:57.781 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:57.795 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:57.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:57.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:57.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:58.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:58.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:58.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:58.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:58.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:58.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:58.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:58.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:58.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:58.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:58.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:58.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:58.149 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:58.149 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:58.149 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:58.149 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:58.174 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:58.174 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:58.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:58.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:58.181 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:29:58.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:58.218 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:58.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:58.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:58.659 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:29:58.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:58.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:58.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:58.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:58.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:58.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:58.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:58.694 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:29:58.694 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:29:58.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:29:58.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:29:58.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:58.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:58.695 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:58.695 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:29:58.695 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:29:58.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:29:58.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:29:58.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:58.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:29:59.136 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:29:59.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:29:59.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:29:59.220 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:29:59.224 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:29:59.614 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:30:00.091 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:30:00.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:00.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:00.221 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:00.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:00.569 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:30:01.046 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:30:01.222 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:01.222 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:01.222 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:01.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:01.524 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:30:01.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:01.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:01.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:01.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:01.694 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:01.694 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:01.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:01.700 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:01.700 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:01.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:01.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:01.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:01.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:01.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:01.702 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:01.702 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:01.705 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:01.705 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:01.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:01.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:02.001 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:30:02.222 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:02.223 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:02.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:02.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:02.478 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:30:02.957 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:30:03.435 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:30:03.913 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:30:04.391 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:30:04.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:04.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:04.713 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:04.713 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:04.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:04.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:04.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:04.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:04.727 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:30:04.727 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:30:04.727 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:30:04.727 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:30:04.727 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:30:04.727 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:30:04.727 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:30:04.727 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:04.727 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:04.727 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:04.727 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:04.727 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:04.727 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:04.727 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:09.727 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:30:09.727 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:30:09.728 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:30:09.730 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:30:09.731 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:30:09.731 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:30:09.739 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:30:09.741 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:30:09.742 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:09.742 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:30:09.742 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:30:09.747 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:30:09.748 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:30:09.748 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:30:09.748 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:09.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:30:09.749 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:30:09.749 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:30:09.750 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:30:09.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:09.751 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:30:09.751 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:30:09.751 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:30:09.751 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:09.751 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:30:09.751 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:30:09.751 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:30:09.751 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:30:09.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:09.754 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:30:09.754 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:30:09.754 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:30:09.754 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:09.754 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:30:09.754 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:30:09.754 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:30:09.754 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:30:09.754 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:09.757 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:30:09.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:30:09.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:30:09.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:30:09.757 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:09.758 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:30:09.758 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:30:09.758 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:30:09.758 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:09.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:09.763 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:30:10.248 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:30:10.296 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:30:10.299 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:30:10.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:10.301 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:30:10.328 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:10.328 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:10.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:10.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:10.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:10.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:10.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:10.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:10.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:10.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:10.360 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:10.360 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:10.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:10.387 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:10.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:10.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:10.726 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:30:10.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:10.763 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:10.764 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:10.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:11.203 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:30:11.681 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:30:11.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:11.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:11.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:11.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:11.730 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:11.730 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:11.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:11.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:11.737 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:11.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:11.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:11.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:11.738 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:11.738 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:11.739 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:11.739 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:11.764 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:11.764 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:11.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:11.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:11.773 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:11.773 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:11.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:11.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:12.159 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:30:12.637 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:30:12.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:12.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:12.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:12.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:13.116 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:30:13.594 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:30:13.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:13.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:13.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:13.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:13.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:13.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:13.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:13.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:13.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:13.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:13.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:13.947 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:13.947 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:13.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:13.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:13.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:13.949 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:13.949 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:13.949 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:13.949 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:13.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:13.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:13.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:13.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:14.072 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:30:14.549 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:30:14.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:14.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:14.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:14.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:15.026 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:30:15.504 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:30:15.982 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:30:16.459 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:30:16.937 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:30:17.415 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:30:17.893 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:30:18.371 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:30:18.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:18.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:18.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:18.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:18.848 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:30:18.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:18.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:18.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:18.862 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:18.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:18.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:18.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:18.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:18.863 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:18.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:18.863 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:18.863 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:18.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:18.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:18.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:18.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:19.326 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:30:19.803 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:30:20.281 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:30:20.759 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:30:21.237 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:30:21.714 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:30:22.192 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:30:22.671 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:30:23.149 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:30:23.626 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:30:23.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:23.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:23.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:23.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:23.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:23.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:23.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:23.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:23.795 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:30:23.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:30:23.796 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:30:23.796 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:30:23.796 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:30:23.796 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:30:23.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:30:23.797 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2996 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:23.797 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2996 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:23.797 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2996 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:23.797 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2996 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:23.797 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2996 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:23.797 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2996 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:23.797 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2996 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:28.795 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:30:28.796 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:30:28.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:30:28.799 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:30:28.799 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:30:28.800 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:30:28.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:30:28.803 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:30:28.803 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:28.803 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:30:28.803 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:30:28.804 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:30:28.804 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:30:28.804 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:30:28.805 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:28.805 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:30:28.805 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:30:28.805 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:30:28.806 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:30:28.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:28.806 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:30:28.806 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:30:28.806 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:30:28.806 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:28.807 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:30:28.807 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:30:28.807 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:30:28.807 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:30:28.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:28.808 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:30:28.808 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:30:28.808 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:30:28.808 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:28.809 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:30:28.809 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:30:28.809 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:30:28.809 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:30:28.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:28.811 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:30:28.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:30:28.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:30:28.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:30:28.811 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:30:28.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:30:28.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:30:28.812 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:30:28.812 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:30:28.812 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:28.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:28.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:28.817 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:30:29.300 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:30:29.341 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:30:29.344 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:30:29.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:29.346 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:30:29.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:29.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:29.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:29.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:29.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:29.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:29.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:29.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:29.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:29.393 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:29.393 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:29.393 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:29.439 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:29.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:29.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:29.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:29.778 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:30:29.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:29.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:29.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:29.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:30.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:30.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:30.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:30.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:30.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:30.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:30.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:30.090 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:30.090 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:30.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:30.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:30.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:30.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:30.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:30.092 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:30.092 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:30.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:30.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:30.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:30.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:30.253 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:30:30.731 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:30:30.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:30.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:30.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:30.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:31.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:31.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:31.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:31.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:31.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:31.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:31.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:31.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:31.056 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:31.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:31.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:31.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:31.058 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:31.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:31.058 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:31.058 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:31.104 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:31.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:31.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:31.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:31.208 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:30:31.686 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:30:31.818 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:31.818 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:31.818 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:31.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:32.164 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:30:32.641 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:30:32.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:32.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:32.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:32.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:33.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:33.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:33.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:33.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:33.055 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:33.055 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:33.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:33.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:33.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:33.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:33.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:33.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:33.063 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:33.063 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:33.063 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:33.063 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:33.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:33.112 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:33.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:33.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:33.118 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:30:33.595 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:30:33.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:33.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:33.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:33.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:34.073 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:30:34.550 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:30:35.028 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:30:35.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:35.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:35.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:35.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:35.123 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:35.123 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:35.123 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:35.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:35.124 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:30:35.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:30:35.124 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:30:35.124 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:30:35.124 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:30:35.124 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:30:35.124 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:30:40.127 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:30:40.127 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:30:40.129 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:30:40.131 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:30:40.131 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:30:40.131 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:30:40.139 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:30:40.139 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:30:40.139 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:40.140 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:30:40.140 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:30:40.142 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:30:40.142 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:30:40.142 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:30:40.143 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:40.143 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:30:40.143 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:30:40.144 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:30:40.144 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:30:40.144 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:40.144 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:30:40.144 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:30:40.144 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:30:40.145 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:40.145 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:30:40.145 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:30:40.145 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:30:40.145 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:30:40.145 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:40.147 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:30:40.147 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:30:40.147 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:30:40.147 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:40.147 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:30:40.147 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:30:40.147 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:30:40.147 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:30:40.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:40.149 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:30:40.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:30:40.150 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:30:40.150 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:30:40.150 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:30:40.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:40.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:40.155 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:30:40.639 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:30:40.680 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:30:40.682 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:30:40.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:40.685 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:30:40.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:40.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:40.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:40.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:40.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:40.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:40.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:40.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:40.723 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:40.723 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:40.723 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:40.723 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:40.730 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:40.730 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:40.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:40.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:41.116 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:30:41.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:41.153 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:41.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:41.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:41.594 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:30:42.072 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:30:42.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:42.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:42.155 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:42.159 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:42.550 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:30:43.028 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:30:43.154 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:43.155 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:43.156 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:43.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:43.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:43.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:43.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:43.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:43.193 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:43.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:43.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:43.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:43.199 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:43.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:43.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:43.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:43.200 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:43.200 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:43.200 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:43.200 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:43.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:43.209 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:43.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:43.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:43.505 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:30:43.983 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:30:44.155 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:44.155 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:44.157 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:44.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:44.461 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:30:44.940 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:30:45.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:45.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:45.157 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:45.162 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:45.418 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:30:45.897 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:30:45.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:45.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:45.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:45.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:45.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:45.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:45.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:45.987 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:45.987 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:45.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:45.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:45.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:45.989 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:45.989 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:45.989 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:45.989 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:46.034 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:46.034 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:46.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:46.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:46.373 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:30:46.851 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:30:47.328 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:30:47.806 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:30:48.284 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:30:48.762 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:30:49.240 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:30:49.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:49.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:49.400 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:49.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:49.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:49.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:49.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:49.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:49.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:49.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:49.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:49.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:49.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:49.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:49.426 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:49.426 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:49.474 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:49.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:49.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:49.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:49.715 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:30:50.192 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:30:50.670 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:30:51.148 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:30:51.626 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:30:52.104 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:30:52.582 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:30:52.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:52.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:52.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:52.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:52.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:52.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:52.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:52.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:52.917 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:30:52.917 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:30:52.917 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:30:52.917 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:30:52.917 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:30:52.917 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:30:52.918 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:30:52.918 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2726 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:52.918 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2726 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:52.918 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2726 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:52.918 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2726 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:52.918 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2726 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:52.918 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2726 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:52.918 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2726 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:30:57.917 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:30:57.917 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:30:57.918 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:30:57.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:30:57.921 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:30:57.921 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:30:57.930 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:30:57.931 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:30:57.931 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:57.932 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:30:57.932 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:30:57.937 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:30:57.937 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:30:57.937 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:30:57.937 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:57.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:30:57.937 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:30:57.938 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:30:57.938 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:30:57.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:57.941 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:30:57.941 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:30:57.941 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:30:57.941 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:57.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:30:57.941 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:30:57.941 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:30:57.941 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:30:57.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:57.944 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:30:57.944 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:30:57.944 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:30:57.944 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:30:57.944 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:30:57.944 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:30:57.944 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:30:57.944 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:30:57.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:57.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:57.949 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:30:57.949 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:30:57.949 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:30:57.949 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:30:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:57.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:30:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:57.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:57.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:57.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:30:57.954 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:30:58.437 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:30:58.476 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:30:58.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:58.479 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:30:58.481 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:30:58.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:58.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:58.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:58.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:58.529 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:58.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:58.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:58.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:58.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:58.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:58.535 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:58.535 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:58.575 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:58.575 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:58.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:58.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:58.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:58.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:58.796 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:58.796 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:58.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:58.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:58.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:58.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:58.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:58.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:58.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:58.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:58.822 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:58.822 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:58.822 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:58.822 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:58.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:58.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:58.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:58.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:58.914 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:30:58.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:58.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:58.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:58.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:30:59.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:59.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:59.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:59.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:59.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:59.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:59.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:59.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:59.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:59.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:59.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:59.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:59.224 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:59.224 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:59.224 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:59.224 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:59.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:59.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:59.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:59.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:59.390 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:30:59.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:59.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:59.786 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:59.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:59.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:59.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:59.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:59.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:30:59.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:30:59.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:30:59.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:30:59.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:59.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:59.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:59.803 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:30:59.803 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:30:59.807 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:30:59.807 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:30:59.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:59.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:30:59.867 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:30:59.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:30:59.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:30:59.955 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:30:59.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:31:00.345 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:31:00.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:31:00.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:31:00.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:31:00.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:31:00.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:31:00.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:31:00.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:31:00.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:31:00.446 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:31:00.447 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:31:00.447 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:31:00.447 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:31:00.447 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:31:00.447 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:31:00.447 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:31:00.447 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=534 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:31:00.447 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=534 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:31:00.448 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=534 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:31:00.448 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=534 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:31:00.448 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=534 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:31:00.448 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=534 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:31:00.448 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=534 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:31:00.448 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=534 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:31:05.445 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:31:05.446 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:31:05.447 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:31:05.448 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:31:05.448 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:31:05.449 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:31:05.457 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:31:05.458 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:31:05.458 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:31:05.459 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:31:05.459 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:31:05.462 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:31:05.462 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:31:05.462 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:31:05.462 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:31:05.463 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:31:05.463 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:31:05.463 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:31:05.463 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:31:05.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:31:05.465 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:31:05.465 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:31:05.465 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:31:05.466 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:31:05.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:31:05.466 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:31:05.466 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:31:05.466 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:31:05.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:31:05.469 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:31:05.469 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:31:05.469 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:31:05.469 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:31:05.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:31:05.470 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:31:05.470 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:31:05.470 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:31:05.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:31:05.474 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:31:05.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:31:05.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:31:05.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:31:05.474 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:31:05.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:31:05.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:31:05.475 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:31:05.475 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:31:05.475 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:31:05.475 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:31:05.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:31:05.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:31:05.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:31:05.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:31:05.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:31:05.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:31:05.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:31:05.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:31:05.476 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:31:05.476 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:31:05.476 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:31:05.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:31:05.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:31:05.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:31:05.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:31:05.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:31:05.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:31:05.477 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:31:05.477 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:31:05.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:31:05.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:31:05.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:31:05.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:31:05.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:31:05.480 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:31:05.962 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:31:06.004 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:31:06.004 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:31:06.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:31:06.006 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:31:06.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:31:06.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:31:06.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:31:06.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:31:06.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:31:06.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:31:06.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:31:06.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:31:06.043 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:31:06.043 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:31:06.043 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:31:06.043 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:31:06.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:31:06.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:31:06.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:31:06.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:31:06.440 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:31:06.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:31:06.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:31:06.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:31:06.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:31:06.918 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:31:07.395 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:31:07.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:31:07.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:31:07.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:31:07.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:31:07.873 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:31:08.351 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:31:08.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:31:08.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:31:08.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:31:08.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:31:08.828 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:31:09.306 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:31:09.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:31:09.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:31:09.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:31:09.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:31:09.784 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:31:10.262 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:31:10.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:31:10.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:31:10.484 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:31:10.488 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:31:10.740 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:31:11.218 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:31:11.696 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:31:12.173 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:31:12.650 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:31:13.128 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:31:13.606 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:31:14.085 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:31:14.563 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:31:15.041 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:31:15.519 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:31:15.997 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:31:16.475 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:31:16.953 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:31:17.431 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:31:17.909 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:31:18.387 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:31:18.865 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:31:19.342 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:31:19.820 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:31:20.298 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:31:20.777 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:31:21.255 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:31:21.733 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:31:22.211 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:31:22.689 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:31:23.166 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:31:23.643 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:31:24.121 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:31:24.599 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:31:25.077 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:31:25.555 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:31:26.033 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:31:26.511 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:31:26.989 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:31:27.467 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:31:27.945 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:31:28.423 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:31:28.901 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:31:29.380 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:31:29.858 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:31:30.336 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:31:30.813 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:31:31.290 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:31:31.768 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:31:32.246 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:31:32.724 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:31:33.202 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:31:33.680 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:31:34.158 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:31:34.636 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:31:35.114 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 02:31:35.591 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 02:31:36.069 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 02:31:36.546 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 02:31:37.024 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 02:31:37.502 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 02:31:37.980 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 02:31:38.457 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 02:31:38.935 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 02:31:39.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:31:39.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:31:39.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:31:39.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:31:39.077 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:31:39.077 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:31:39.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:31:39.082 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:31:39.082 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:31:39.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:31:39.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:31:39.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:31:39.084 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:31:39.084 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:31:39.084 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:31:39.084 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:31:39.120 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:31:39.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:31:39.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:31:39.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:31:39.411 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 02:31:39.889 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 02:31:40.367 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 02:31:40.845 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 02:31:41.324 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 02:31:41.801 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 02:31:42.280 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 02:31:42.758 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 02:31:43.236 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 02:31:43.714 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 02:31:44.193 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 02:31:44.671 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 02:31:45.149 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 02:31:45.627 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 02:31:46.106 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 02:31:46.584 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 02:31:47.062 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 02:31:47.541 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 02:31:48.019 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 02:31:48.496 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 02:31:48.974 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 02:31:49.452 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 02:31:49.930 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 02:31:50.409 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 02:31:50.887 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 02:31:51.365 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 02:31:51.843 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 02:31:52.321 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 02:31:52.800 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 02:31:53.278 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 02:31:53.755 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 02:31:54.234 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 02:31:54.711 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 02:31:55.189 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 02:31:55.667 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 02:31:56.144 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 02:31:56.622 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 02:31:57.101 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 02:31:57.578 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 02:31:58.056 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 02:31:58.534 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 02:31:59.012 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 02:31:59.491 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 02:31:59.969 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 02:32:00.447 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 02:32:00.925 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 02:32:01.404 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 02:32:01.882 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 02:32:02.360 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 02:32:02.838 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 02:32:03.316 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 02:32:03.794 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 02:32:04.272 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 02:32:04.750 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 02:32:05.228 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 02:32:05.706 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 02:32:06.184 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-05 02:32:06.662 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-05 02:32:07.140 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-05 02:32:07.618 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-05 02:32:08.096 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-05 02:32:08.574 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-05 02:32:09.052 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-05 02:32:09.530 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-05 02:32:10.007 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-05 02:32:10.486 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-05 02:32:10.964 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-05 02:32:11.442 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-05 02:32:11.920 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-05 02:32:12.398 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-05 02:32:12.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:32:12.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:32:12.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:32:12.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:32:12.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:32:12.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:32:12.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:32:12.797 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:32:12.797 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:32:12.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:32:12.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:32:12.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:32:12.799 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:32:12.799 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:32:12.799 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:32:12.799 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:32:12.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:32:12.816 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:32:12.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:32:12.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:32:12.875 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-05 02:32:13.353 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-05 02:32:13.831 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-05 02:32:14.309 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-05 02:32:14.787 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-05 02:32:15.264 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-05 02:32:15.742 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-05 02:32:16.219 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-05 02:32:16.697 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-05 02:32:17.175 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-05 02:32:17.653 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-05 02:32:18.130 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-05 02:32:18.608 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-05 02:32:19.086 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-05 02:32:19.564 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-05 02:32:20.041 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-05 02:32:20.519 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-05 02:32:21.000 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-05 02:32:21.478 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-05 02:32:21.955 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-05 02:32:22.433 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-05 02:32:22.911 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-05 02:32:23.388 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-05 02:32:23.866 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-05 02:32:24.344 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-05 02:32:24.822 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-05 02:32:25.300 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-05 02:32:25.778 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-05 02:32:26.256 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-05 02:32:26.733 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-05 02:32:27.211 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-05 02:32:27.688 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-05 02:32:28.166 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-05 02:32:28.644 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-05 02:32:29.122 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-05 02:32:29.599 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-05 02:32:30.077 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-05 02:32:30.555 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-05 02:32:31.033 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-05 02:32:31.511 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-05 02:32:31.989 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-05 02:32:32.466 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-05 02:32:32.944 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-05 02:32:33.422 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-05 02:32:33.900 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-05 02:32:34.377 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-05 02:32:34.855 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-05 02:32:35.332 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-05 02:32:35.810 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-05 02:32:36.288 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-05 02:32:36.765 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-05 02:32:37.243 [DEBUG] clck_gen.py:113 IND CLOCK 19584
2026-03-05 02:32:37.721 [DEBUG] clck_gen.py:113 IND CLOCK 19686
2026-03-05 02:32:38.199 [DEBUG] clck_gen.py:113 IND CLOCK 19788
2026-03-05 02:32:38.676 [DEBUG] clck_gen.py:113 IND CLOCK 19890
2026-03-05 02:32:39.154 [DEBUG] clck_gen.py:113 IND CLOCK 19992
2026-03-05 02:32:39.632 [DEBUG] clck_gen.py:113 IND CLOCK 20094
2026-03-05 02:32:40.110 [DEBUG] clck_gen.py:113 IND CLOCK 20196
2026-03-05 02:32:40.588 [DEBUG] clck_gen.py:113 IND CLOCK 20298
2026-03-05 02:32:41.066 [DEBUG] clck_gen.py:113 IND CLOCK 20400
2026-03-05 02:32:41.544 [DEBUG] clck_gen.py:113 IND CLOCK 20502
2026-03-05 02:32:42.022 [DEBUG] clck_gen.py:113 IND CLOCK 20604
2026-03-05 02:32:42.500 [DEBUG] clck_gen.py:113 IND CLOCK 20706
2026-03-05 02:32:42.977 [DEBUG] clck_gen.py:113 IND CLOCK 20808
2026-03-05 02:32:43.455 [DEBUG] clck_gen.py:113 IND CLOCK 20910
2026-03-05 02:32:43.933 [DEBUG] clck_gen.py:113 IND CLOCK 21012
2026-03-05 02:32:44.410 [DEBUG] clck_gen.py:113 IND CLOCK 21114
2026-03-05 02:32:44.888 [DEBUG] clck_gen.py:113 IND CLOCK 21216
2026-03-05 02:32:45.366 [DEBUG] clck_gen.py:113 IND CLOCK 21318
2026-03-05 02:32:45.844 [DEBUG] clck_gen.py:113 IND CLOCK 21420
2026-03-05 02:32:46.321 [DEBUG] clck_gen.py:113 IND CLOCK 21522
2026-03-05 02:32:46.800 [DEBUG] clck_gen.py:113 IND CLOCK 21624
2026-03-05 02:32:47.278 [DEBUG] clck_gen.py:113 IND CLOCK 21726
2026-03-05 02:32:47.756 [DEBUG] clck_gen.py:113 IND CLOCK 21828
2026-03-05 02:32:48.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:32:48.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:32:48.156 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:32:48.156 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:32:48.169 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:32:48.169 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:32:48.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:32:48.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:32:48.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:32:48.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:32:48.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:32:48.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:32:48.177 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:32:48.177 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:32:48.177 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:32:48.177 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:32:48.226 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:32:48.226 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:32:48.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:32:48.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:32:48.233 [DEBUG] clck_gen.py:113 IND CLOCK 21930
2026-03-05 02:32:48.710 [DEBUG] clck_gen.py:113 IND CLOCK 22032
2026-03-05 02:32:49.188 [DEBUG] clck_gen.py:113 IND CLOCK 22134
2026-03-05 02:32:49.666 [DEBUG] clck_gen.py:113 IND CLOCK 22236
2026-03-05 02:32:50.144 [DEBUG] clck_gen.py:113 IND CLOCK 22338
2026-03-05 02:32:50.621 [DEBUG] clck_gen.py:113 IND CLOCK 22440
2026-03-05 02:32:51.099 [DEBUG] clck_gen.py:113 IND CLOCK 22542
2026-03-05 02:32:51.577 [DEBUG] clck_gen.py:113 IND CLOCK 22644
2026-03-05 02:32:52.055 [DEBUG] clck_gen.py:113 IND CLOCK 22746
2026-03-05 02:32:52.533 [DEBUG] clck_gen.py:113 IND CLOCK 22848
2026-03-05 02:32:53.011 [DEBUG] clck_gen.py:113 IND CLOCK 22950
2026-03-05 02:32:53.489 [DEBUG] clck_gen.py:113 IND CLOCK 23052
2026-03-05 02:32:53.967 [DEBUG] clck_gen.py:113 IND CLOCK 23154
2026-03-05 02:32:54.445 [DEBUG] clck_gen.py:113 IND CLOCK 23256
2026-03-05 02:32:54.923 [DEBUG] clck_gen.py:113 IND CLOCK 23358
2026-03-05 02:32:55.401 [DEBUG] clck_gen.py:113 IND CLOCK 23460
2026-03-05 02:32:55.878 [DEBUG] clck_gen.py:113 IND CLOCK 23562
2026-03-05 02:32:56.356 [DEBUG] clck_gen.py:113 IND CLOCK 23664
2026-03-05 02:32:56.834 [DEBUG] clck_gen.py:113 IND CLOCK 23766
2026-03-05 02:32:57.312 [DEBUG] clck_gen.py:113 IND CLOCK 23868
2026-03-05 02:32:57.789 [DEBUG] clck_gen.py:113 IND CLOCK 23970
2026-03-05 02:32:58.268 [DEBUG] clck_gen.py:113 IND CLOCK 24072
2026-03-05 02:32:58.746 [DEBUG] clck_gen.py:113 IND CLOCK 24174
2026-03-05 02:32:59.225 [DEBUG] clck_gen.py:113 IND CLOCK 24276
2026-03-05 02:32:59.703 [DEBUG] clck_gen.py:113 IND CLOCK 24378
2026-03-05 02:33:00.181 [DEBUG] clck_gen.py:113 IND CLOCK 24480
2026-03-05 02:33:00.659 [DEBUG] clck_gen.py:113 IND CLOCK 24582
2026-03-05 02:33:01.138 [DEBUG] clck_gen.py:113 IND CLOCK 24684
2026-03-05 02:33:01.616 [DEBUG] clck_gen.py:113 IND CLOCK 24786
2026-03-05 02:33:02.093 [DEBUG] clck_gen.py:113 IND CLOCK 24888
2026-03-05 02:33:02.571 [DEBUG] clck_gen.py:113 IND CLOCK 24990
2026-03-05 02:33:03.049 [DEBUG] clck_gen.py:113 IND CLOCK 25092
2026-03-05 02:33:03.528 [DEBUG] clck_gen.py:113 IND CLOCK 25194
2026-03-05 02:33:04.006 [DEBUG] clck_gen.py:113 IND CLOCK 25296
2026-03-05 02:33:04.484 [DEBUG] clck_gen.py:113 IND CLOCK 25398
2026-03-05 02:33:04.962 [DEBUG] clck_gen.py:113 IND CLOCK 25500
2026-03-05 02:33:05.439 [DEBUG] clck_gen.py:113 IND CLOCK 25602
2026-03-05 02:33:05.917 [DEBUG] clck_gen.py:113 IND CLOCK 25704
2026-03-05 02:33:06.396 [DEBUG] clck_gen.py:113 IND CLOCK 25806
2026-03-05 02:33:06.874 [DEBUG] clck_gen.py:113 IND CLOCK 25908
2026-03-05 02:33:07.352 [DEBUG] clck_gen.py:113 IND CLOCK 26010
2026-03-05 02:33:07.830 [DEBUG] clck_gen.py:113 IND CLOCK 26112
2026-03-05 02:33:08.308 [DEBUG] clck_gen.py:113 IND CLOCK 26214
2026-03-05 02:33:08.785 [DEBUG] clck_gen.py:113 IND CLOCK 26316
2026-03-05 02:33:09.263 [DEBUG] clck_gen.py:113 IND CLOCK 26418
2026-03-05 02:33:09.741 [DEBUG] clck_gen.py:113 IND CLOCK 26520
2026-03-05 02:33:10.220 [DEBUG] clck_gen.py:113 IND CLOCK 26622
2026-03-05 02:33:10.698 [DEBUG] clck_gen.py:113 IND CLOCK 26724
2026-03-05 02:33:11.176 [DEBUG] clck_gen.py:113 IND CLOCK 26826
2026-03-05 02:33:11.654 [DEBUG] clck_gen.py:113 IND CLOCK 26928
2026-03-05 02:33:12.128 [DEBUG] clck_gen.py:113 IND CLOCK 27030
2026-03-05 02:33:12.604 [DEBUG] clck_gen.py:113 IND CLOCK 27132
2026-03-05 02:33:13.082 [DEBUG] clck_gen.py:113 IND CLOCK 27234
2026-03-05 02:33:13.560 [DEBUG] clck_gen.py:113 IND CLOCK 27336
2026-03-05 02:33:14.038 [DEBUG] clck_gen.py:113 IND CLOCK 27438
2026-03-05 02:33:14.515 [DEBUG] clck_gen.py:113 IND CLOCK 27540
2026-03-05 02:33:14.994 [DEBUG] clck_gen.py:113 IND CLOCK 27642
2026-03-05 02:33:15.472 [DEBUG] clck_gen.py:113 IND CLOCK 27744
2026-03-05 02:33:15.950 [DEBUG] clck_gen.py:113 IND CLOCK 27846
2026-03-05 02:33:16.428 [DEBUG] clck_gen.py:113 IND CLOCK 27948
2026-03-05 02:33:16.906 [DEBUG] clck_gen.py:113 IND CLOCK 28050
2026-03-05 02:33:17.384 [DEBUG] clck_gen.py:113 IND CLOCK 28152
2026-03-05 02:33:17.861 [DEBUG] clck_gen.py:113 IND CLOCK 28254
2026-03-05 02:33:18.339 [DEBUG] clck_gen.py:113 IND CLOCK 28356
2026-03-05 02:33:18.817 [DEBUG] clck_gen.py:113 IND CLOCK 28458
2026-03-05 02:33:19.294 [DEBUG] clck_gen.py:113 IND CLOCK 28560
2026-03-05 02:33:19.772 [DEBUG] clck_gen.py:113 IND CLOCK 28662
2026-03-05 02:33:20.251 [DEBUG] clck_gen.py:113 IND CLOCK 28764
2026-03-05 02:33:20.729 [DEBUG] clck_gen.py:113 IND CLOCK 28866
2026-03-05 02:33:21.207 [DEBUG] clck_gen.py:113 IND CLOCK 28968
2026-03-05 02:33:21.684 [DEBUG] clck_gen.py:113 IND CLOCK 29070
2026-03-05 02:33:22.162 [DEBUG] clck_gen.py:113 IND CLOCK 29172
2026-03-05 02:33:22.639 [DEBUG] clck_gen.py:113 IND CLOCK 29274
2026-03-05 02:33:23.117 [DEBUG] clck_gen.py:113 IND CLOCK 29376
2026-03-05 02:33:23.594 [DEBUG] clck_gen.py:113 IND CLOCK 29478
2026-03-05 02:33:23.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:23.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:33:23.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:23.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:23.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:23.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:23.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:23.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:23.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:33:23.697 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:33:23.697 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:33:23.697 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:33:23.697 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:33:23.697 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:33:23.697 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:33:23.697 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=29502 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:33:23.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=29502 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:33:23.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=29502 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:33:23.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=29502 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:33:23.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=29502 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:33:23.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=29502 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:33:23.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=29502 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:33:28.697 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:33:28.698 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:33:28.699 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:33:28.701 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:33:28.701 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:33:28.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:33:28.705 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:33:28.705 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:33:28.705 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:33:28.705 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:33:28.705 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:33:28.706 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:33:28.706 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:33:28.706 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:33:28.707 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:33:28.707 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:33:28.707 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:33:28.707 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:33:28.707 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:33:28.708 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:28.708 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:33:28.708 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:33:28.708 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:33:28.708 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:33:28.708 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:33:28.708 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:33:28.709 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:33:28.709 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:33:28.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:28.710 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:33:28.710 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:33:28.710 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:33:28.710 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:33:28.710 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:33:28.711 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:33:28.711 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:33:28.711 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:33:28.711 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:28.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:28.714 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:28.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:28.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:28.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:28.714 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:33:28.714 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:33:28.714 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:33:28.714 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:33:28.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:28.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:28.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:28.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:33:28.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:28.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:28.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:28.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:33:28.715 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:33:28.715 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:33:28.715 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:33:33.722 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:33:33.722 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:33:33.722 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:33:33.723 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:33:33.723 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:33:33.723 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:33:33.731 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:33:33.733 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:33:33.733 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:33:33.734 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:33:33.734 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:33:33.737 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:33:33.738 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:33:33.738 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:33:33.738 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:33:33.739 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:33:33.739 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:33:33.740 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:33:33.740 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:33:33.740 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:33.741 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:33:33.741 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:33:33.742 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:33:33.742 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:33:33.742 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:33:33.742 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:33:33.742 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:33:33.743 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:33:33.743 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:33.744 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:33:33.744 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:33:33.744 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:33:33.744 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:33:33.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:33:33.745 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:33:33.745 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:33:33.745 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:33:33.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:33.748 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:33:33.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:33:33.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:33:33.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:33:33.748 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:33:33.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:33:33.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:33:33.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:33:33.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:33:33.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:33.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:33.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:33.748 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:33:33.749 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:33:33.749 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:33:33.749 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:33.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:33.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:33.754 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:33:34.238 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:33:34.277 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:33:34.279 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:33:34.281 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:33:34.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:33:34.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:34.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:34.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:33:34.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:34.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:34.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:33:34.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:33:34.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:34.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:33:34.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:33:34.322 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:33:34.322 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:33:34.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:33:34.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:33:34.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:34.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:34.715 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:33:34.751 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:34.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:34.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:34.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:35.193 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:33:35.671 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:33:35.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:35.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:35.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:35.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:35.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:35.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:33:35.781 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:35.781 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:35.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:35.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:35.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:33:35.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:35.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:35.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:33:35.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:33:35.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:35.806 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:33:35.806 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:33:35.806 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:33:35.806 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:33:35.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:33:35.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:33:35.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:35.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:36.147 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:33:36.626 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:33:36.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:36.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:36.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:36.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:37.104 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:33:37.582 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:33:37.754 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:37.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:37.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:37.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:38.061 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:33:38.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:38.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:33:38.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:38.135 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:38.154 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:38.154 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:38.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:33:38.160 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:38.160 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:38.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:33:38.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:33:38.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:38.161 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:33:38.161 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:33:38.161 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:33:38.161 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:33:38.199 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:33:38.199 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:33:38.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:38.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:38.538 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:33:38.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:38.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:38.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:38.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:39.016 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:33:39.494 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:33:39.972 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:33:40.450 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:33:40.928 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:33:41.405 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:33:41.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:41.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:33:41.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:41.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:41.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:41.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:41.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:33:41.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:41.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:41.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:33:41.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:33:41.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:41.592 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:33:41.592 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:33:41.592 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:33:41.592 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:33:41.640 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:33:41.640 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:33:41.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:41.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:41.882 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:33:42.361 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:33:42.839 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:33:43.317 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:33:43.796 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:33:44.273 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:33:44.751 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:33:45.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:45.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:33:45.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:45.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:45.084 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:45.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:45.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:45.085 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:45.087 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:33:45.087 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:33:45.087 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:33:45.087 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:33:45.087 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:33:45.087 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:33:45.087 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:33:50.091 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:33:50.091 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:33:50.091 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:33:50.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:33:50.091 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:33:50.091 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:33:50.094 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:33:50.094 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:33:50.094 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:33:50.095 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:33:50.095 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:33:50.097 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:33:50.097 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:33:50.097 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:33:50.097 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:33:50.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:33:50.098 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:33:50.098 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:33:50.098 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:33:50.099 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:50.099 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:33:50.100 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:33:50.100 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:33:50.100 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:33:50.100 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:33:50.100 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:33:50.101 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:33:50.101 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:33:50.101 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:50.102 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:33:50.102 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:33:50.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:33:50.102 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:33:50.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:33:50.102 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:33:50.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:33:50.102 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:33:50.103 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:50.105 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:33:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:33:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:33:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:33:50.105 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:33:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:33:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:33:50.106 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:33:50.106 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:33:50.106 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:50.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:33:50.111 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:33:50.595 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:33:50.637 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:33:50.639 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:33:50.640 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:33:50.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:33:50.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:50.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:50.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:33:50.676 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:33:50.676 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:33:50.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:33:50.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:33:50.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:50.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:33:50.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:33:50.686 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:33:50.686 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:33:50.734 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:33:50.734 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:33:50.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:50.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:33:51.073 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:33:51.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:51.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:51.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:51.114 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:51.551 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:33:52.029 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:33:52.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:52.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:52.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:52.115 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:52.507 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:33:52.984 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:33:53.112 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:53.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:53.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:53.115 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:53.462 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:33:53.940 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:33:54.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:54.114 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:54.114 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:54.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:54.418 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:33:54.896 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:33:55.114 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:33:55.114 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:33:55.114 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:33:55.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:33:55.374 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:33:55.852 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:33:56.329 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:33:56.807 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:33:57.285 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:33:57.763 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:33:58.241 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:33:58.719 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:33:59.197 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:33:59.675 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:34:00.153 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:34:00.631 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:34:01.109 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:34:01.587 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:34:02.065 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:34:02.542 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:34:03.020 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:34:03.498 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:34:03.976 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:34:04.454 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:34:04.931 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:34:05.409 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:34:05.887 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:34:06.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:34:06.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:34:06.186 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:34:06.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:34:06.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:34:06.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:34:06.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:34:06.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:34:06.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:34:06.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:34:06.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:34:06.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:34:06.214 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:34:06.214 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:34:06.214 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:34:06.214 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:34:06.260 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:34:06.260 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:34:06.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:34:06.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:34:06.362 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:34:06.839 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:34:07.318 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:34:07.796 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:34:08.274 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:34:08.752 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:34:09.230 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:34:09.708 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:34:10.186 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:34:10.664 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:34:11.143 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:34:11.621 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:34:12.099 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:34:12.577 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:34:13.055 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:34:13.533 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:34:14.011 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:34:14.489 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:34:14.968 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:34:15.446 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:34:15.924 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:34:16.403 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:34:16.881 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:34:17.359 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:34:17.838 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:34:18.316 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:34:18.794 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:34:19.272 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:34:19.750 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 02:34:20.228 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 02:34:20.706 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 02:34:21.184 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 02:34:21.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:34:21.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:34:21.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:34:21.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:34:21.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:34:21.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:34:21.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:34:21.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:34:21.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:34:21.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:34:21.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:34:21.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:34:21.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:34:21.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:34:21.567 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:34:21.567 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:34:21.603 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:34:21.604 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:34:21.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:34:21.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:34:21.661 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 02:34:22.139 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 02:34:22.616 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 02:34:23.094 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 02:34:23.571 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 02:34:24.049 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 02:34:24.527 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 02:34:25.005 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 02:34:25.482 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 02:34:25.960 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 02:34:26.438 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 02:34:26.915 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 02:34:27.393 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 02:34:27.870 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 02:34:28.348 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 02:34:28.826 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 02:34:29.304 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 02:34:29.781 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 02:34:30.260 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 02:34:30.738 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 02:34:31.215 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 02:34:31.693 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 02:34:32.171 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 02:34:32.649 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 02:34:33.127 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 02:34:33.605 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 02:34:34.083 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 02:34:34.560 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 02:34:35.038 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 02:34:35.516 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 02:34:35.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:34:35.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:34:35.958 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:34:35.958 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:34:35.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:34:35.978 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:34:35.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:34:35.984 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:34:35.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:34:35.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:34:35.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:34:35.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:34:35.985 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:34:35.985 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:34:35.985 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:34:35.985 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:34:35.992 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 02:34:36.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:34:36.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:34:36.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:34:36.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:34:36.469 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 02:34:36.947 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 02:34:37.425 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 02:34:37.902 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 02:34:38.380 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 02:34:38.858 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 02:34:39.336 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 02:34:39.813 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 02:34:40.291 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 02:34:40.770 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 02:34:41.247 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 02:34:41.725 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 02:34:42.202 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 02:34:42.680 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 02:34:43.158 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 02:34:43.635 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 02:34:44.113 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 02:34:44.591 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 02:34:45.070 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 02:34:45.548 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 02:34:46.025 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 02:34:46.504 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 02:34:46.982 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 02:34:47.461 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 02:34:47.939 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 02:34:48.418 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 02:34:48.896 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 02:34:49.375 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 02:34:49.853 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 02:34:50.331 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 02:34:50.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:34:50.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:34:50.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:34:50.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:34:50.740 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:34:50.741 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:34:50.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:34:50.741 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:34:50.744 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:34:50.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:34:50.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:34:50.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:34:50.745 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:34:50.745 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:34:50.745 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:34:50.746 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=12943 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:34:50.746 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=12943 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:34:50.746 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=12943 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:34:50.746 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=12943 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:34:50.746 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=12943 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:34:50.746 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=12943 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:34:55.743 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:34:55.743 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:34:55.744 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:34:55.746 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:34:55.747 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:34:55.747 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:34:55.750 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:34:55.751 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:34:55.751 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:34:55.752 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:34:55.752 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:34:55.754 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:34:55.755 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:34:55.755 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:34:55.755 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:34:55.755 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:34:55.755 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:34:55.756 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:34:55.756 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:34:55.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:34:55.757 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:34:55.757 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:34:55.757 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:34:55.757 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:34:55.757 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:34:55.757 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:34:55.757 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:34:55.757 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:34:55.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:34:55.759 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:34:55.759 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:34:55.759 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:34:55.759 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:34:55.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:34:55.760 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:34:55.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:34:55.760 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:34:55.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:34:55.762 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:34:55.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:34:55.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:34:55.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:34:55.762 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:34:55.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:34:55.763 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:34:55.763 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:34:55.763 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:34:55.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:34:55.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:34:55.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:34:55.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:34:55.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:34:55.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:34:55.765 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:34:55.765 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:34:55.765 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:35:00.769 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:35:00.769 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:35:00.770 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:35:00.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:35:00.772 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:35:00.772 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:35:00.779 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:35:00.780 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:35:00.780 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:35:00.780 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:35:00.780 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:35:00.783 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:35:00.783 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:35:00.784 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:35:00.784 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:35:00.784 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:35:00.784 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:35:00.784 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:35:00.784 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:35:00.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:00.789 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:35:00.789 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:35:00.789 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:35:00.789 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:35:00.789 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:35:00.789 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:35:00.789 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:35:00.789 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:35:00.789 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:00.791 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:35:00.791 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:35:00.791 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:35:00.791 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:35:00.791 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:35:00.791 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:35:00.791 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:35:00.791 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:35:00.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:00.795 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:35:00.795 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:35:00.795 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:35:00.796 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:00.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:00.800 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:35:01.285 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:35:01.326 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:35:01.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:01.330 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:35:01.332 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:35:01.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:01.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:01.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:01.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:01.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:01.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:01.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:01.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:01.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:01.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:01.383 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:35:01.383 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:35:01.423 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:01.423 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:01.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:01.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:01.761 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:35:01.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:01.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:01.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:01.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:02.239 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:35:02.717 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:35:02.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:02.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:02.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:02.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:03.195 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:35:03.673 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:35:03.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:03.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:03.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:03.805 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:04.151 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:35:04.629 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:35:04.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:04.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:04.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:04.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:05.107 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:35:05.585 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:35:05.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:05.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:05.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:05.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:06.064 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:35:06.542 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:35:07.020 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:35:07.498 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:35:07.976 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:35:08.454 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:35:08.931 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:35:09.409 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:35:09.887 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:35:10.365 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:35:10.843 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:35:11.321 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:35:11.799 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:35:12.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:12.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:12.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:12.007 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:12.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:12.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:12.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:12.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:12.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:12.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:12.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:12.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:12.030 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:12.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:12.030 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:35:12.030 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:35:12.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:12.080 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:12.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:12.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:12.275 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:35:12.753 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:35:13.230 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:35:13.707 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:35:14.185 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:35:14.664 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:35:15.142 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:35:15.620 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:35:16.098 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:35:16.576 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:35:17.054 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:35:17.532 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:35:18.010 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:35:18.489 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:35:18.967 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:35:19.445 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:35:19.924 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:35:20.402 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:35:20.880 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:35:21.358 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:35:21.836 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:35:22.314 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:35:22.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:22.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:22.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:22.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:22.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:22.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:22.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:22.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:22.510 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:22.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:22.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:22.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:22.512 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:22.512 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:22.512 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:35:22.512 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:35:22.548 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:22.548 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:22.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:22.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:22.787 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:35:23.264 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:35:23.742 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:35:24.220 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:35:24.697 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:35:25.175 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:35:25.652 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:35:26.130 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:35:26.608 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:35:27.086 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:35:27.563 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:35:28.040 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:35:28.517 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:35:28.995 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:35:29.473 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:35:29.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:29.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:29.516 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:29.516 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:29.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:29.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:29.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:29.541 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:29.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:29.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:29.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:29.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:29.542 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:29.542 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:29.542 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:35:29.542 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:35:29.564 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:29.564 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:29.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:29.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:29.950 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:35:30.428 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 02:35:30.906 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 02:35:31.384 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 02:35:31.863 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 02:35:32.340 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 02:35:32.818 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 02:35:33.296 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 02:35:33.775 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 02:35:34.253 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 02:35:34.731 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 02:35:35.209 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 02:35:35.687 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 02:35:36.164 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 02:35:36.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:36.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:36.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:36.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:36.642 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 02:35:36.647 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:36.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:36.647 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:36.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:36.650 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:35:36.650 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:35:36.650 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:35:36.650 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:35:36.650 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:35:36.651 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:35:36.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:35:41.650 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:35:41.650 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:35:41.652 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:35:41.653 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:35:41.653 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:35:41.654 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:35:41.656 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:35:41.656 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:35:41.656 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:35:41.657 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:35:41.657 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:35:41.657 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:35:41.657 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:35:41.657 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:35:41.657 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:35:41.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:35:41.658 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:35:41.658 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:35:41.658 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:35:41.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:41.659 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:35:41.659 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:35:41.659 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:35:41.659 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:35:41.660 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:35:41.660 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:35:41.660 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:35:41.660 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:35:41.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:41.661 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:35:41.661 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:35:41.661 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:35:41.661 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:35:41.661 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:35:41.661 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:35:41.662 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:35:41.662 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:35:41.662 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:35:41.664 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:35:41.664 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:35:41.664 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:41.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:41.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:41.669 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:35:42.152 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:35:42.190 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:35:42.192 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:35:42.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:42.193 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:35:42.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:42.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:42.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:42.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:42.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:42.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:42.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:42.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:42.241 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:42.242 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:42.242 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:35:42.242 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:35:42.289 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:42.290 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:42.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:42.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:42.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:42.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:42.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:42.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:42.622 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:35:42.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:42.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:42.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:42.639 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:42.639 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:42.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:42.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:42.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:42.641 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:42.641 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:42.641 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:35:42.641 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:35:42.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:42.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:42.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:42.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:42.667 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:42.667 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:42.668 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:42.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:43.095 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:35:43.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:43.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:43.154 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:43.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:43.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:43.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:43.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:43.180 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:43.180 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:43.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:43.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:43.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:43.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:43.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:43.182 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:35:43.182 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:35:43.183 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:43.183 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:43.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:43.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:43.572 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:35:43.667 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:43.667 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:43.669 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:43.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:43.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:43.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:43.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:43.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:43.988 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:43.988 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:43.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:43.995 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:43.995 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:43.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:43.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:43.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:43.996 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:43.996 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:43.996 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:35:43.996 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:35:44.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:44.042 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:44.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:44.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:44.049 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:35:44.527 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:35:44.668 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:44.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:44.670 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:44.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:44.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:44.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:44.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:44.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:44.860 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:44.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:44.860 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:44.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:44.864 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:35:44.864 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:35:44.864 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:35:44.864 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:35:44.864 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:35:44.864 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:35:44.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:35:44.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=686 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=686 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=686 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=686 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=686 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=686 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.866 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=686 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.866 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=686 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.866 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=687 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.866 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=687 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.866 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=687 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.866 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=687 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.866 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=687 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.866 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=687 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.866 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=687 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:44.866 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=687 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:35:49.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:35:49.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:35:49.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:35:49.868 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:35:49.868 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:35:49.868 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:35:49.870 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:35:49.870 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:35:49.870 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:35:49.871 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:35:49.871 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:35:49.873 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:35:49.873 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:35:49.873 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:35:49.873 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:35:49.874 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:35:49.874 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:35:49.874 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:35:49.874 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:35:49.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:49.875 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:35:49.876 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:35:49.876 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:35:49.876 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:35:49.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:35:49.876 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:35:49.876 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:35:49.876 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:35:49.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:49.878 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:35:49.878 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:35:49.878 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:35:49.878 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:35:49.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:35:49.878 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:35:49.878 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:35:49.878 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:35:49.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:49.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:35:49.882 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:35:49.882 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:35:49.882 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:49.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:49.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:49.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:49.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:49.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:49.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:35:49.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:35:49.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:35:49.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:49.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:49.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:49.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:49.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:35:49.887 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:35:50.370 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:35:50.404 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:35:50.405 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:35:50.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:50.406 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:35:50.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:50.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:50.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:50.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:50.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:50.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:50.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:50.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:50.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:50.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:50.460 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:35:50.460 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:35:50.508 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:50.508 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:50.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:50.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:50.847 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:35:50.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:50.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:50.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:50.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:51.325 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:35:51.803 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:35:51.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:51.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:51.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:51.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:52.281 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:35:52.758 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:35:52.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:52.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:52.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:52.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:53.236 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:35:53.713 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:35:53.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:53.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:53.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:53.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:53.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:53.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:53.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:53.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:53.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:53.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:53.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:53.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:53.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:53.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:53.768 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:35:53.768 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:35:53.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:53.804 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:53.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:53.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:53.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:53.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:53.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:53.916 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:54.190 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:35:54.668 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:35:54.889 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:35:54.889 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:35:54.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:35:54.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:35:55.146 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:35:55.624 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:35:56.102 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:35:56.580 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:35:57.059 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:35:57.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:57.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:57.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:57.151 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:57.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:57.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:57.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:57.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:35:57.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:35:57.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:35:57.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:35:57.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:57.177 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:57.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:57.178 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:35:57.178 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:35:57.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:35:57.195 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:35:57.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:57.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:35:57.536 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:35:58.014 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:35:58.492 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:35:58.969 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:35:59.447 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:35:59.925 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:36:00.403 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:36:00.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:00.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:00.799 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:00.799 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:00.818 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:00.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:00.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:00.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:00.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:00.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:00.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:00.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:00.826 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:00.826 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:00.826 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:36:00.826 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:36:00.873 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:00.873 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:00.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:00.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:00.881 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:36:01.359 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:36:01.836 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:36:02.314 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:36:02.792 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:36:03.269 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:36:03.747 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:36:04.225 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:36:04.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:04.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:04.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:04.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:04.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:04.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:04.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:04.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:04.562 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:36:04.562 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:36:04.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:36:04.563 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:36:04.563 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:36:04.563 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:36:04.563 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:36:04.563 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3134 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.563 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3134 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.564 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3134 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.564 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3134 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.564 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3134 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.564 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3134 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.564 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3134 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.564 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3135 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.564 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3135 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.564 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3135 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.564 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3135 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.564 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3135 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.564 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3135 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.564 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3135 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:04.565 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3135 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:09.562 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:36:09.562 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:36:09.566 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:36:09.566 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:36:09.566 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:36:09.566 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:36:09.572 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:36:09.573 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:36:09.573 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:36:09.573 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:36:09.573 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:36:09.573 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:36:09.573 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:36:09.573 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:36:09.573 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:36:09.573 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:36:09.573 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:36:09.573 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:36:09.573 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:36:09.574 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:09.576 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:36:09.576 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:36:09.576 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:36:09.576 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:36:09.576 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:36:09.576 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:36:09.576 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:36:09.576 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:36:09.577 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:09.579 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:36:09.579 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:36:09.579 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:36:09.579 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:36:09.579 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:36:09.580 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:36:09.580 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:36:09.580 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:36:09.580 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:09.583 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:36:09.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:36:09.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:36:09.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:36:09.583 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:09.584 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:36:09.584 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:36:09.584 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:36:09.584 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:09.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:09.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:09.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:09.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:09.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:09.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:09.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:09.589 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:36:10.072 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:36:10.114 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:36:10.116 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:36:10.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:10.118 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:36:10.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:10.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:10.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:10.164 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:10.165 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:10.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:10.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:10.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:10.172 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:10.173 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:10.173 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:36:10.173 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:36:10.210 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:10.210 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:10.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:10.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:10.549 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:36:10.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:10.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:10.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:10.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:10.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:10.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:10.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:10.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:10.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:10.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:10.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:10.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:10.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:10.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:10.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:10.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:10.623 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:10.623 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:10.623 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:36:10.623 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:36:10.638 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:10.639 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:10.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:10.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:11.026 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:36:11.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:11.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:11.205 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:11.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:11.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:11.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:11.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:11.231 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:11.231 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:11.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:11.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:11.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:11.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:11.232 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:11.232 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:36:11.232 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:36:11.259 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:11.260 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:11.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:11.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:11.502 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:36:11.588 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:11.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:11.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:11.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:11.980 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:36:12.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:12.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:12.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:12.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:12.387 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:12.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:12.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:12.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:12.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:12.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:12.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:12.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:12.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:12.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:12.395 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:36:12.395 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:36:12.397 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:12.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:12.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:12.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:12.457 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:36:12.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:12.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:12.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:12.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:12.935 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:36:13.413 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:36:13.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:13.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:13.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:13.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:13.511 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:13.511 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:13.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:13.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:13.514 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:36:13.514 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:36:13.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:36:13.514 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:36:13.514 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:36:13.514 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:36:13.514 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:36:13.514 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=839 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:13.515 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=839 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:13.515 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=839 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:13.515 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:13.515 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:13.515 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:13.515 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:13.515 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:18.517 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:36:18.517 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:36:18.517 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:36:18.517 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:36:18.517 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:36:18.517 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:36:18.526 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:36:18.528 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:36:18.528 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:36:18.529 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:36:18.529 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:36:18.533 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:36:18.534 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:36:18.534 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:36:18.535 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:36:18.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:36:18.535 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:36:18.536 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:36:18.536 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:36:18.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:18.537 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:36:18.537 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:36:18.538 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:36:18.538 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:36:18.538 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:36:18.538 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:36:18.538 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:36:18.538 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:36:18.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:18.540 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:36:18.541 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:36:18.541 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:36:18.541 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:36:18.541 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:36:18.541 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:36:18.541 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:36:18.541 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:36:18.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:18.544 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:36:18.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:36:18.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:36:18.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:36:18.544 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:36:18.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:36:18.545 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:36:18.545 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:36:18.545 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:18.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:18.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:18.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:18.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:18.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:18.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:18.550 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:36:19.034 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:36:19.076 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:36:19.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:19.079 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:36:19.083 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:36:19.108 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:19.108 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:19.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:19.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:19.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:19.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:19.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:19.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:19.144 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:19.144 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:19.144 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:36:19.144 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:36:19.172 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:19.173 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:19.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:19.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:19.512 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:36:19.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:19.549 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:19.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:19.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:19.990 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:36:20.468 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:36:20.549 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:20.549 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:20.551 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:20.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:20.946 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:36:21.424 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:36:21.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:21.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:21.551 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:21.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:21.901 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:36:22.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:22.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:22.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:22.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:22.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:22.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:22.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:22.083 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:22.083 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:22.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:22.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:22.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:22.084 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:22.085 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:22.085 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:36:22.085 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:36:22.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:22.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:22.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:22.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:22.377 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:36:22.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:22.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:22.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:22.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:22.855 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:36:23.333 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:36:23.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:23.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:23.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:23.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:23.810 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:36:24.288 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:36:24.766 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:36:25.244 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:36:25.722 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:36:26.200 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:36:26.678 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:36:26.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:26.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:26.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:26.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:26.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:26.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:26.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:26.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:26.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:26.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:26.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:26.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:26.729 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:26.729 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:26.730 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:36:26.730 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:36:26.770 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:26.770 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:26.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:26.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:27.155 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:36:27.634 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:36:28.111 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:36:28.589 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:36:29.067 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:36:29.545 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:36:30.022 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:36:30.500 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:36:30.978 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:36:31.456 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:36:31.934 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:36:32.412 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:36:32.890 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:36:33.368 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:36:33.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:33.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:33.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:33.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:33.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:33.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:33.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:33.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:33.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:33.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:33.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:33.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:33.548 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:33.548 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:33.548 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:36:33.548 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:36:33.599 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:33.599 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:33.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:33.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:33.843 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:36:34.321 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:36:34.798 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:36:35.276 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:36:35.754 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:36:36.232 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:36:36.711 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:36:37.188 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:36:37.666 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:36:38.144 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:36:38.621 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:36:39.100 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:36:39.577 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:36:40.055 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:36:40.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:40.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:40.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:40.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:40.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:40.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:40.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:40.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:40.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:36:40.393 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:36:40.393 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:36:40.393 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:36:40.393 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:36:40.393 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:36:40.393 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:36:40.394 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4665 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:40.394 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4665 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:40.394 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4665 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:40.394 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4665 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:40.394 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4665 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:40.394 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4665 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:45.391 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:36:45.391 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:36:45.392 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:36:45.393 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:36:45.394 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:36:45.394 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:36:45.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:36:45.402 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:36:45.402 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:36:45.402 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:36:45.402 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:36:45.404 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:36:45.404 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:36:45.405 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:36:45.405 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:36:45.405 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:36:45.405 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:36:45.406 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:36:45.406 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:36:45.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:45.406 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:36:45.407 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:36:45.407 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:36:45.407 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:36:45.407 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:36:45.407 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:36:45.407 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:36:45.407 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:36:45.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:45.409 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:36:45.409 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:36:45.409 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:36:45.409 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:36:45.409 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:36:45.409 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:36:45.409 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:36:45.409 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:36:45.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:45.411 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:36:45.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:36:45.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:36:45.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:36:45.412 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:36:45.412 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:36:45.412 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:45.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:45.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:36:45.417 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:36:45.900 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:36:45.943 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:36:45.946 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:36:45.947 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:36:45.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:45.974 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:45.974 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:45.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:45.989 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:45.989 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:45.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:45.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:45.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:45.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:45.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:45.993 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:36:45.993 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:36:46.038 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:46.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:46.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:46.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:46.377 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:36:46.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:46.415 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:46.416 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:46.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:46.855 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:36:47.333 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:36:47.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:47.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:47.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:47.420 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:47.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:47.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:47.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:47.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:47.811 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:36:47.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:47.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:47.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:47.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:47.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:47.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:47.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:47.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:47.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:47.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:47.835 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:36:47.835 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:36:47.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:47.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:47.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:47.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:48.288 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:36:48.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:48.418 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:48.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:48.421 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:48.766 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:36:49.244 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:36:49.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:49.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:49.419 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:49.422 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:49.722 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:36:50.200 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:36:50.419 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:50.419 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:50.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:50.423 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:50.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:50.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:50.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:50.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:50.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:50.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:50.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:50.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:50.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:50.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:50.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:50.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:50.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:50.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:50.670 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:36:50.670 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:36:50.678 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:36:50.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:50.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:50.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:50.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:51.155 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:36:51.632 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:36:52.110 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:36:52.588 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:36:53.066 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:36:53.543 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:36:54.020 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:36:54.498 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:36:54.976 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:36:55.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:55.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:55.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:55.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:55.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:55.156 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:55.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:55.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:55.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:55.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:36:55.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:55.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:55.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:55.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:55.164 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:36:55.164 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:36:55.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:36:55.211 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:36:55.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:55.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:55.453 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:36:55.930 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:36:56.408 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:36:56.886 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:36:57.364 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:36:57.842 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:36:58.320 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:36:58.798 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:36:59.276 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:36:59.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:36:59.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:36:59.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:36:59.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:36:59.611 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:36:59.612 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:36:59.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:36:59.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:36:59.614 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:36:59.614 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:36:59.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:36:59.615 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:36:59.615 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:36:59.615 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:36:59.615 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3032 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3032 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3032 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3032 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3032 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3032 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3033 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3033 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3033 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3033 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3033 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3033 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3033 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:36:59.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3033 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:04.615 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:04.615 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:04.616 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:04.618 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:04.619 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:04.619 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:04.623 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:04.624 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:04.624 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:04.625 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:04.625 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:37:04.627 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:37:04.627 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:37:04.628 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:04.628 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:04.628 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:04.628 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:37:04.629 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:04.629 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:37:04.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:04.630 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:37:04.630 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:37:04.630 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:04.630 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:04.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:04.630 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:37:04.631 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:04.631 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:37:04.631 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:04.632 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:37:04.632 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:37:04.632 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:04.632 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:04.632 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:04.632 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:37:04.632 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:04.632 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:37:04.633 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:04.635 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:37:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:37:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:37:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:37:04.635 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:37:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:37:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:37:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:37:04.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:37:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:04.635 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:37:04.636 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:37:04.636 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:37:04.636 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:04.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:04.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:04.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:04.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:04.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:04.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:04.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:04.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:04.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:04.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:04.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:04.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:04.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:04.641 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:37:05.124 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:37:05.164 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:37:05.166 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:37:05.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:05.168 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:37:05.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:05.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:05.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:05.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:05.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:05.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:05.594 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:37:05.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:05.639 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:05.641 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:05.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:05.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:05.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:05.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:05.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:06.068 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:37:06.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:06.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:06.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:06.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:06.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:06.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:06.487 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:06.487 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:06.487 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:06.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:06.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:06.490 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:06.490 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:06.490 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:06.490 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:06.490 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:06.490 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:37:06.490 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.490 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.490 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.490 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.490 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.490 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.490 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.490 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=399 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.491 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=399 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.491 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=399 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.491 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=399 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.491 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=399 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.491 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=399 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.491 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=399 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:06.491 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=399 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:11.491 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:11.491 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:11.492 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:11.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:11.495 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:11.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:11.510 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:11.510 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:11.510 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:11.511 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:11.511 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:37:11.512 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:37:11.512 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:37:11.513 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:11.513 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:11.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:11.513 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:37:11.513 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:11.513 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:37:11.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:11.514 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:37:11.514 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:37:11.514 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:11.514 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:11.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:11.514 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:37:11.514 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:11.514 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:37:11.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:11.515 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:37:11.515 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:37:11.516 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:11.516 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:11.516 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:37:11.516 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:11.516 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:11.516 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:37:11.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:11.517 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:37:11.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:37:11.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:37:11.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:37:11.517 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:37:11.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:37:11.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:37:11.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:37:11.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:37:11.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:11.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:37:11.518 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:37:11.518 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:37:11.518 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:11.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:11.522 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:37:12.006 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:37:12.038 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:37:12.039 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:37:12.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.041 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:37:12.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.483 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:37:12.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:12.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:12.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:12.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:12.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:12.957 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:37:13.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:13.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:13.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:13.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:13.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:13.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:13.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:13.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:13.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:13.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:13.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:13.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:13.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:13.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:13.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:13.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:13.399 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:13.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:13.399 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:13.399 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:13.399 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:13.399 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:13.399 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:37:13.400 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:13.400 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:13.400 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:13.400 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:13.400 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:13.400 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:13.400 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:13.400 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:13.401 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:13.401 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:13.401 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:13.401 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:13.401 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:13.401 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:18.398 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:18.399 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:18.400 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:18.400 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:18.401 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:18.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:18.410 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:18.411 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:18.411 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:18.412 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:18.412 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:37:18.415 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:37:18.415 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:37:18.416 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:18.416 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:18.416 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:18.417 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:37:18.417 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:18.417 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:37:18.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:18.418 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:37:18.418 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:37:18.418 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:18.418 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:18.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:18.419 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:37:18.419 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:18.419 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:37:18.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:18.420 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:37:18.420 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:37:18.420 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:18.420 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:18.421 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:18.421 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:37:18.421 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:18.421 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:37:18.421 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:18.423 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:37:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:37:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:37:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:37:18.423 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:37:18.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:37:18.424 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:37:18.424 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:37:18.424 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:18.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:18.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:18.429 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:37:18.914 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:37:18.951 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:37:18.953 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:37:18.954 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:37:18.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:18.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:18.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.390 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:37:19.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:19.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:19.429 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:19.432 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:19.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.864 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:37:19.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:19.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:20.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:20.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:20.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:20.276 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:20.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:20.276 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:20.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:20.277 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:20.277 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:20.277 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:20.277 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:20.277 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:20.277 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:37:20.277 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:20.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:20.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:20.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:20.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:20.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:20.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:20.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:20.277 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:25.279 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:25.279 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:25.281 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:25.283 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:25.284 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:25.284 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:25.296 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:25.297 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:25.297 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:25.297 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:25.298 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:37:25.299 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:37:25.300 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:37:25.300 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:25.300 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:25.300 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:25.301 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:37:25.301 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:25.301 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:37:25.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:25.302 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:37:25.302 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:37:25.302 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:25.302 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:25.302 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:25.302 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:37:25.302 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:25.302 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:37:25.302 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:25.304 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:37:25.304 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:37:25.304 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:25.304 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:25.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:25.304 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:37:25.304 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:25.304 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:37:25.304 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:37:25.307 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:37:25.307 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:37:25.307 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:37:25.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:25.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:25.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:25.312 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:37:25.794 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:37:25.840 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:37:25.842 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:37:25.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:25.845 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:37:25.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:25.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:26.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:26.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:26.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:26.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:26.272 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:37:26.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:26.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:26.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:26.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:26.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:26.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:26.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:26.741 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:37:26.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:26.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:26.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:26.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:27.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:27.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:27.172 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:27.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:27.172 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:27.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:27.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:27.173 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:27.173 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:27.173 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:27.173 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:27.173 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:37:27.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:27.173 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=402 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:27.173 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=402 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:27.173 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=402 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:27.173 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=402 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:27.173 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=402 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:27.173 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=402 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:27.173 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=402 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:27.173 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=402 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:32.175 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:32.176 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:32.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:32.178 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:32.178 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:32.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:32.184 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:32.186 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:32.186 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:32.186 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:32.186 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:37:32.190 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:37:32.190 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:37:32.191 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:32.191 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:32.191 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:32.191 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:37:32.192 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:32.192 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:37:32.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:32.193 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:37:32.194 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:37:32.194 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:32.194 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:32.194 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:32.194 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:37:32.194 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:32.194 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:37:32.194 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:32.196 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:37:32.197 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:37:32.197 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:32.197 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:32.197 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:32.197 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:37:32.197 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:32.197 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:37:32.197 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:32.200 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:37:32.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:37:32.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:37:32.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:37:32.200 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:37:32.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:32.201 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:37:32.201 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:37:32.201 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:37:32.201 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:32.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:32.206 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:37:32.690 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:37:32.730 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:37:32.731 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:37:32.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:32.732 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:37:32.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:32.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:32.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:33.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:33.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:33.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:33.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:33.159 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:37:33.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:33.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:33.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:33.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:33.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:33.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:33.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:33.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:33.634 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:37:33.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:33.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:33.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:33.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:34.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:34.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:34.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:34.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:34.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:34.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:34.061 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:34.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:34.061 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:34.061 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:34.061 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:34.061 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:37:34.062 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:34.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=400 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:34.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=400 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:34.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=400 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:34.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=400 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:34.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=400 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:34.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=400 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:34.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=400 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:39.062 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:39.062 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:39.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:39.062 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:39.062 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:39.062 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:39.071 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:39.073 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:39.073 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:39.073 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:39.074 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:37:39.077 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:37:39.077 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:37:39.078 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:39.078 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:39.078 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:39.079 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:37:39.079 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:39.079 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:37:39.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:39.080 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:37:39.080 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:37:39.080 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:39.080 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:39.081 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:39.081 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:37:39.081 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:39.081 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:37:39.081 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:39.083 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:37:39.083 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:37:39.083 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:39.083 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:39.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:39.084 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:37:39.084 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:39.084 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:37:39.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:39.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:37:39.088 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:37:39.088 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:37:39.088 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:39.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:39.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:39.093 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:37:39.577 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:37:39.626 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:37:39.628 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:37:39.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:39.630 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:37:39.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:39.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:39.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:39.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:39.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:39.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:39.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:39.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:39.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:39.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:39.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.054 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:37:40.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:40.093 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:40.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:40.098 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:40.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.522 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:37:40.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:40.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:40.959 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:40.959 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:40.959 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:40.960 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:40.960 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:40.960 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:40.960 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:40.960 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:40.960 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:40.960 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:37:40.960 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:40.960 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:40.960 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:40.960 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:45.963 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:45.963 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:45.965 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:45.966 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:45.967 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:45.967 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:45.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:45.972 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:45.972 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:45.972 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:45.972 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:37:45.975 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:37:45.975 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:37:45.975 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:45.976 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:45.976 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:45.976 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:37:45.976 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:45.977 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:37:45.977 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:45.977 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:37:45.977 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:37:45.977 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:45.977 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:45.978 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:45.978 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:37:45.978 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:45.978 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:37:45.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:45.979 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:37:45.979 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:37:45.979 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:45.980 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:45.980 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:45.980 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:37:45.980 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:45.980 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:37:45.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:45.982 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:37:45.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:37:45.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:37:45.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:37:45.982 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:37:45.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:37:45.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:37:45.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:37:45.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:37:45.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:45.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:37:45.983 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:37:45.983 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:37:45.983 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:45.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:45.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:45.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:45.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:45.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:45.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:45.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:45.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:45.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:45.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:45.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:45.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:45.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:45.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:45.988 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:37:46.472 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:37:46.503 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:37:46.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:46.505 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:37:46.505 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:37:46.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:46.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:46.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:46.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:46.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:46.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:46.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:46.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:46.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:46.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:46.943 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:37:46.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:46.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:46.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:46.989 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:47.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.417 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:37:47.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:47.835 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:47.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:47.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:47.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:47.836 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:47.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:47.836 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:47.836 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:47.836 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:47.836 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:47.836 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:37:52.838 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:52.839 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:52.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:52.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:52.842 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:52.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:52.863 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:52.864 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:52.865 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:52.865 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:52.865 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:37:52.866 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:37:52.866 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:37:52.866 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:52.866 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:52.866 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:52.866 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:37:52.867 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:52.867 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:37:52.867 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:52.867 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:37:52.868 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:37:52.868 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:52.868 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:52.868 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:52.868 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:37:52.869 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:52.869 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:37:52.869 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:52.871 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:37:52.871 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:37:52.871 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:52.871 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:52.871 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:52.871 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:37:52.871 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:52.871 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:37:52.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:52.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:52.876 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:37:52.876 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:37:52.876 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:37:52.876 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:37:52.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:52.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:52.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:52.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:37:52.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:52.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:52.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:52.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:52.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:52.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:52.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:52.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:52.877 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:52.877 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:52.877 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:52.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:52.877 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:52.877 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:52.877 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:52.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:52.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:52.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:52.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:52.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:52.881 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:37:53.363 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:37:53.397 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:37:53.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.398 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:37:53.399 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:37:53.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:53.483 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:53.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:53.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:53.483 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:53.483 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:53.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:53.483 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:53.483 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:53.483 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:53.483 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:53.483 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:37:53.483 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=130 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:53.484 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=130 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:37:58.486 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:58.487 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:58.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:58.490 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:58.491 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:58.491 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:58.502 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:58.502 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:58.502 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:58.502 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:37:58.502 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:37:58.504 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:37:58.505 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:37:58.505 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:58.505 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:58.506 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:58.506 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:37:58.506 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:37:58.506 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:37:58.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:58.508 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:37:58.509 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:37:58.509 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:58.509 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:58.510 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:58.510 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:37:58.510 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:37:58.510 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:37:58.510 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:58.512 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:37:58.512 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:37:58.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:58.512 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:37:58.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:58.512 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:37:58.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:37:58.512 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:37:58.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:58.515 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:58.516 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:37:58.516 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:37:58.516 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:37:58.517 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:58.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:58.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:37:58.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:37:58.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:58.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:37:58.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:58.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:58.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:58.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:37:58.521 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:37:59.006 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:37:59.048 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:37:59.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.051 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:37:59.052 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:37:59.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:37:59.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:37:59.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:37:59.165 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:37:59.165 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:37:59.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:37:59.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:37:59.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:37:59.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:37:59.166 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:37:59.166 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:37:59.166 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:38:04.169 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:04.169 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:04.171 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:04.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:04.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:04.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:04.182 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:04.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:04.184 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:04.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:04.184 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:38:04.189 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:38:04.190 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:38:04.190 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:04.190 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:04.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:04.190 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:38:04.190 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:04.190 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:38:04.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:04.194 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:38:04.194 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:38:04.194 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:04.194 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:04.195 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:04.195 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:38:04.195 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:04.195 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:38:04.195 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:04.198 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:38:04.198 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:38:04.198 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:04.198 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:04.198 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:04.198 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:38:04.198 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:04.198 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:38:04.199 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:04.202 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:38:04.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:38:04.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:38:04.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:38:04.202 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:38:04.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:38:04.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:38:04.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:38:04.203 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:38:04.203 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:38:04.203 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:04.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:04.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:04.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:04.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:04.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:04.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:04.208 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:38:04.691 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:38:04.725 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:38:04.726 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:38:04.726 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:38:04.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:04.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:04.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:04.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:04.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:04.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:04.815 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:04.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:04.815 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:04.815 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:04.815 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:38:04.816 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:09.819 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:09.819 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:09.820 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:09.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:09.825 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:09.826 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:09.840 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:09.842 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:09.842 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:09.842 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:09.843 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:38:09.847 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:38:09.847 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:38:09.847 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:09.848 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:09.848 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:09.848 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:38:09.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:09.848 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:38:09.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:09.849 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:38:09.849 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:38:09.849 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:09.849 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:09.849 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:09.849 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:38:09.849 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:09.849 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:38:09.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:09.850 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:38:09.850 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:38:09.850 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:09.850 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:09.850 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:38:09.850 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:09.851 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:09.851 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:38:09.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:38:09.854 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:38:09.854 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:38:09.854 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:38:09.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:09.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:09.859 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:38:10.343 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:38:10.380 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:38:10.381 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:38:10.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.382 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:38:10.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:10.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:10.451 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:10.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:10.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:10.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:10.452 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:10.452 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:10.452 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:10.452 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:10.452 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:38:10.452 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:15.455 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:15.455 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:15.456 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:15.458 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:15.459 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:15.459 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:15.469 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:15.471 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:15.471 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:15.471 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:15.471 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:38:15.474 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:38:15.475 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:38:15.475 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:15.475 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:15.475 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:15.475 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:38:15.476 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:15.476 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:38:15.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:15.478 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:38:15.478 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:38:15.478 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:15.478 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:15.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:15.479 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:38:15.479 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:15.479 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:38:15.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:15.481 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:38:15.481 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:38:15.481 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:15.481 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:15.481 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:15.481 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:38:15.482 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:15.482 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:38:15.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:15.484 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:15.485 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:38:15.485 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:38:15.485 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:38:15.486 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:38:15.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:15.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:15.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:15.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:38:15.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:15.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:15.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:15.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:15.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:15.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:15.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:15.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:15.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:15.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:15.490 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:38:15.973 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:38:16.010 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:38:16.011 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:38:16.012 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:38:16.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:16.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:16.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:16.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:16.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:16.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:16.077 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:16.077 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:16.077 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:16.077 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:16.077 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:16.077 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:38:16.077 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:16.077 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:38:16.077 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:38:16.077 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:38:16.077 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:38:16.077 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:38:21.079 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:21.080 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:21.081 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:21.083 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:21.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:21.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:21.090 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:21.091 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:21.091 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:21.091 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:21.092 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:38:21.094 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:38:21.094 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:38:21.095 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:21.095 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:21.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:21.095 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:38:21.096 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:21.096 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:38:21.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:21.097 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:38:21.097 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:38:21.097 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:21.097 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:21.097 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:21.097 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:38:21.097 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:21.097 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:38:21.098 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:21.099 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:38:21.099 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:38:21.099 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:21.099 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:21.099 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:21.099 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:38:21.099 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:21.099 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:38:21.100 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:21.102 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:38:21.103 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:38:21.103 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:38:21.103 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:21.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:21.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:21.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:21.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:21.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:21.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:21.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:21.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:21.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:21.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:21.108 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:38:21.590 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:38:21.633 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:38:21.635 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:38:21.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.637 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:38:21.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:21.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:21.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:21.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:21.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:21.746 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:21.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:21.746 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:21.746 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:21.747 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:21.747 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:38:21.747 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:21.747 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:26.750 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:26.750 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:26.751 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:26.753 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:26.754 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:26.754 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:26.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:26.767 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:26.767 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:26.768 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:26.768 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:38:26.771 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:38:26.771 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:38:26.772 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:26.772 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:26.772 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:26.773 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:38:26.773 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:26.774 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:38:26.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:26.775 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:38:26.775 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:38:26.775 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:26.776 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:26.776 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:26.776 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:38:26.776 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:26.776 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:38:26.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:26.779 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:38:26.779 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:38:26.779 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:26.779 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:26.779 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:26.779 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:38:26.779 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:26.779 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:38:26.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:26.783 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:38:26.783 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:38:26.784 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:38:26.784 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:38:26.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:26.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:26.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:26.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:38:26.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:26.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:26.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:26.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:26.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:26.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:26.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:26.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:26.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:26.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:26.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:26.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:26.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:26.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:26.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:26.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:26.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:26.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:26.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:26.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:26.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:26.789 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:38:27.272 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:38:27.315 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:38:27.317 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:38:27.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.318 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:38:27.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:27.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:27.407 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:27.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:27.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:27.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:27.408 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:27.408 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:27.408 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:27.408 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:27.408 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:27.408 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:27.408 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:38:32.411 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:32.411 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:32.412 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:32.414 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:32.415 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:32.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:32.422 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:32.422 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:32.422 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:32.423 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:32.423 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:38:32.424 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:38:32.425 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:38:32.425 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:32.425 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:32.425 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:32.426 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:38:32.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:32.426 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:38:32.426 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:32.427 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:38:32.427 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:38:32.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:32.427 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:32.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:32.427 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:38:32.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:32.427 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:38:32.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:32.430 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:38:32.430 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:38:32.430 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:32.430 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:32.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:32.430 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:38:32.430 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:32.430 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:38:32.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:32.433 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:38:32.433 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:38:32.434 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:38:32.434 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:32.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:32.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:32.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:32.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:32.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:32.438 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:38:32.922 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:38:32.965 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:38:32.968 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:38:32.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:32.970 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:38:32.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:38:32.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:38:32.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:38:32.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:38:32.973 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:38:32.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:38:32.973 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:38:32.973 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:38:33.400 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:38:33.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:33.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:33.438 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:33.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:33.878 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:38:34.355 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:38:34.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:34.437 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:34.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:34.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:34.833 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:38:35.311 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:38:35.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:35.438 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:35.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:35.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:35.789 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:38:36.267 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:38:36.438 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:38:36.438 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:38:36.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:36.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:36.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:36.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:36.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:36.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:36.441 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:36.441 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:36.441 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:36.441 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:36.441 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:36.441 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:36.441 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:38:41.443 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:41.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:41.445 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:41.446 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:41.447 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:41.448 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:41.455 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:41.456 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:41.456 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:41.457 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:41.457 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:38:41.459 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:38:41.459 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:38:41.460 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:41.460 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:41.460 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:41.460 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:38:41.460 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:41.460 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:38:41.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:41.462 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:38:41.463 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:38:41.463 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:41.463 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:41.463 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:41.463 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:38:41.463 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:41.463 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:38:41.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:41.466 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:38:41.466 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:38:41.466 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:41.466 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:41.466 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:41.466 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:38:41.466 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:41.466 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:38:41.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:41.469 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:41.470 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:38:41.470 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:38:41.471 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:38:41.471 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:38:41.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:41.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:41.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:41.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:38:41.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:41.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:41.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:41.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:41.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:41.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:41.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:41.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:41.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:41.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:41.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:41.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:41.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:41.472 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:41.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:41.472 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:41.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:41.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:41.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:41.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:41.475 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:38:41.958 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:38:42.004 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:38:42.006 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:38:42.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:42.009 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:38:42.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:38:42.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:38:42.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:38:42.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:38:42.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:38:42.037 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:38:42.037 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:38:42.037 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:38:42.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:38:42.057 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:38:42.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:38:42.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:38:42.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:38:42.436 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:38:42.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:42.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:42.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:42.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:42.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:38:42.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:38:42.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:38:42.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:38:42.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:38:42.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:38:42.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:38:42.560 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:38:42.560 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:38:42.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:42.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:38:42.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:38:42.581 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:42.581 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:42.581 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:42.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:42.582 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:42.582 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:42.582 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:42.582 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:42.582 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:42.582 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:42.582 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:38:47.585 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:38:47.585 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:38:47.586 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:47.587 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:47.588 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:47.588 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:47.595 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:38:47.596 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:47.596 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:47.596 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:38:47.596 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:38:47.598 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:38:47.599 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:38:47.599 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:47.599 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:47.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:38:47.600 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:38:47.600 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:38:47.600 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:38:47.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:47.601 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:38:47.601 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:38:47.601 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:47.601 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:47.601 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:38:47.601 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:38:47.601 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:38:47.601 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:38:47.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:47.603 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:38:47.603 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:38:47.603 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:47.603 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:38:47.603 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:38:47.603 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:38:47.603 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:38:47.603 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:38:47.603 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:47.605 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:38:47.605 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:38:47.605 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:38:47.606 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:38:47.606 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:38:47.606 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:47.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:47.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:38:47.611 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:38:48.094 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:38:48.136 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:38:48.138 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:38:48.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:48.139 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:38:48.158 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:38:48.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:38:48.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:38:48.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:38:48.161 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:38:48.162 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:38:48.162 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:38:48.162 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:38:48.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:38:48.193 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:38:48.194 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:38:48.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:38:48.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:38:48.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:38:48.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:38:48.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:38:48.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:38:48.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:38:48.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:38:48.310 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:38:48.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:38:48.311 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:38:48.311 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:38:48.571 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:38:48.608 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:48.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:48.610 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:48.613 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:49.049 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:38:49.526 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:38:49.609 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:49.610 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:49.610 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:49.613 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:50.004 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:38:50.482 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:38:50.610 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:50.611 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:50.611 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:50.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:50.960 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:38:51.438 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:38:51.611 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:51.611 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:51.611 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:51.616 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:51.915 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:38:52.392 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:38:52.612 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:38:52.612 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:38:52.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:38:52.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:38:52.870 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:38:53.348 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:38:53.825 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:38:54.303 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:38:54.781 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:38:55.259 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:38:55.737 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:38:56.215 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:38:56.690 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:38:57.159 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:38:57.636 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:38:58.114 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:38:58.592 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:38:59.070 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:38:59.548 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:39:00.026 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:39:00.504 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:39:00.982 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:39:01.460 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:39:01.938 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:39:02.416 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:39:02.894 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:39:03.372 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:39:03.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:39:03.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:39:03.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:39:03.669 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=3432 tn=2 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:03.670 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=3432 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:03.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:39:03.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:39:03.689 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:39:03.689 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:39:03.689 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:39:03.690 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:39:03.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:39:03.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:39:03.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:39:03.703 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:39:03.703 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:39:03.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:39:03.703 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:39:03.707 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:03.707 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:03.707 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:03.707 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:03.707 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:39:03.707 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:39:03.708 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:39:03.708 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3440 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:03.708 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3440 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:03.708 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3440 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:03.708 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3440 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:03.708 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3440 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:03.708 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3440 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:03.708 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3440 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:08.706 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:39:08.707 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:39:08.708 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:08.709 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:08.711 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:08.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:08.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:08.719 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:39:08.719 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:08.719 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:39:08.720 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:39:08.723 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:39:08.724 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:39:08.724 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:39:08.725 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:08.725 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:08.726 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:39:08.726 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:39:08.726 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:39:08.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:39:08.727 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:39:08.728 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:39:08.728 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:39:08.728 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:08.728 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:08.729 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:39:08.729 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:39:08.729 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:39:08.730 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:39:08.732 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:39:08.732 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:39:08.732 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:39:08.732 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:08.732 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:08.733 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:39:08.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:39:08.733 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:39:08.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:39:08.737 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:39:08.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:39:08.737 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:39:08.737 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:39:08.737 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:39:08.737 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:39:08.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:39:08.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:39:08.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:39:08.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:08.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:08.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:08.738 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:39:08.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:08.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:08.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:08.738 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:39:08.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:08.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:08.739 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:39:08.739 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:39:08.739 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:39:08.739 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:39:08.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:08.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:08.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:08.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:39:08.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:08.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:08.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:08.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:08.744 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:39:09.227 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:39:09.270 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:39:09.270 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:39:09.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:39:09.271 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:39:09.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:39:09.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:39:09.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:39:09.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:39:09.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:39:09.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:39:09.295 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:39:09.295 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:39:09.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:39:09.329 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:39:09.329 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:39:09.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:39:09.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:39:09.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:39:09.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:39:09.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:39:09.622 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:39:09.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:39:09.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:39:09.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:39:09.623 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:39:09.623 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:39:09.623 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:39:09.623 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:39:09.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:39:09.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:39:09.650 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:39:09.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:39:09.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:39:09.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:39:09.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:39:09.661 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:09.661 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:09.661 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:09.661 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:39:09.661 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:39:09.661 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:39:09.661 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:09.661 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=197 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:09.661 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=197 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:09.661 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=197 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:09.661 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=197 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:09.661 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=197 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:09.661 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=197 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:09.661 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=197 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:14.662 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:39:14.662 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:39:14.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:14.664 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:14.665 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:14.665 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:14.672 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:14.673 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:39:14.673 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:14.673 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:39:14.673 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:39:14.675 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:39:14.676 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:39:14.676 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:39:14.676 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:14.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:14.677 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:39:14.677 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:39:14.677 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:39:14.677 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:39:14.678 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:39:14.678 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:39:14.678 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:39:14.678 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:14.678 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:14.678 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:39:14.678 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:39:14.678 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:39:14.678 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:39:14.680 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:39:14.680 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:39:14.680 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:39:14.680 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:14.680 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:14.680 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:39:14.680 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:39:14.680 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:39:14.680 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:39:14.683 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:39:14.683 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:39:14.683 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:39:14.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:14.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:14.688 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:39:15.172 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:39:15.214 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:39:15.216 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:39:15.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:39:15.219 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:39:15.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:39:15.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:39:15.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:39:15.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:39:15.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:39:15.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:39:15.250 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:39:15.250 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:39:15.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:39:15.273 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:39:15.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:39:15.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:39:15.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:39:15.650 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:39:15.686 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:39:15.686 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:39:15.686 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:39:15.690 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:39:16.128 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:39:16.606 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:39:16.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:39:16.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:39:16.687 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:39:16.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:39:17.084 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:39:17.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:39:17.281 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:39:17.281 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:39:17.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:39:17.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:39:17.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:39:17.300 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:39:17.300 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:39:17.301 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:39:17.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:39:17.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:39:17.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:39:17.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:39:17.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:39:17.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:39:17.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:39:17.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:17.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:17.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:17.330 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:39:17.330 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:39:17.330 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:39:17.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:17.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:17.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:17.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:17.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:17.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:17.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:17.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:17.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:17.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:17.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:17.331 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:39:22.328 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:39:22.328 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:39:22.329 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:22.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:22.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:22.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:22.333 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:22.334 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:39:22.334 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:22.334 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:39:22.334 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:39:22.335 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:39:22.335 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:39:22.335 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:39:22.335 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:22.335 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:22.335 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:39:22.335 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:39:22.335 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:39:22.336 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:39:22.336 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:39:22.336 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:39:22.336 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:39:22.336 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:22.336 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:22.337 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:39:22.337 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:39:22.337 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:39:22.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:39:22.337 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:39:22.337 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:39:22.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:39:22.337 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:22.338 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:22.338 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:39:22.338 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:39:22.338 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:39:22.338 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:22.339 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:39:22.339 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:39:22.339 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:39:22.340 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:22.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:22.341 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:22.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:22.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:39:22.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:22.341 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:22.341 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:22.341 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:39:22.341 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:39:22.341 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:39:22.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:27.342 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:39:27.342 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:39:27.342 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:27.342 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:27.343 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:27.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:27.345 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:27.345 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:39:27.345 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:27.345 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:39:27.345 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:39:27.346 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:39:27.346 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:39:27.346 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:39:27.346 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:27.346 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:27.346 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:39:27.346 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:39:27.346 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:39:27.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:39:27.347 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:39:27.347 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:39:27.347 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:39:27.347 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:39:27.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:27.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:39:27.349 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:39:27.349 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:39:27.349 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:39:27.349 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:39:27.349 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:39:27.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:39:31.696 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.201.20:5700'
2026-03-05 02:39:31.696 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.201.20:5802)
2026-03-05 02:39:31.696 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.201.20:5801)
2026-03-05 02:39:31.697 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.201.22:6700'
2026-03-05 02:39:31.697 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.201.22:6802)
2026-03-05 02:39:31.697 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.201.22:6801)
2026-03-05 02:39:31.697 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.201.20:5700/1'
2026-03-05 02:39:31.697 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.201.20:5804)
2026-03-05 02:39:31.697 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.201.20:5803)
2026-03-05 02:39:31.697 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.201.20:5700/2'
2026-03-05 02:39:31.697 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.201.20:5806)
2026-03-05 02:39:31.697 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.201.20:5805)
2026-03-05 02:39:31.697 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.201.20:5700/3'
2026-03-05 02:39:31.697 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.201.20:5808)
2026-03-05 02:39:31.697 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.201.20:5807)
2026-03-05 02:39:31.697 [INFO] fake_trx.py:429 Init complete
2026-03-05 02:39:31.697 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-03-05 02:39:33.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:39:33.288 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:39:33.289 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:33.289 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:33.289 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:33.289 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:44.373 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:44.373 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:44.373 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:44.373 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:49.382 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:39:49.382 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:39:49.383 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:49.383 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:49.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:49.386 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:49.408 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:49.408 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:49.408 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:49.408 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:54.416 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:39:54.416 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:39:54.416 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:54.416 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:54.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:54.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:54.446 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:54.446 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:54.446 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:54.446 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:59.455 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:39:59.455 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:39:59.456 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:59.458 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:59.459 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:39:59.462 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:59.484 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:39:59.484 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:39:59.484 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:39:59.484 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:04.492 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:40:04.492 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:40:04.493 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:04.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:04.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:04.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:04.518 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:04.518 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:04.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:04.518 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:09.526 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:40:09.526 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:40:09.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:09.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:09.527 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:09.530 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:09.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:09.547 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:09.547 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:09.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:14.556 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:40:14.556 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:40:14.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:14.557 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:14.557 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:14.560 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:14.579 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:14.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:14.579 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:14.579 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:19.587 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:40:19.587 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:40:19.587 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:19.587 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:19.588 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:19.589 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:19.611 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:19.611 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:19.611 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:19.611 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:24.620 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:40:24.620 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:40:24.620 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:24.621 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:24.623 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:24.624 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:24.645 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:24.645 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:24.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:24.645 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:29.653 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:40:29.653 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:40:29.653 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:29.654 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:29.654 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:29.657 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:29.675 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:29.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:29.675 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:29.675 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:34.684 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:40:34.684 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:40:34.684 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:34.685 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:34.685 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:34.688 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:34.710 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:40:34.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:40:34.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:40:34.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:40:34.710 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:40:34.710 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:40:34.710 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:40:34.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:40:34.710 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:40:34.710 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:40:34.710 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:40:34.710 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:40:34.710 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:40:34.710 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:40:34.710 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 0 -> 1
2026-03-05 02:40:34.710 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:40:34.710 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 0 -> 1
2026-03-05 02:40:34.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:40:34.711 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:40:34.711 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 0 -> 1
2026-03-05 02:40:34.711 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:40:34.711 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:40:34.711 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 0 -> 1
2026-03-05 02:40:34.711 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:40:34.713 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:34.713 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:34.713 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:34.713 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:39.722 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:40:39.722 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:40:39.723 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:39.723 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:39.723 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:39.726 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:39.744 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:39.744 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:39.744 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:39.744 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:44.753 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:40:44.753 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:40:44.753 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:44.753 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:44.753 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:44.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:44.756 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:40:44.757 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:40:44.757 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:40:44.757 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:40:44.770 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:44.770 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:44.770 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:44.770 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:49.778 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:40:49.779 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:40:49.779 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:49.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:49.779 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:49.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:49.802 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:49.802 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:49.802 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:49.802 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:54.809 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:40:54.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:40:54.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:54.813 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:54.813 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:54.814 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:54.827 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:54.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:54.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:54.827 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:59.836 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:40:59.836 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:40:59.838 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:59.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:40:59.843 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:59.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:59.871 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:40:59.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:40:59.871 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:40:59.871 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:04.880 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:41:04.880 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:41:04.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:04.880 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:04.880 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:04.880 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:04.901 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:04.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:04.901 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:04.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:10.990 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.201.20:5700'
2026-03-05 02:41:10.990 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.201.20:5802)
2026-03-05 02:41:10.990 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.201.20:5801)
2026-03-05 02:41:10.990 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.201.22:6700'
2026-03-05 02:41:10.990 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.201.22:6802)
2026-03-05 02:41:10.990 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.201.22:6801)
2026-03-05 02:41:10.990 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.201.20:5700/1'
2026-03-05 02:41:10.990 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.201.20:5804)
2026-03-05 02:41:10.990 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.201.20:5803)
2026-03-05 02:41:10.991 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.201.20:5700/2'
2026-03-05 02:41:10.991 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.201.20:5806)
2026-03-05 02:41:10.991 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.201.20:5805)
2026-03-05 02:41:10.991 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.201.20:5700/3'
2026-03-05 02:41:10.991 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.201.20:5808)
2026-03-05 02:41:10.991 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.201.20:5807)
2026-03-05 02:41:10.991 [INFO] fake_trx.py:429 Init complete
2026-03-05 02:41:10.991 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-03-05 02:41:12.598 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:41:12.598 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:41:12.599 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:12.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:12.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:12.600 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:15.613 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:15.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:41:15.614 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:15.615 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:41:15.615 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 0 -> 1
2026-03-05 02:41:15.618 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:41:15.619 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:41:15.619 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:41:15.619 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:15.620 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:15.620 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:41:15.621 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:41:15.621 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 0 -> 1
2026-03-05 02:41:15.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:15.623 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:41:15.624 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:41:15.624 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:41:15.624 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:15.625 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:15.625 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:41:15.626 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:41:15.626 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 0 -> 1
2026-03-05 02:41:15.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:15.627 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:41:15.627 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:41:15.627 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:41:15.627 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:15.627 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:15.627 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:41:15.627 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:41:15.627 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 0 -> 1
2026-03-05 02:41:15.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:15.629 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:41:15.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:41:15.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:41:15.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:41:15.629 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:41:15.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:41:15.629 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:41:15.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:41:15.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:15.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:15.630 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:41:15.630 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:41:15.630 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:41:15.630 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:41:15.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:15.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:41:15.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:41:15.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:41:15.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:15.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:15.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:15.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:15.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:15.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:15.635 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:41:16.117 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:41:16.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:16.168 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:41:16.171 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:41:16.172 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:41:16.193 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:16.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:16.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:16.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:16.199 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:16.199 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:16.199 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:16.199 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:16.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:16.388 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:16.389 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:16.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:16.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:16.594 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:41:16.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:16.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:16.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:16.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:16.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:16.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:16.799 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:16.799 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:16.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:16.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:16.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:16.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:16.814 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:16.814 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:16.815 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:16.815 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:16.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:16.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:16.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:16.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:16.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:17.071 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:41:17.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:17.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:17.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:17.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:17.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:17.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:17.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:17.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:17.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:17.313 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:17.313 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:17.313 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:17.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:17.548 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:41:17.584 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:17.584 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:17.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:17.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:17.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:17.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:17.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:17.641 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:17.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:17.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:17.989 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:17.989 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:18.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:18.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:18.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:18.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:18.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:18.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:18.002 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:18.002 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:18.026 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:41:18.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:18.090 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:18.090 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:18.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:18.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:18.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:18.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:18.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:18.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:18.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:18.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:18.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:18.504 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:41:18.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:18.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:18.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:18.504 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:18.504 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:18.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:18.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:18.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:18.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:18.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:18.775 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:18.776 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:18.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:18.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:18.981 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:41:19.459 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:41:19.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:19.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:19.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:19.526 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:19.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:19.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:19.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:19.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:19.545 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:19.546 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:19.546 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:19.546 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:19.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:19.637 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:19.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:19.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:19.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:19.731 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:41:19.731 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 02:41:19.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:19.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:19.933 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:41:20.412 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:41:20.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:20.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:20.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:20.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:20.557 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:41:20.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:20.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:20.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:20.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:20.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:20.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:20.576 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:20.576 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:20.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:20.683 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:41:20.683 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-05 02:41:20.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:20.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:20.890 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:41:21.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:21.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:21.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:21.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:21.104 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:41:21.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:21.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:21.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:21.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:21.124 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:21.124 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:21.124 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:21.124 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:21.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:21.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:21.367 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:41:21.403 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:21.404 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:21.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:21.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:21.845 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:41:22.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:22.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:22.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:22.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:22.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:22.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:22.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:22.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:22.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:22.157 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:22.157 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:22.157 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:22.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:22.323 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:41:22.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:22.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:22.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:22.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:22.801 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:41:23.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:23.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:23.172 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:23.172 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:23.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:23.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:23.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:23.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:23.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:23.191 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:23.191 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:23.191 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:23.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:23.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:23.279 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:41:23.315 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:23.315 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:23.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:23.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:23.756 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:41:24.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:24.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:24.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:24.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:24.106 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:24.106 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:24.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:24.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:24.107 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:24.107 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:24.107 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:24.107 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:24.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:24.233 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:41:24.270 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:41:24.271 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:41:24.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:24.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:24.712 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:41:25.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:25.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:25.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:25.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:25.061 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:41:25.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:25.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:25.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:25.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:25.083 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:25.083 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:25.083 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:25.083 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:25.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:25.190 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:41:25.227 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:41:25.227 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:41:25.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:25.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:25.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:25.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:25.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:25.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:25.609 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:41:25.630 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:25.630 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:25.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:25.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:25.632 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:25.632 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:25.632 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:25.632 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:25.668 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:41:25.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:25.732 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:41:25.733 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:41:25.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:25.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:25.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:25.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:25.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:25.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:25.827 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:41:25.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:25.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:25.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:25.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:25.847 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:25.847 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:25.847 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:25.847 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:25.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:25.940 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:41:25.940 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:41:25.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:25.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:26.146 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:41:26.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:26.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:26.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:26.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:26.323 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:41:26.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:26.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:26.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:26.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:26.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:26.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:26.332 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:26.332 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:26.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:26.445 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:41:26.445 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:41:26.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:26.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:26.624 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:41:26.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:26.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:26.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:26.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:26.821 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:41:26.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:26.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:26.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:26.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:26.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:26.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:26.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:26.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:26.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:26.923 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:41:26.923 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:41:26.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:26.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:27.101 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:41:27.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:27.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:27.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:27.316 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:27.316 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:41:27.334 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:27.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:27.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:27.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:27.336 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:27.336 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:27.336 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:27.336 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:27.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:27.578 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:41:27.614 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:41:27.615 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:41:27.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:27.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:27.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:27.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:27.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:27.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:27.974 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:41:27.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:27.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:27.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:27.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:27.984 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:27.984 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:27.984 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:27.984 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:28.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:28.056 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:41:28.093 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:41:28.093 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:41:28.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:28.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:28.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:28.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:28.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:28.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:28.470 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:41:28.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:28.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:28.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:28.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:28.482 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:28.482 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:28.482 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:28.482 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:28.534 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:41:28.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:28.598 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:41:28.598 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:41:28.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:28.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:28.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:28.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:28.966 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:28.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:28.966 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:41:28.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:28.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:28.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:28.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:28.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:28.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:28.987 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:28.987 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:29.012 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:41:29.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:29.076 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:41:29.076 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:41:29.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:29.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:29.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:29.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:29.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:29.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:29.462 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:41:29.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:29.469 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:29.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:29.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:29.472 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:29.472 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:29.472 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:29.472 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:29.472 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:41:29.472 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:41:29.472 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:41:29.473 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2957 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:29.473 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2957 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:29.473 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2957 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:29.473 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2957 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:29.473 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2957 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:29.473 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2957 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:29.473 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2957 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:34.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:41:34.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:41:34.475 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:34.476 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:34.478 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:34.480 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:34.491 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:34.492 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:41:34.492 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:34.492 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:41:34.492 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:41:34.494 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:41:34.494 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:41:34.494 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:41:34.494 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:34.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:34.494 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:41:34.495 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:41:34.495 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:41:34.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:34.495 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:41:34.495 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:41:34.496 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:41:34.496 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:34.496 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:34.496 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:41:34.496 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:41:34.496 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:41:34.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:34.497 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:41:34.497 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:41:34.497 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:41:34.497 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:34.497 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:41:34.497 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:34.497 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:41:34.497 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:41:34.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:41:34.499 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:41:34.499 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:41:34.499 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:34.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:34.504 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:41:34.984 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:41:35.025 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:41:35.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.029 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:41:35.032 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:41:35.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:35.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:35.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:35.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.455 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:41:35.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:35.501 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:35.501 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:35.502 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:35.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.926 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:41:35.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:35.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.395 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:41:36.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:36.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:36.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:36.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:36.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:36.469 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:36.469 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:36.469 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:36.469 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:41:36.469 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:41:36.469 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:41:36.469 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:36.470 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=426 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:36.470 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=426 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:36.470 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=426 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:36.470 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=426 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:36.470 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=426 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:36.470 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=426 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:36.470 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=426 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:36.470 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=426 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:41.470 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:41:41.470 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:41:41.472 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:41.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:41.474 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:41.474 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:41.486 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:41.487 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:41:41.487 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:41.487 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:41:41.488 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:41:41.490 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:41:41.490 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:41:41.490 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:41:41.490 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:41.490 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:41.491 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:41:41.491 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:41:41.491 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:41:41.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:41.492 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:41:41.492 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:41:41.492 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:41:41.492 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:41.492 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:41:41.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:41.493 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:41:41.493 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:41:41.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:41.494 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:41:41.494 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:41:41.494 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:41:41.494 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:41.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:41.494 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:41:41.494 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:41:41.494 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:41:41.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:41.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:41:41.497 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:41:41.497 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:41:41.497 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:41.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:41.501 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:41:41.985 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:41:42.019 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:41:42.020 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:41:42.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:42.021 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:41:42.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:42.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:42.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:42.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:42.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:42.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:42.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:42.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:42.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:42.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:42.059 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:42.059 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:42.059 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:42.059 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:41:42.059 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:41:42.059 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:41:42.059 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:42.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:42.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:42.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:42.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:42.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:42.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:42.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:42.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:42.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:42.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:42.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:42.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:42.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:47.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:41:47.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:41:47.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:47.063 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:47.064 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:47.064 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:47.073 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:47.074 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:41:47.074 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:47.075 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:41:47.075 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:41:47.079 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:41:47.079 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:41:47.079 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:41:47.080 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:47.080 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:47.080 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:41:47.081 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:41:47.081 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:41:47.081 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:47.082 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:41:47.082 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:41:47.082 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:41:47.082 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:47.082 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:47.082 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:41:47.082 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:41:47.082 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:41:47.083 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:47.084 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:41:47.084 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:41:47.084 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:41:47.084 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:47.084 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:47.085 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:41:47.085 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:41:47.085 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:41:47.085 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:47.087 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:41:47.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:41:47.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:41:47.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:41:47.087 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:41:47.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:41:47.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:41:47.088 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:41:47.088 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:41:47.088 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:47.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:47.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:47.093 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:41:47.577 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:41:47.622 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:41:47.624 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:41:47.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:47.626 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:41:47.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:47.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:47.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:47.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:47.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:47.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:47.671 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:47.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:47.675 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:47.675 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:47.675 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:47.675 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:41:47.675 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:41:47.675 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:41:47.676 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:47.676 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:47.676 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:47.676 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:47.676 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:47.676 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:47.676 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:41:52.674 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:41:52.674 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:41:52.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:52.677 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:52.678 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:52.678 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:52.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:52.688 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:41:52.688 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:52.688 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:41:52.688 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:41:52.692 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:41:52.693 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:41:52.693 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:41:52.693 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:52.694 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:52.694 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:41:52.695 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:41:52.695 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:41:52.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:52.695 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:41:52.696 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:41:52.696 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:41:52.696 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:52.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:52.696 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:41:52.696 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:41:52.696 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:41:52.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:52.698 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:41:52.698 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:41:52.698 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:41:52.698 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:52.698 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:52.698 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:41:52.699 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:41:52.699 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:41:52.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:52.701 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:41:52.702 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:41:52.702 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:41:52.702 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:52.702 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:52.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:52.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:52.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:52.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:52.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:52.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:52.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:52.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:52.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:52.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:52.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:52.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:52.707 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:41:53.191 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:41:53.233 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:41:53.235 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:41:53.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:53.237 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:41:53.262 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:53.262 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:53.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:53.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:53.288 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:53.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:53.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:53.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:53.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:53.304 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:53.304 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:53.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:53.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:53.312 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:53.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:53.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:53.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:53.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:53.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:53.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:53.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:53.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:53.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:53.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:53.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:53.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:53.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:53.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:53.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:53.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:53.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:53.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:53.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:53.367 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:53.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:53.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:53.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:53.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:53.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:53.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:53.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:53.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:53.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:53.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:53.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:53.380 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:53.380 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:41:53.380 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:41:53.380 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:41:53.380 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:58.388 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:41:58.388 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:41:58.388 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:58.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:58.389 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:58.389 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:58.399 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:41:58.399 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:41:58.400 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:58.400 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:41:58.400 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:41:58.401 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:41:58.401 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:41:58.402 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:41:58.402 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:58.402 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:41:58.402 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:41:58.402 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:41:58.402 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:41:58.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:58.403 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:41:58.403 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:41:58.403 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:41:58.403 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:58.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:41:58.403 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:41:58.403 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:41:58.403 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:41:58.403 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:58.404 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:41:58.404 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:41:58.404 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:41:58.404 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:41:58.404 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:41:58.404 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:41:58.404 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:41:58.404 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:41:58.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:41:58.406 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:41:58.406 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:41:58.406 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:41:58.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:41:58.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:41:58.411 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:41:58.894 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:41:58.931 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:41:58.933 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:41:58.935 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:41:58.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:58.955 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:41:58.955 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:41:58.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:41:58.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:58.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:58.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:58.962 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:41:58.962 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:41:58.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:58.998 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:41:58.999 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:41:58.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:59.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:41:59.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:41:59.372 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:41:59.409 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:41:59.410 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:41:59.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:41:59.410 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:41:59.850 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:42:00.328 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:42:00.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:42:00.410 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:42:00.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:42:00.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:42:00.806 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:42:01.283 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:42:01.412 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:42:01.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:42:01.412 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:42:01.412 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:42:01.760 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:42:02.238 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:42:02.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:42:02.413 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:42:02.413 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:42:02.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:42:02.716 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:42:03.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:03.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:03.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:03.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:03.116 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:03.116 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:03.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:42:03.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:03.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:03.118 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:03.118 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:42:03.118 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:42:03.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:03.144 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:03.144 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:03.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:03.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:03.194 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:42:03.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:42:03.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:42:03.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:42:03.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:42:03.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:03.672 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:42:04.150 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:42:04.627 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:42:05.105 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:42:05.583 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:42:06.061 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:42:06.539 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:42:07.016 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:42:07.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:07.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:07.420 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:07.420 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:07.429 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:07.429 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:07.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:42:07.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:07.430 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:07.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:07.431 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:42:07.431 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:42:07.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:07.435 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:07.435 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:07.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:07.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:07.493 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:42:07.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:07.971 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:42:08.448 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:42:08.926 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:42:09.403 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:42:09.882 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:42:10.359 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:42:10.837 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:42:11.314 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:42:11.792 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:42:11.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:11.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:11.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:11.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:11.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:11.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:11.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:42:11.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:11.946 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:11.946 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:11.946 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:42:11.946 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:42:11.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:11.985 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:11.986 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:11.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:11.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:12.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:12.269 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:42:12.747 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:42:13.225 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:42:13.704 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:42:14.181 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:42:14.659 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:42:15.137 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:42:15.615 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:42:16.093 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:42:16.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:16.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:16.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:16.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:16.269 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:16.269 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:16.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:42:16.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:16.271 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:16.271 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:16.271 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:42:16.271 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:42:16.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:16.276 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:16.276 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:16.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:16.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:16.570 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:42:16.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:17.048 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:42:17.526 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:42:18.005 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:42:18.482 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:42:18.960 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:42:19.438 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:42:19.916 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:42:20.394 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:42:20.871 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:42:20.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:20.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:20.917 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:20.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:20.936 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:20.936 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:20.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:42:20.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:20.937 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:20.937 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:20.938 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:42:20.938 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:42:20.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:20.973 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:42:20.974 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 02:42:20.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:20.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:21.349 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:42:21.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:21.828 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:42:22.306 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:42:22.783 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:42:23.262 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:42:23.739 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:42:24.218 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:42:24.696 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:42:25.174 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:42:25.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:25.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:25.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:25.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:25.370 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:42:25.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:25.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:25.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:42:25.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:25.394 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:25.394 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:25.394 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:42:25.394 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:42:25.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:25.412 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:42:25.413 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-05 02:42:25.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:25.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:25.652 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:42:25.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:26.131 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:42:26.609 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:42:27.088 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:42:27.566 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:42:28.045 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 02:42:28.523 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 02:42:29.002 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 02:42:29.481 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 02:42:29.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:29.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:29.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:29.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:29.816 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:42:29.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:29.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:29.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:42:29.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:29.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:29.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:29.835 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:42:29.835 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:42:29.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:42:29.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:29.859 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:29.859 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:29.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:29.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:29.958 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 02:42:30.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:30.436 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 02:42:30.914 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 02:42:31.392 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 02:42:31.870 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 02:42:32.348 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 02:42:32.827 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 02:42:33.305 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 02:42:33.783 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 02:42:34.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:34.261 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 02:42:34.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:34.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:34.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:34.281 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:34.281 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:34.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:42:34.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:34.283 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:34.283 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:34.283 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:42:34.283 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:42:34.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:34.315 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:34.315 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:34.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:34.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:34.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:34.739 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 02:42:35.217 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 02:42:35.695 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 02:42:36.173 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 02:42:36.651 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 02:42:37.129 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 02:42:37.606 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 02:42:38.084 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 02:42:38.562 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 02:42:38.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:38.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:38.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:38.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:38.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:38.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:38.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:42:38.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:38.730 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:38.730 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:38.730 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:42:38.730 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:42:38.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:42:38.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:38.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:38.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:38.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:38.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:39.040 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 02:42:39.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:39.518 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 02:42:39.996 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 02:42:40.474 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 02:42:40.952 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 02:42:41.430 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 02:42:41.908 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 02:42:42.386 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 02:42:42.863 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 02:42:43.341 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 02:42:43.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:43.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:43.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:43.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:43.540 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:43.540 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:43.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:42:43.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:43.541 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:43.542 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:43.542 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:42:43.542 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:42:43.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:43.587 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:42:43.587 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:42:43.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:43.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:43.814 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 02:42:44.284 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 02:42:44.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:44.757 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 02:42:45.235 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 02:42:45.714 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 02:42:46.193 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 02:42:46.671 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 02:42:47.150 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 02:42:47.629 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 02:42:48.107 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 02:42:48.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:48.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:48.386 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:48.386 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:48.386 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:42:48.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:48.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:48.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:42:48.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:48.409 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:48.409 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:48.409 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:42:48.409 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:42:48.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:48.442 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:42:48.442 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:42:48.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:48.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:48.585 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 02:42:48.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:49.063 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 02:42:49.541 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 02:42:50.019 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 02:42:50.498 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 02:42:50.977 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 02:42:51.454 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 02:42:51.933 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 02:42:52.411 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 02:42:52.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:52.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:52.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:52.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:52.830 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:42:52.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:52.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:52.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:42:52.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:52.853 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:52.853 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:52.853 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:42:52.853 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:42:52.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:52.889 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 02:42:52.892 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:42:52.892 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:42:52.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:52.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:53.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:53.360 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 02:42:53.838 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 02:42:54.316 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 02:42:54.794 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 02:42:55.271 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 02:42:55.749 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 02:42:56.228 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 02:42:56.706 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 02:42:57.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:57.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:57.050 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:57.050 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:57.050 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:42:57.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:42:57.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:42:57.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:42:57.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:57.070 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:42:57.070 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:42:57.070 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:42:57.070 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:42:57.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:57.078 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:42:57.078 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:42:57.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:57.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:42:57.183 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 02:42:57.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:42:57.661 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 02:42:58.139 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 02:42:58.617 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 02:42:59.095 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-05 02:42:59.574 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-05 02:43:00.051 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-05 02:43:00.529 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-05 02:43:01.008 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-05 02:43:01.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:01.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:01.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:01.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:01.362 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:01.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:01.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:01.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:01.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:01.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:01.373 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:01.373 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:01.373 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:01.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:01.380 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:01.381 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:01.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:01.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:01.484 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-05 02:43:01.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:01.962 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-05 02:43:02.441 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-05 02:43:02.919 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-05 02:43:03.397 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-05 02:43:03.876 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-05 02:43:04.354 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-05 02:43:04.832 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-05 02:43:05.303 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-05 02:43:05.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:05.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:05.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:05.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:05.682 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:05.693 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:05.693 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:05.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:05.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:05.694 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:05.694 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:05.694 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:05.694 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:05.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:05.733 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:05.733 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:05.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:05.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:05.777 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-05 02:43:05.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:06.253 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-05 02:43:06.731 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-05 02:43:07.208 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-05 02:43:07.686 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-05 02:43:08.164 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-05 02:43:08.642 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-05 02:43:09.119 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-05 02:43:09.597 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-05 02:43:09.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:09.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:09.989 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:09.989 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:09.990 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:10.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:10.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:10.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:10.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:10.011 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:10.011 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:10.011 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:10.011 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:10.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:10.016 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:10.016 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:10.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:10.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:10.074 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-05 02:43:10.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:10.552 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-05 02:43:11.029 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-05 02:43:11.507 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-05 02:43:11.985 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-05 02:43:12.463 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-05 02:43:12.941 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-05 02:43:13.419 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-05 02:43:13.897 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-05 02:43:14.375 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-05 02:43:14.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:14.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:14.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:14.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:14.470 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:14.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:14.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:14.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:14.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:14.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:14.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:14.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:14.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:14.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:14.522 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:14.522 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:14.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:14.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:14.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:14.849 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-05 02:43:15.328 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-05 02:43:15.806 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-05 02:43:16.283 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-05 02:43:16.760 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-05 02:43:17.239 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-05 02:43:17.717 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-05 02:43:18.194 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-05 02:43:18.673 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-05 02:43:18.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:18.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:18.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:18.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:18.790 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:18.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:18.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:18.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:18.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:18.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:18.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:18.811 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:18.811 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:18.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:18.868 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:18.868 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:18.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:18.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:19.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:19.150 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-05 02:43:19.627 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-05 02:43:20.105 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-05 02:43:20.583 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-05 02:43:21.061 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-05 02:43:21.538 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-05 02:43:22.016 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-05 02:43:22.495 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-05 02:43:22.973 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-05 02:43:23.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:23.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:23.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:23.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:23.121 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:23.142 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:23.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:23.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:23.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:23.144 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:23.144 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:23.144 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:23.144 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:23.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:23.160 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:23.160 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:23.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:23.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:23.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:23.450 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-05 02:43:23.928 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-05 02:43:24.406 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-05 02:43:24.884 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-05 02:43:25.363 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-05 02:43:25.841 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-05 02:43:26.319 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-05 02:43:26.798 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-05 02:43:27.276 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-05 02:43:27.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:27.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:27.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:27.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:27.424 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:27.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:27.437 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:27.437 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:27.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:27.441 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:43:27.441 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:43:27.441 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:43:27.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:43:27.442 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:43:27.442 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:43:27.442 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:43:27.442 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19009 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:27.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19009 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:27.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19009 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:27.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19009 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:27.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19009 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:27.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19009 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:27.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19010 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:27.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19010 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:27.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19010 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:27.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19010 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:27.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19010 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:27.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19010 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:27.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19010 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:27.444 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=19010 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:32.439 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:43:32.439 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:43:32.440 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:43:32.442 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:43:32.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:43:32.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:43:32.450 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:43:32.451 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:43:32.451 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:43:32.451 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:43:32.451 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:43:32.453 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:43:32.454 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:43:32.454 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:43:32.454 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:43:32.455 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:43:32.455 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:43:32.455 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:43:32.455 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:43:32.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:32.456 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:43:32.456 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:43:32.456 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:43:32.456 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:43:32.457 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:43:32.457 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:43:32.457 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:43:32.457 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:43:32.457 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:32.458 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:43:32.458 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:43:32.458 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:43:32.458 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:43:32.459 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:43:32.459 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:43:32.459 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:43:32.459 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:43:32.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:32.461 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:43:32.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:43:32.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:43:32.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:43:32.461 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:43:32.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:43:32.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:43:32.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:43:32.462 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:43:32.462 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:43:32.462 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:32.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:32.463 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:43:32.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:32.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:32.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:32.463 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:43:32.463 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:43:32.463 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:43:32.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:32.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:32.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:37.470 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:43:37.470 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:43:37.470 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:43:37.470 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:43:37.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:43:37.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:43:37.479 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:43:37.481 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:43:37.481 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:43:37.482 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:43:37.482 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:43:37.485 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:43:37.486 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:43:37.486 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:43:37.487 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:43:37.487 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:43:37.487 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:43:37.488 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:43:37.488 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:43:37.488 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:37.489 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:43:37.489 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:43:37.490 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:43:37.490 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:43:37.490 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:43:37.490 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:43:37.490 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:43:37.490 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:43:37.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:37.492 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:43:37.492 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:43:37.492 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:43:37.492 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:43:37.492 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:43:37.493 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:43:37.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:43:37.493 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:43:37.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:37.496 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:43:37.496 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:43:37.496 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:43:37.497 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:37.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:37.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:37.502 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:43:37.984 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:43:38.028 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:43:38.030 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:43:38.032 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:43:38.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:38.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:38.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:38.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:38.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:38.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:38.066 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:38.066 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:38.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:38.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:38.085 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:38.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:38.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:38.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:38.197 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:38.197 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:38.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:38.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.199 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:38.199 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:38.199 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:38.199 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:38.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:38.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:38.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:38.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.460 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:43:38.499 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:38.500 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:38.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:38.504 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:38.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:38.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:38.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:38.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:38.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:38.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:38.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.701 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:38.701 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:38.701 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:38.701 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:38.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:38.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:38.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:38.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:38.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:38.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:38.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:38.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:38.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:38.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.911 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:38.911 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:38.911 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:38.911 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:38.937 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:43:38.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:38.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:38.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:38.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:38.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:39.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:39.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:39.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:39.396 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:39.414 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:43:39.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:39.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:39.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:39.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:39.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:39.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:39.418 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:39.418 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:39.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:39.474 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:39.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:39.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:39.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:39.500 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:39.501 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:39.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:39.505 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:39.892 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:43:39.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:39.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:39.930 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:39.931 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:39.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:39.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:39.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:39.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:39.946 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:39.946 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:39.946 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:39.946 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:39.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:39.994 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:39.995 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 02:43:39.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:39.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:40.366 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:43:40.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:40.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:40.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:40.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:40.472 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:40.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:40.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:40.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:40.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:40.492 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:40.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:40.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:40.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:40.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:40.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:40.501 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:40.503 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:40.504 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-05 02:43:40.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:40.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:40.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:40.506 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:40.843 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:43:41.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:41.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:41.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:41.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:41.021 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:41.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:41.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:41.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:41.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:41.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:41.042 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:41.042 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:41.042 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:41.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:41.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:41.090 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:41.090 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:41.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:41.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:41.322 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:43:41.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:41.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:41.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:41.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:41.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:41.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:41.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:41.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:41.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:41.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:41.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:41.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:41.590 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:41.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:41.590 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:41.590 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:41.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:41.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:41.642 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:41.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:41.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:41.799 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:43:42.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:42.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:42.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:42.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:42.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:42.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:42.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:42.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:42.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:42.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:42.136 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:42.136 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:42.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:42.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:42.186 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:42.187 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:42.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:42.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:42.277 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:43:42.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:42.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:42.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:42.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:42.751 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:43:43.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:43.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:43.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:43.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:43.022 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=1183 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:43.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:43.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:43.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:43.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:43.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:43.042 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:43.043 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:43.043 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:43.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:43.095 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:43.095 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:43:43.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:43.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:43.228 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:43:43.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:43.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:43.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:43.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:43.518 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:43.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:43.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:43.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:43.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:43.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:43.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:43.539 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:43.539 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:43.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:43.590 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:43.590 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:43:43.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:43.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:43.706 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:43:44.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:44.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:44.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:44.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:44.060 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:44.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:44.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:44.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:44.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:44.083 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:44.083 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:44.083 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:44.083 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:44.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:44.137 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:44.137 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:44.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:44.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:44.183 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:43:44.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:44.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:44.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:44.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:44.344 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:44.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:44.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:44.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:44.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:44.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:44.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:44.365 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:44.365 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:44.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:44.427 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:44.427 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:44.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:44.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:44.657 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:43:44.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:44.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:44.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:44.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:44.833 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:44.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:44.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:44.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:44.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:44.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:44.854 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:44.854 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:44.855 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:44.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:44.906 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:44.906 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:44.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:44.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:45.133 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:43:45.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:45.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:45.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:45.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:45.331 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:45.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:45.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:45.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:45.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:45.354 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:45.354 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:45.354 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:45.354 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:45.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:45.406 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:45.406 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:45.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:45.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:45.611 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:43:45.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:45.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:45.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:45.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:45.825 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:45.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:45.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:45.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:45.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:45.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:45.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:45.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:45.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:45.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:45.889 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:45.889 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:45.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:45.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:46.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:46.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:46.006 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:46.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:46.006 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:46.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:46.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:46.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:46.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:46.027 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:46.027 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:46.027 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:46.027 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:46.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:46.087 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:43:46.091 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:46.091 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:46.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:46.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:46.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:46.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:46.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:46.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:46.501 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:46.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:46.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:46.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:46.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:46.522 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:46.522 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:46.522 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:46.522 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:46.565 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:43:46.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:46.574 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:46.574 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:46.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:46.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:46.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:46.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:46.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:46.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:46.997 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:47.006 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:47.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:47.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:47.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:47.008 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:47.008 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:47.008 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:47.008 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:47.042 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:43:47.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:47.062 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:47.062 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:43:47.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:47.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:47.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:47.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:47.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:47.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:47.492 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:43:47.497 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:47.498 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:47.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:47.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:47.498 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:43:47.498 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:43:47.498 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:43:47.498 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:43:47.498 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:43:47.498 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:43:47.498 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:43:52.501 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:43:52.502 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:43:52.505 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:43:52.505 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:43:52.505 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:43:52.505 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:43:52.514 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:43:52.515 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:43:52.515 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:43:52.516 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:43:52.516 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:43:52.520 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:43:52.520 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:43:52.520 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:43:52.520 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:43:52.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:43:52.520 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:43:52.521 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:43:52.521 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:43:52.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:52.524 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:43:52.524 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:43:52.524 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:43:52.524 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:43:52.524 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:43:52.524 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:43:52.524 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:43:52.524 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:43:52.525 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:52.527 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:43:52.527 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:43:52.527 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:43:52.527 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:43:52.527 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:43:52.527 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:43:52.527 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:43:52.528 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:43:52.528 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:52.531 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:43:52.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:43:52.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:43:52.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:43:52.531 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:43:52.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:43:52.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:43:52.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:43:52.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:43:52.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:52.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:43:52.532 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:43:52.532 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:43:52.532 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:52.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:52.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:43:52.537 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:43:53.021 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:43:53.055 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:43:53.056 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:43:53.057 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:43:53.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:53.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:53.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:53.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:53.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:53.079 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:53.080 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:53.080 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:53.080 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:53.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:53.124 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:53.125 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:53.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:53.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:53.498 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:43:53.535 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:53.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:53.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:53.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:53.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:53.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:53.975 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:43:54.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:54.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:54.180 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:54.180 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:54.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:54.199 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:54.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:54.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:54.202 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:54.202 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:54.202 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:54.202 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:54.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:54.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:54.252 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:54.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:54.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:54.453 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:43:54.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:54.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:54.537 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:54.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:54.930 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:43:55.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:55.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:55.408 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:43:55.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:55.537 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:55.537 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:55.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:55.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:55.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:55.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:55.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:55.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:55.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:55.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:55.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:55.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:55.642 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:55.642 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:55.642 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:55.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:55.694 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:55.694 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:55.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:55.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:55.886 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:43:56.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:56.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:56.363 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:43:56.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:56.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:56.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:56.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:56.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:56.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:56.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:56.803 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:56.813 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:56.813 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:56.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:56.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:56.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:56.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:56.815 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:56.815 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:56.841 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:43:56.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:56.867 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:56.867 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:56.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:56.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:57.318 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:43:57.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:43:57.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:43:57.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:43:57.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:43:57.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:57.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:57.796 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:43:58.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:58.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:58.255 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:58.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:58.255 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=1223 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:43:58.274 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:43:58.275 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:58.275 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:58.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:58.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:58.277 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:58.277 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:58.277 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:58.277 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:58.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:58.329 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:58.329 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:58.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:58.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:58.751 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:43:59.220 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:43:59.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:59.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:59.690 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:43:59.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:59.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:59.816 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:59.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:59.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:43:59.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:43:59.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:43:59.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:59.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:43:59.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:43:59.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:43:59.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:43:59.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:43:59.876 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:43:59.876 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 02:43:59.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:43:59.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:00.166 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:44:00.640 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:44:00.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:00.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:01.113 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:44:01.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:01.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:01.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:01.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:01.332 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:01.332 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=1885 tn=1 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:44:01.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:01.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:01.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:01.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:01.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:01.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:01.352 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:01.352 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:01.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:01.405 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:44:01.405 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-05 02:44:01.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:01.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:01.588 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:44:02.059 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:44:02.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:02.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:02.528 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:44:02.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:02.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:02.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:02.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:02.833 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:02.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:02.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:02.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:02.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:02.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:02.854 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:02.854 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:02.854 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:02.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:44:02.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:02.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:02.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:02.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:02.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:02.997 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:44:03.472 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:44:03.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:03.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:03.946 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:44:04.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:04.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:04.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:04.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:04.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:04.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:04.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:04.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:04.346 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:04.346 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:04.346 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:04.346 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:04.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:04.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:04.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:04.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:04.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:04.419 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:44:04.893 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:44:05.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:05.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:05.368 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:44:05.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:05.844 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:44:05.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:05.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:05.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:05.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:05.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:05.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:05.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:05.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:05.868 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:05.868 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:05.868 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:05.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:44:05.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:05.923 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:05.923 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:05.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:05.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:06.319 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:44:06.794 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:44:07.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:07.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:07.268 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:44:07.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:07.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:07.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:07.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:07.742 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:44:07.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:07.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:07.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:07.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:07.746 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:07.746 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:07.746 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:07.746 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:07.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:07.799 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:44:07.799 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:44:07.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:07.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:08.215 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:44:08.683 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:44:08.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:08.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:09.151 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:44:09.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:09.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:09.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:09.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:09.166 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:09.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:09.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:09.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:09.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:09.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:09.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:09.178 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:09.178 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:09.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:09.225 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:44:09.225 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:44:09.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:09.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:09.622 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:44:10.097 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:44:10.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:10.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:10.568 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:44:10.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:10.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:10.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:10.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:10.668 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:10.687 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:10.687 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:10.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:10.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:10.689 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:10.689 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:10.689 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:10.689 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:10.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:10.732 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:44:10.732 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:44:10.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:10.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:11.038 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:44:11.514 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:44:11.667 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:11.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:11.990 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:44:12.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:12.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:12.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:12.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:12.144 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:12.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:12.151 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:12.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:12.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:12.154 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:12.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:12.154 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:12.154 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:12.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:12.196 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:44:12.196 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:44:12.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:12.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:12.461 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:44:12.932 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:44:13.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:13.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:13.405 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:44:13.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:13.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:13.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:13.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:13.575 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:13.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:13.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:13.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:13.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:13.583 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:13.583 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:13.583 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:13.583 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:13.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:13.639 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:44:13.639 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:44:13.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:13.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:13.875 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:44:14.348 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:44:14.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:14.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:14.822 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:44:15.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:15.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:15.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:15.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:15.013 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:15.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:15.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:15.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:15.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:15.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:15.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:15.030 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:15.030 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:15.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:15.078 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:44:15.078 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:44:15.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:15.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:15.297 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:44:15.771 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:44:15.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:15.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:16.246 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:44:16.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:16.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:16.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:16.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:16.455 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:16.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:16.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:16.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:16.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:16.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:16.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:16.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:16.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:16.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:16.508 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:44:16.508 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:44:16.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:16.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:16.718 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:44:17.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:17.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:17.193 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:44:17.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:17.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:17.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:17.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:17.587 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:17.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:17.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:17.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:17.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:17.611 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:17.611 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:17.611 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:17.611 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:17.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:17.662 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:44:17.662 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:44:17.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:17.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:17.666 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:44:18.139 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:44:18.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:18.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:18.614 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:44:19.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:19.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:19.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:19.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:19.024 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:19.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:19.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:19.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:19.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:19.035 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:19.035 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:19.036 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:19.036 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:19.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:19.080 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:44:19.080 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:44:19.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:19.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:19.085 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:44:19.560 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:44:19.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:19.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:20.034 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:44:20.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:20.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:20.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:20.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:20.466 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:20.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:20.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:20.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:20.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:20.478 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:20.478 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:20.478 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:20.478 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:20.506 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:44:20.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:20.526 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:44:20.526 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:44:20.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:20.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:20.974 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:44:21.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:21.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:21.443 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:44:21.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:21.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:21.892 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:21.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:21.893 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:21.898 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:44:21.898 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:44:21.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:44:21.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:44:21.898 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:44:21.898 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:44:21.898 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:44:21.898 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:44:21.898 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:44:21.898 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:44:21.899 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:44:21.899 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:44:21.899 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:44:26.901 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:44:26.901 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:44:26.903 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:44:26.904 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:44:26.905 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:44:26.905 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:44:26.913 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:44:26.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:44:26.914 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:44:26.914 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:44:26.915 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:44:26.916 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:44:26.917 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:44:26.917 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:44:26.917 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:44:26.917 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:44:26.917 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:44:26.917 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:44:26.917 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:44:26.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:44:26.919 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:44:26.919 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:44:26.919 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:44:26.919 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:44:26.919 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:44:26.919 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:44:26.919 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:44:26.919 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:44:26.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:44:26.921 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:44:26.921 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:44:26.921 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:44:26.921 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:44:26.921 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:44:26.921 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:44:26.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:44:26.922 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:44:26.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:44:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:44:26.925 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:44:26.925 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:44:26.925 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:44:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:44:26.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:44:26.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:44:26.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:44:26.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:44:26.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:44:26.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:44:26.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:44:26.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:44:26.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:44:26.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:44:26.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:44:26.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:44:26.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:44:26.930 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:44:27.411 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:44:27.451 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:44:27.453 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:44:27.454 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:44:27.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:27.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:27.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:27.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:27.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:27.472 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:27.472 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:27.472 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:27.472 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:27.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:27.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:27.515 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:27.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:27.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:27.886 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:44:27.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:44:27.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:44:27.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:44:27.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:44:28.364 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:44:28.842 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:44:28.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:44:28.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:44:28.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:44:28.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:44:29.320 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:44:29.796 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:44:29.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:44:29.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:44:29.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:44:29.933 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:44:30.273 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:44:30.752 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:44:30.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:44:30.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:44:30.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:44:30.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:44:31.230 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:44:31.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:31.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:31.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:31.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:31.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:31.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:31.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:31.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:31.455 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:31.455 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:31.455 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:31.455 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:31.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:31.507 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:31.507 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:31.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:31.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:31.707 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:44:31.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:44:31.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:44:31.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:44:31.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:44:32.184 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:44:32.662 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:44:33.140 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:44:33.618 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:44:34.095 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:44:34.573 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:44:35.051 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:44:35.529 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:44:35.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:35.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:35.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:35.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:35.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:35.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:35.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:35.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:35.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:35.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:35.774 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:35.774 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:35.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:35.821 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:35.822 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:35.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:35.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:36.006 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:44:36.484 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:44:36.961 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:44:37.439 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:44:37.917 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:44:38.394 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:44:38.871 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:44:39.349 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:44:39.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:39.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:39.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:39.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:39.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:39.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:39.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:39.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:39.811 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:39.811 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:39.811 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:39.811 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:39.827 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:44:39.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:39.863 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:39.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:39.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:39.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:40.304 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:44:40.782 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:44:41.260 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:44:41.738 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:44:42.216 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:44:42.694 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:44:43.171 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:44:43.649 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:44:44.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:44.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:44.108 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:44.108 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:44.126 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:44.126 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:44:44.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:44.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:44.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:44.129 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:44.129 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:44.129 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:44.129 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:44.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:44.180 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:44.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:44.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:44.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:44.604 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:44:45.081 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:44:45.559 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:44:46.037 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:44:46.514 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:44:46.992 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:44:47.470 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:44:47.948 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:44:48.426 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:44:48.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:48.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:48.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:48.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:48.834 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=4680 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:44:48.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:48.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:48.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:48.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:48.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:48.854 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:48.854 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:48.854 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:48.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:48.903 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:44:48.906 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:44:48.906 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 02:44:48.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:48.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:49.382 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:44:49.860 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:44:50.339 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:44:50.817 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:44:51.295 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:44:51.774 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:44:52.252 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:44:52.731 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:44:53.209 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:44:53.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:53.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:53.290 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:53.290 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:53.290 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:53.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:53.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:53.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:53.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:53.309 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:53.309 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:53.309 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:53.309 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:53.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:53.360 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:44:53.361 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-05 02:44:53.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:53.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:53.686 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:44:54.164 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:44:54.643 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:44:55.120 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:44:55.589 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:44:56.061 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:44:56.539 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 02:44:57.013 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 02:44:57.482 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 02:44:57.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:57.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:57.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:57.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:57.706 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:44:57.725 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:44:57.725 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:44:57.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:44:57.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:57.728 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:57.728 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:57.728 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:44:57.728 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:44:57.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:44:57.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:44:57.779 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:44:57.779 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:44:57.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:57.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:44:57.956 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 02:44:58.434 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 02:44:58.912 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 02:44:59.390 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 02:44:59.868 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 02:45:00.346 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 02:45:00.824 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 02:45:01.302 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 02:45:01.780 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 02:45:02.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:02.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:02.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:02.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:02.164 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:02.164 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:02.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:45:02.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:02.166 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:02.166 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:02.166 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:45:02.166 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:45:02.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:02.213 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:02.214 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:02.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:02.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:02.258 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 02:45:02.736 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 02:45:03.214 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 02:45:03.692 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 02:45:04.171 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 02:45:04.648 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 02:45:05.126 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 02:45:05.604 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 02:45:06.082 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 02:45:06.560 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 02:45:06.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:06.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:06.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:06.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:06.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:06.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:06.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:45:06.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:06.619 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:06.619 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:06.619 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:45:06.619 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:45:06.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:45:06.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:06.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:06.671 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:06.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:06.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:07.037 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 02:45:07.514 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 02:45:07.993 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 02:45:08.470 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 02:45:08.948 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 02:45:09.425 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 02:45:09.904 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 02:45:10.382 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 02:45:10.860 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 02:45:10.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:10.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:10.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:10.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:10.945 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:10.945 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:10.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:45:10.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:10.948 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:10.948 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:10.948 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:45:10.948 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:45:10.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:11.003 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:45:11.003 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:45:11.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:11.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:11.332 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 02:45:11.804 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 02:45:12.274 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 02:45:12.745 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 02:45:13.225 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 02:45:13.703 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 02:45:14.182 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 02:45:14.661 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 02:45:15.140 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 02:45:15.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:15.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:15.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:15.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:15.285 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:45:15.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:15.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:15.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:45:15.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:15.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:15.304 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:15.304 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:45:15.304 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:45:15.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:15.354 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:45:15.355 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:45:15.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:15.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:15.612 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 02:45:16.082 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 02:45:16.553 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 02:45:17.024 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 02:45:17.494 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 02:45:17.971 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 02:45:18.449 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 02:45:18.928 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 02:45:19.407 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 02:45:19.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:19.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:19.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:19.696 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:19.696 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:45:19.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:19.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:19.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:45:19.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:19.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:19.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:19.719 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:45:19.719 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:45:19.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:19.775 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:45:19.775 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:45:19.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:19.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:19.881 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 02:45:20.360 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 02:45:20.838 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 02:45:21.310 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 02:45:21.788 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 02:45:22.267 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 02:45:22.745 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 02:45:23.224 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 02:45:23.699 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 02:45:23.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:23.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:23.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:23.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:23.860 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:45:23.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:23.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:23.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:45:23.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:23.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:23.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:23.881 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:45:23.881 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:45:23.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:23.945 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:45:23.945 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:45:23.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:23.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:24.177 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 02:45:24.656 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 02:45:25.134 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 02:45:25.612 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 02:45:26.090 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 02:45:26.569 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 02:45:27.047 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 02:45:27.525 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-05 02:45:28.004 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-05 02:45:28.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:28.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:28.181 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:28.181 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:28.181 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:45:28.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:28.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:28.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:45:28.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:28.203 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:28.203 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:28.203 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:45:28.203 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:45:28.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:28.275 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:45:28.275 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:45:28.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:28.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:28.482 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-05 02:45:28.960 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-05 02:45:29.439 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-05 02:45:29.918 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-05 02:45:30.396 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-05 02:45:30.875 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-05 02:45:31.353 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-05 02:45:31.831 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-05 02:45:32.310 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-05 02:45:32.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:32.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:32.506 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:32.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:32.507 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:45:32.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:32.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:32.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:45:32.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:32.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:32.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:32.529 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:45:32.529 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:45:32.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:32.578 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:45:32.578 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:45:32.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:32.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:32.786 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-05 02:45:33.260 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-05 02:45:33.736 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-05 02:45:34.215 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-05 02:45:34.710 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-05 02:45:35.189 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-05 02:45:35.667 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-05 02:45:36.145 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-05 02:45:36.624 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-05 02:45:36.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:36.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:36.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:36.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:36.839 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:45:36.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:36.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:36.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:45:36.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:36.861 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:36.861 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:36.861 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:45:36.862 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:45:36.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:36.913 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:45:36.913 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:45:36.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:36.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:37.100 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-05 02:45:37.578 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-05 02:45:38.056 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-05 02:45:38.533 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-05 02:45:39.011 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-05 02:45:39.489 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-05 02:45:39.968 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-05 02:45:40.446 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-05 02:45:40.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:40.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:40.840 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:40.840 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:40.840 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:45:40.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:40.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:40.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:45:40.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:40.863 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:40.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:40.864 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:45:40.864 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:45:40.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:40.923 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-05 02:45:40.924 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:45:40.924 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:45:40.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:40.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:41.402 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-05 02:45:41.880 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-05 02:45:42.359 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-05 02:45:42.838 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-05 02:45:43.316 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-05 02:45:43.794 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-05 02:45:44.273 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-05 02:45:44.751 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-05 02:45:45.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:45.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:45.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:45.165 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:45.165 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:45:45.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:45.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:45.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:45:45.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:45.184 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:45.185 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:45.185 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:45:45.185 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:45:45.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:45.229 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-05 02:45:45.234 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:45:45.234 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:45:45.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:45.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:45.707 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-05 02:45:46.185 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-05 02:45:46.664 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-05 02:45:47.142 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-05 02:45:47.620 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-05 02:45:48.098 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-05 02:45:48.576 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-05 02:45:49.054 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-05 02:45:49.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:49.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:49.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:49.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:49.486 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:45:49.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:49.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:49.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:45:49.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:49.507 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:45:49.507 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:45:49.507 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:45:49.507 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:45:49.533 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-05 02:45:49.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:49.559 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:45:49.559 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:45:49.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:49.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:50.012 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-05 02:45:50.490 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-05 02:45:50.967 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-05 02:45:51.445 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-05 02:45:51.924 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-05 02:45:52.402 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-05 02:45:52.880 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-05 02:45:53.359 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-05 02:45:53.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:45:53.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:45:53.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:45:53.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:45:53.810 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:45:53.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:45:53.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:45:53.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:45:53.824 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:45:53.826 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:45:53.826 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:45:53.826 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:45:53.826 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:45:53.826 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:45:53.826 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:45:53.826 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:45:53.826 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18564 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.826 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18564 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.826 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18564 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.827 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18564 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.827 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18564 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.827 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18564 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.827 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18564 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.827 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18565 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.827 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18565 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.827 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18565 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.827 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18565 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.827 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18565 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.827 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18565 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.827 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18565 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:53.827 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=18565 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:45:58.827 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:45:58.827 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:45:58.828 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:45:58.829 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:45:58.830 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:45:58.830 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:45:58.837 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:45:58.837 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:45:58.838 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:45:58.838 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:45:58.838 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:45:58.840 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:45:58.840 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:45:58.841 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:45:58.841 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:45:58.841 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:45:58.841 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:45:58.842 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:45:58.842 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:45:58.842 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:45:58.842 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:45:58.842 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:45:58.843 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:45:58.843 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:45:58.843 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:45:58.843 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:45:58.843 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:45:58.843 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:45:58.843 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:45:58.845 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:45:58.845 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:45:58.845 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:45:58.845 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:45:58.845 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:45:58.845 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:45:58.845 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:45:58.845 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:45:58.845 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:45:58.847 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:45:58.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:45:58.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:45:58.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:45:58.847 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:45:58.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:45:58.848 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:45:58.848 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:45:58.848 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:45:58.848 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:45:58.849 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:45:58.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:45:58.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:45:58.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:45:58.849 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:45:58.849 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:45:58.849 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:45:58.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:45:58.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:45:58.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:46:03.853 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:46:03.853 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:46:03.855 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:46:03.856 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:46:03.857 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:46:03.857 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:46:03.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:46:03.867 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:46:03.867 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:46:03.868 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:46:03.868 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:46:03.871 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:46:03.872 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:46:03.872 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:46:03.872 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:46:03.873 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:46:03.873 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:46:03.874 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:46:03.874 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:46:03.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:46:03.874 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:46:03.875 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:46:03.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:46:03.875 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:46:03.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:46:03.875 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:46:03.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:46:03.875 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:46:03.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:46:03.877 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:46:03.877 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:46:03.877 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:46:03.877 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:46:03.877 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:46:03.877 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:46:03.877 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:46:03.877 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:46:03.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:46:03.880 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:46:03.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:46:03.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:46:03.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:46:03.880 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:46:03.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:46:03.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:46:03.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:46:03.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:46:03.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:46:03.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:46:03.880 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:46:03.881 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:46:03.881 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:46:03.881 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:46:03.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:46:03.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:46:03.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:46:03.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:46:03.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:46:03.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:46:03.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:46:03.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:46:03.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:46:03.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:46:03.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:46:03.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:46:03.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:46:03.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:46:03.886 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:46:04.370 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:46:04.410 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:46:04.412 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:46:04.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:04.414 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:46:04.441 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:04.441 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:04.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:46:04.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:04.446 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:04.446 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:04.446 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:46:04.447 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:46:04.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:04.471 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:04.471 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:04.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:04.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:04.847 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:46:04.884 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:46:04.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:46:04.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:46:04.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:46:05.324 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:46:05.802 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:46:05.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:46:05.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:46:05.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:46:05.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:46:06.280 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:46:06.758 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:46:06.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:46:06.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:46:06.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:46:06.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:46:07.236 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:46:07.713 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:46:07.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:46:07.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:46:07.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:46:07.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:46:08.191 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:46:08.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:08.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:08.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:08.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:08.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:08.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:08.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:46:08.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:08.551 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:08.551 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:08.551 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:46:08.551 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:46:08.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:08.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:08.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:08.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:08.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:08.668 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:46:08.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:46:08.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:46:08.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:46:08.891 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:46:09.146 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:46:09.624 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:46:10.102 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:46:10.580 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:46:11.057 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:46:11.534 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:46:12.011 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:46:12.489 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:46:12.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:12.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:12.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:12.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:12.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:12.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:12.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:46:12.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:12.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:12.868 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:12.868 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:46:12.868 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:46:12.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:12.937 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:12.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:12.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:12.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:12.966 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:46:13.445 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:46:13.922 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:46:14.401 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:46:14.878 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:46:15.356 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:46:15.833 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:46:16.311 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:46:16.789 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:46:17.266 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:46:17.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:17.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:17.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:17.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:17.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:17.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:17.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:46:17.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:17.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:17.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:17.386 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:46:17.386 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:46:17.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:17.434 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:17.434 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:17.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:17.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:17.741 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:46:18.220 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:46:18.697 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:46:19.175 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:46:19.653 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:46:20.130 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:46:20.608 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:46:21.086 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:46:21.563 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:46:21.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:21.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:21.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:21.679 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:21.696 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:21.696 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:21.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:46:21.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:21.699 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:21.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:21.699 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:46:21.699 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:46:21.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:21.752 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:21.752 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:21.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:21.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:22.041 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:46:22.518 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:46:22.996 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:46:23.473 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:46:23.951 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:46:24.429 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:46:24.907 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:46:25.389 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:46:25.867 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:46:26.346 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:46:26.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:26.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:26.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:26.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:26.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:26.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:26.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:46:26.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:26.379 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:26.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:26.379 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:46:26.379 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:46:26.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:26.430 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:46:26.430 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 02:46:26.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:26.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:26.824 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:46:27.302 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:46:27.781 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:46:28.260 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:46:28.738 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:46:29.216 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:46:29.695 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:46:30.173 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:46:30.652 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:46:30.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:30.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:30.816 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:30.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:30.816 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:46:30.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:30.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:30.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:46:30.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:30.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:30.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:30.838 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:46:30.838 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:46:30.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:30.894 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:46:30.894 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-05 02:46:30.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:30.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:31.129 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:46:31.608 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:46:32.087 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:46:32.564 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:46:33.043 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:46:33.521 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 02:46:34.000 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 02:46:34.478 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 02:46:34.956 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 02:46:35.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:35.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:35.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:35.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:35.265 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:46:35.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:35.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:35.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:46:35.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:35.285 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:35.285 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:35.285 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:46:35.285 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:46:35.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:46:35.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:35.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:35.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:35.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:35.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:35.434 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 02:46:35.912 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 02:46:36.391 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 02:46:36.869 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 02:46:37.346 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 02:46:37.824 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 02:46:38.302 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 02:46:38.779 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 02:46:39.257 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 02:46:39.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:39.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:39.713 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:39.713 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:39.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:39.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:39.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:46:39.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:39.734 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:39.734 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:39.734 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:46:39.734 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:46:39.735 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 02:46:39.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:39.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:39.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:39.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:39.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:40.213 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 02:46:40.691 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 02:46:41.169 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 02:46:41.647 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 02:46:42.126 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 02:46:42.604 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 02:46:43.081 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 02:46:43.560 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 02:46:44.038 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 02:46:44.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:44.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:44.156 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:44.156 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:44.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:44.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:44.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:46:44.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:44.176 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:44.176 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:44.176 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:46:44.176 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:46:44.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:46:44.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:44.226 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:44.226 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:44.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:44.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:44.515 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 02:46:44.993 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 02:46:45.472 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 02:46:45.950 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 02:46:46.427 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 02:46:46.905 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 02:46:47.383 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 02:46:47.861 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 02:46:48.340 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 02:46:48.817 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 02:46:49.295 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 02:46:49.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:49.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:49.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:49.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:49.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:49.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:49.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:46:49.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:49.481 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:49.481 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:49.481 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:46:49.481 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:46:49.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:49.541 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:46:49.541 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:46:49.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:49.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:49.773 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 02:46:50.251 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 02:46:50.730 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 02:46:51.209 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 02:46:51.687 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 02:46:52.166 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 02:46:52.645 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 02:46:53.124 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 02:46:53.602 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 02:46:54.081 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 02:46:54.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:54.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:54.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:54.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:54.337 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:46:54.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:54.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:54.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:46:54.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:54.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:54.354 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:54.354 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:46:54.354 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:46:54.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:54.400 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:46:54.401 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:46:54.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:54.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:54.559 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 02:46:55.037 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 02:46:55.516 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 02:46:55.995 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 02:46:56.473 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 02:46:56.952 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 02:46:57.430 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 02:46:57.909 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 02:46:58.388 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 02:46:58.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:58.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:58.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:58.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:58.787 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:46:58.805 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:46:58.805 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:46:58.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:46:58.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:58.808 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:46:58.808 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:46:58.808 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:46:58.808 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:46:58.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:46:58.866 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:46:58.866 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:46:58.867 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 02:46:58.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:58.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:46:59.345 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 02:46:59.823 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 02:47:00.301 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 02:47:00.780 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 02:47:01.258 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 02:47:01.755 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 02:47:02.233 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 02:47:02.711 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 02:47:02.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:02.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:02.982 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:02.982 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:02.982 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:47:02.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:02.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:02.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:03.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:03.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:03.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:03.002 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:03.002 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:03.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:03.050 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:47:03.050 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:47:03.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:03.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:03.189 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 02:47:03.667 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 02:47:04.145 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 02:47:04.623 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-05 02:47:05.100 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-05 02:47:05.578 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-05 02:47:06.056 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-05 02:47:06.534 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-05 02:47:07.013 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-05 02:47:07.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:07.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:07.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:07.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:07.323 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:47:07.324 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=13533 tn=1 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:47:07.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:07.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:07.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:07.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:07.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:07.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:07.343 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:07.343 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:07.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:07.394 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:47:07.394 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:47:07.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:07.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:07.490 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-05 02:47:07.968 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-05 02:47:08.445 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-05 02:47:08.923 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-05 02:47:09.401 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-05 02:47:09.879 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-05 02:47:10.358 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-05 02:47:10.836 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-05 02:47:11.314 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-05 02:47:11.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:11.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:11.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:11.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:11.642 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:47:11.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:11.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:11.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:11.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:11.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:11.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:11.656 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:11.656 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:11.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:11.709 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:47:11.710 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:47:11.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:11.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:11.792 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-05 02:47:12.270 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-05 02:47:12.748 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-05 02:47:13.226 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-05 02:47:13.705 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-05 02:47:14.183 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-05 02:47:14.661 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-05 02:47:15.139 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-05 02:47:15.617 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-05 02:47:15.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:15.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:15.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:15.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:15.964 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:47:15.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:15.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:15.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:15.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:15.985 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:15.985 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:15.985 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:15.986 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:16.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:16.036 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:47:16.036 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:47:16.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:16.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:16.095 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-05 02:47:16.573 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-05 02:47:17.051 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-05 02:47:17.529 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-05 02:47:18.007 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-05 02:47:18.485 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-05 02:47:18.963 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-05 02:47:19.440 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-05 02:47:19.919 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-05 02:47:20.396 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-05 02:47:20.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:20.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:20.446 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:20.446 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:20.447 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:47:20.456 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:20.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:20.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:20.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:20.458 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:20.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:20.458 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:20.458 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:20.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:20.507 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:47:20.507 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:47:20.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:20.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:20.874 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-05 02:47:21.352 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-05 02:47:21.830 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-05 02:47:22.308 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-05 02:47:22.787 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-05 02:47:23.265 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-05 02:47:23.739 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-05 02:47:24.217 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-05 02:47:24.696 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-05 02:47:24.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:24.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:24.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:24.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:24.766 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:47:24.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:24.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:24.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:24.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:24.788 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:24.788 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:24.788 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:24.788 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:24.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:24.842 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:47:24.842 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:47:24.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:24.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:25.173 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-05 02:47:25.652 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-05 02:47:26.130 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-05 02:47:26.608 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-05 02:47:27.086 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-05 02:47:27.565 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-05 02:47:28.043 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-05 02:47:28.521 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-05 02:47:28.999 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-05 02:47:29.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:29.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:29.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:29.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:29.085 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:47:29.104 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:29.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:29.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:29.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:29.106 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:29.106 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:29.106 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:29.106 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:29.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:29.154 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:47:29.155 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:47:29.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:29.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:29.478 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-05 02:47:29.956 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-05 02:47:30.435 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-05 02:47:30.913 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-05 02:47:31.392 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-05 02:47:31.870 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-05 02:47:32.349 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-05 02:47:32.827 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-05 02:47:33.305 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-05 02:47:33.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:33.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:33.406 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:33.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:33.407 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:47:33.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:47:33.413 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:47:33.413 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:47:33.413 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:47:33.413 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:47:33.413 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:47:33.413 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:47:33.413 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:47:33.413 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:47:33.413 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:47:33.414 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:47:38.417 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:47:38.417 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:47:38.419 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:47:38.419 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:47:38.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:47:38.420 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:47:38.429 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:47:38.429 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:47:38.429 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:47:38.430 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:47:38.430 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:47:38.431 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:47:38.432 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:47:38.432 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:47:38.432 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:47:38.432 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:47:38.432 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:47:38.433 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:47:38.433 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:47:38.433 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:47:38.433 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:47:38.433 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:47:38.434 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:47:38.434 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:47:38.434 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:47:38.434 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:47:38.434 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:47:38.434 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:47:38.434 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:47:38.435 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:47:38.435 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:47:38.435 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:47:38.435 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:47:38.435 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:47:38.435 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:47:38.436 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:47:38.436 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:47:38.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:47:38.437 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:47:38.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:47:38.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:47:38.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:47:38.438 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:47:38.438 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:47:38.438 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:38.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:47:38.439 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:47:38.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:38.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:38.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:47:38.439 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:47:38.439 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:47:38.439 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:47:38.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:38.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:38.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:47:43.446 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:47:43.446 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:47:43.446 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:47:43.446 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:47:43.446 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:47:43.446 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:47:43.456 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:47:43.458 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:47:43.458 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:47:43.459 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:47:43.459 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:47:43.463 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:47:43.463 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:47:43.464 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:47:43.464 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:47:43.464 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:47:43.465 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:47:43.465 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:47:43.465 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:47:43.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:47:43.466 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:47:43.466 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:47:43.466 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:47:43.466 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:47:43.467 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:47:43.467 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:47:43.467 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:47:43.467 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:47:43.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:47:43.469 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:47:43.469 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:47:43.469 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:47:43.469 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:47:43.469 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:47:43.469 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:47:43.470 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:47:43.470 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:47:43.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:47:43.472 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:47:43.472 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:43.473 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:47:43.473 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:47:43.473 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:47:43.473 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:47:43.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:47:43.475 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:47:43.475 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:47:43.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:47:43.475 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:47:43.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:47:43.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:47:43.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:47:43.478 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:47:43.963 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:47:44.004 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:47:44.006 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:47:44.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:44.008 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:47:44.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:44.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:44.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:44.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:44.039 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:44.039 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:44.039 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:44.039 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:44.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:44.061 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:44.062 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:44.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:44.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:44.440 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:47:44.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:47:44.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:47:44.477 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:47:44.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:47:44.917 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:47:45.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:45.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:45.123 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:45.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:45.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:45.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:45.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:45.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:45.141 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:45.141 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:45.141 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:45.141 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:45.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:45.189 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:45.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:45.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:45.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:45.394 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:47:45.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:47:45.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:47:45.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:47:45.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:47:45.872 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:47:46.350 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:47:46.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:47:46.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:47:46.480 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:47:46.483 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:47:46.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:46.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:46.572 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:46.572 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:46.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:46.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:46.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:46.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:46.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:46.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:46.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:46.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:46.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:46.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:46.642 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:46.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:46.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:46.827 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:47:47.304 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:47:47.480 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:47:47.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:47:47.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:47:47.484 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:47:47.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:47.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:47.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:47.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:47.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:47.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:47.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:47.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:47.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:47.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:47.766 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:47.766 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:47.782 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:47:47.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:47.819 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:47.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:47.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:47.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:48.260 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:47:48.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:47:48.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:47:48.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:47:48.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:47:48.737 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:47:49.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:49.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:49.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:49.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:49.196 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=1223 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:47:49.215 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:47:49.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:49.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:49.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:49.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:49.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:49.219 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:49.219 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:49.219 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:49.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:49.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:49.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:49.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:49.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:49.692 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:47:50.170 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:47:50.648 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:47:50.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:50.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:50.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:50.779 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:50.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:50.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:50.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:50.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:50.801 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:50.801 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:50.801 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:50.801 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:50.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:50.850 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:47:50.850 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 02:47:50.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:50.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:51.125 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:47:51.603 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:47:52.082 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:47:52.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:52.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:52.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:52.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:52.301 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:47:52.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:52.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:52.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:52.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:52.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:52.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:52.322 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:52.322 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:52.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:52.372 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:47:52.372 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-05 02:47:52.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:52.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:52.559 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:47:53.036 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:47:53.513 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:47:53.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:53.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:53.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:53.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:53.820 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:47:53.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:53.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:53.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:53.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:53.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:53.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:53.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:53.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:53.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:47:53.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:53.895 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:53.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:53.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:53.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:53.988 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:47:54.467 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:47:54.945 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:47:55.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:55.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:55.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:55.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:55.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:55.357 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:55.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:55.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:55.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:55.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:55.360 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:55.360 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:55.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:55.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:55.412 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:55.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:55.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:55.423 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:47:55.901 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:47:56.379 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:47:56.858 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:47:56.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:56.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:56.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:56.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:56.879 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:56.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:56.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:56.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:56.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:56.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:56.881 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:56.881 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:56.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:47:56.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:56.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:56.931 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:56.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:56.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:57.335 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:47:57.813 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:47:58.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:58.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:58.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:58.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:58.279 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:58.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:58.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:58.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:58.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:58.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:58.282 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:58.282 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:58.291 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:47:58.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:58.348 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:47:58.348 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:47:58.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:58.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:58.769 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:47:59.248 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:47:59.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:59.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:59.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:59.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:59.726 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:47:59.726 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:47:59.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:47:59.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:47:59.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:47:59.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:59.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:47:59.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:47:59.747 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:47:59.747 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:47:59.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:47:59.798 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:47:59.798 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:47:59.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:47:59.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:00.205 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:48:00.683 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:48:01.162 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:48:01.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:01.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:01.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:01.258 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:01.258 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:48:01.276 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:01.276 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:01.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:01.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:01.278 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:01.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:01.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:01.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:01.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:01.331 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:48:01.331 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:48:01.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:01.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:01.638 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:48:02.115 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:48:02.593 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:48:02.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:02.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:02.753 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:02.753 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:02.753 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:48:02.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:02.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:02.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:02.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:02.775 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:02.775 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:02.775 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:02.775 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:02.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:02.839 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:48:02.839 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:48:02.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:02.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:03.068 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:48:03.544 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:48:04.022 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:48:04.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:04.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:04.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:04.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:04.201 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:48:04.221 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:04.221 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:04.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:04.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:04.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:04.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:04.223 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:04.223 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:04.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:04.274 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:48:04.274 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:48:04.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:04.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:04.501 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:48:04.979 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:48:05.457 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:48:05.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:05.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:05.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:05.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:05.654 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:48:05.671 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:05.671 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:05.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:05.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:05.673 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:05.673 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:05.673 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:05.673 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:05.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:05.726 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:48:05.726 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:48:05.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:05.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:05.935 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:48:06.413 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:48:06.891 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:48:07.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:07.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:07.106 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:07.106 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:07.106 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:48:07.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:07.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:07.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:07.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:07.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:07.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:07.117 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:07.117 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:07.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:07.169 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:48:07.170 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:48:07.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:07.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:07.368 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:48:07.847 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:48:08.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:08.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:08.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:08.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:08.267 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:48:08.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:08.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:08.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:08.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:08.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:08.279 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:08.279 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:08.279 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:08.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:08.325 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:48:08.329 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:48:08.329 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:48:08.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:08.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:08.802 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:48:09.279 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:48:09.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:09.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:09.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:09.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:09.692 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:48:09.712 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:09.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:09.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:09.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:09.715 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:09.715 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:09.715 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:09.715 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:09.754 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:48:09.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:09.765 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:48:09.766 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:48:09.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:09.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:10.228 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:48:10.706 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:48:11.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:11.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:11.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:11.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:11.140 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:48:11.159 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:11.159 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:11.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:11.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:11.161 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:11.161 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:11.162 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:11.162 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:11.185 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:48:11.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:11.211 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:48:11.211 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:48:11.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:11.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:11.664 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:48:12.141 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:48:12.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:12.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:12.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:12.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:12.591 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:48:12.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:12.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:12.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:12.601 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:12.604 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:48:12.604 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:48:12.604 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:48:12.604 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:48:12.604 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:48:12.604 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:48:12.604 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6221 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.604 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:12.605 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6222 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:17.605 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:48:17.605 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:48:17.607 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:48:17.608 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:48:17.609 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:48:17.609 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:48:17.614 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:48:17.615 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:48:17.616 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:48:17.616 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:48:17.616 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:48:17.619 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:48:17.619 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:48:17.619 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:48:17.620 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:48:17.620 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:48:17.620 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:48:17.621 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:48:17.621 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:48:17.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:17.621 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:48:17.621 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:48:17.622 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:48:17.622 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:48:17.622 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:48:17.622 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:48:17.622 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:48:17.622 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:48:17.622 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:17.624 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:48:17.624 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:48:17.624 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:48:17.624 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:48:17.624 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:48:17.624 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:48:17.624 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:48:17.624 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:48:17.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:17.626 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:48:17.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:48:17.627 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:48:17.627 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:48:17.627 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:17.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:17.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:17.632 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:48:18.112 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:48:18.154 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:48:18.155 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:48:18.156 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:48:18.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:18.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:18.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:18.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:18.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:18.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:18.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:18.175 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:18.175 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:18.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:48:18.213 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:18.213 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:18.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:18.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:18.586 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:48:18.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:18.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:18.631 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:18.633 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:19.064 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:48:19.542 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:48:19.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:19.631 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:19.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:19.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:20.020 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:48:20.498 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:48:20.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:20.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:20.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:20.636 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:20.976 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:48:21.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:21.454 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:48:21.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:21.633 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:21.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:21.636 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:21.931 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:48:22.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:22.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:22.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:22.007 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:22.007 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=936 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:22.007 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=936 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:22.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:22.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:22.009 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:22.009 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:22.010 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:22.010 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:22.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:48:22.025 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:22.025 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:22.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:22.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:22.408 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:48:22.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:22.634 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:22.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:22.637 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:22.886 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:48:23.364 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:48:23.841 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:48:24.320 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:48:24.798 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:48:25.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:25.276 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:48:25.754 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:48:25.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:25.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:25.902 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:25.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:25.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:25.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:25.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:25.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:25.922 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:25.922 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:25.922 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:25.922 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:25.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:48:25.971 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:48:25.971 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:48:25.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:25.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:26.232 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:48:26.710 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:48:27.188 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:48:27.667 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:48:28.146 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:48:28.624 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:48:28.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:29.103 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:48:29.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:29.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:29.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:29.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:29.559 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:48:29.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:29.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:29.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:29.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:29.561 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:29.561 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:29.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:48:29.576 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:48:29.576 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:48:29.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:29.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:29.581 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:48:30.060 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:48:30.540 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:48:31.019 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:48:31.497 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:48:31.976 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:48:32.454 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:48:32.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:32.933 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:48:32.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:32.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:32.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:32.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:32.981 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:48:33.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:33.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:33.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:33.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:33.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:33.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:33.002 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:33.002 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:33.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:48:33.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:33.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:33.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:33.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:33.410 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:48:33.888 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:48:34.365 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:48:34.843 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:48:35.320 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:48:35.798 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:48:36.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:36.276 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:48:36.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:36.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:36.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:36.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:36.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:36.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:36.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:36.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:36.719 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:36.719 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:36.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:48:36.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:36.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:36.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:36.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:36.753 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:48:37.231 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:48:37.709 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:48:38.187 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:48:38.664 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:48:39.143 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:48:39.620 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:48:39.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:40.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:40.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:40.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:40.062 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:40.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:40.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:40.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:40.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:40.075 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:40.075 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:40.076 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:40.076 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:40.097 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:48:40.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:48:40.123 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:48:40.123 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:48:40.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:40.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:40.566 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:48:41.037 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:48:41.515 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:48:41.994 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:48:42.472 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:48:42.951 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:48:43.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:43.430 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:48:43.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:43.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:43.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:43.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:43.824 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:48:43.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:43.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:43.825 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:43.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:43.825 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:43.825 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:43.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:48:43.852 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:48:43.852 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:48:43.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:43.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:43.908 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:48:44.387 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:48:44.866 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:48:45.344 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:48:45.822 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:48:46.300 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:48:46.779 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:48:46.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:47.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:47.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:47.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:47.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:47.174 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:48:47.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:47.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:47.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:47.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:47.187 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:48:47.187 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:48:47.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:48:47.188 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:48:47.188 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:48:47.188 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:48:47.188 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:48:47.188 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6312 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:47.188 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6312 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:47.188 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6312 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:47.188 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6312 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:47.188 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6312 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:47.188 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6312 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:47.188 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6312 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:52.191 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:48:52.191 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:48:52.191 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:48:52.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:48:52.191 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:48:52.191 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:48:52.204 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:48:52.206 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:48:52.206 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:48:52.206 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:48:52.207 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:48:52.211 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:48:52.212 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:48:52.213 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:48:52.213 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:48:52.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:48:52.214 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:48:52.214 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:48:52.214 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:48:52.215 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:52.215 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:48:52.216 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:48:52.216 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:48:52.216 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:48:52.216 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:48:52.217 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:48:52.217 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:48:52.217 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:48:52.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:52.218 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:48:52.218 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:48:52.218 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:48:52.219 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:48:52.219 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:48:52.219 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:48:52.219 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:48:52.219 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:48:52.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:52.222 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:48:52.223 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:48:52.223 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:48:52.223 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:52.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:52.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:52.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:52.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:52.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:52.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:52.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:48:52.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:52.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:48:52.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:48:52.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:52.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:52.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:52.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:48:52.228 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:48:52.712 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:48:52.750 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:48:52.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:52.751 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:48:52.752 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:48:52.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:52.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:52.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:52.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:52.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:52.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:52.779 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:52.779 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:52.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:48:52.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:52.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:52.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:52.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:53.189 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:48:53.226 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:53.226 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:53.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:53.230 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:53.667 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:48:54.145 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:48:54.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:54.227 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:54.228 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:54.231 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:54.622 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:48:55.100 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:48:55.228 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:55.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:55.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:55.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:55.578 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:48:55.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:56.056 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:48:56.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:56.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:56.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:56.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:56.534 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:48:56.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:56.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:56.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:48:56.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:48:56.609 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=936 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:56.609 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=936 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:48:56.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:48:56.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:56.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:56.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:56.610 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:48:56.610 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:48:56.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:48:56.628 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:48:56.629 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:48:56.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:56.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:48:57.012 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:48:57.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:48:57.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:48:57.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:48:57.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:48:57.489 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:48:57.967 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:48:58.445 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:48:58.923 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:48:59.402 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:48:59.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:48:59.879 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:49:00.357 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:49:00.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:00.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:00.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:00.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:00.507 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=1768 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:00.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:00.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:00.507 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:00.508 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:00.508 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:00.508 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:00.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:00.544 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:00.544 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:00.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:00.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:00.836 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:49:01.313 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:49:01.791 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:49:02.269 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:49:02.747 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:49:03.224 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:49:03.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:03.702 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:49:04.180 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:49:04.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:04.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:04.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:04.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:04.403 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=2600 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:04.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:04.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:04.404 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:04.404 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:04.404 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:04.404 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:04.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:04.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:04.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:04.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:04.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:04.657 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:49:04.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:05.135 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:49:05.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:05.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:05.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:05.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:05.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:05.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:05.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:05.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:05.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:05.396 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:05.396 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:05.396 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:05.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:05.444 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:49:05.445 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:49:05.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:05.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:05.613 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:49:06.091 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:49:06.570 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:49:07.048 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:49:07.520 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:49:07.990 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:49:08.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:08.461 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:49:08.939 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:49:09.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:09.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:09.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:09.015 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:09.016 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:49:09.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:09.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:09.017 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:09.017 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:09.018 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:09.018 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:09.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:09.034 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:49:09.034 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:49:09.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:09.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:09.418 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:49:09.897 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:49:10.376 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:49:10.854 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:49:11.333 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:49:11.811 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:49:12.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:12.290 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:49:12.763 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:49:12.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:12.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:12.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:12.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:12.911 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:49:12.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:12.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:12.911 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:12.912 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:12.912 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:12.912 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:12.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:12.947 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:49:12.947 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:49:12.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:12.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:13.233 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:49:13.712 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:49:14.191 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:49:14.669 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:49:15.148 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:49:15.627 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:49:15.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:16.105 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:49:16.584 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:49:16.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:16.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:16.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:16.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:16.807 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:49:16.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:16.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:16.809 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:16.809 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:16.810 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:16.810 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:16.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:16.820 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:49:16.820 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:49:16.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:16.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:17.062 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:49:17.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:17.540 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:49:17.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:17.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:17.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:17.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:17.782 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:49:17.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:17.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:17.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:17.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:17.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:17.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:17.805 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:17.805 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:17.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:17.851 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:17.851 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:17.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:17.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:18.018 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:49:18.495 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:49:18.974 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:49:19.451 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:49:19.929 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:49:20.407 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:49:20.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:20.885 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:49:21.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:21.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:21.325 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:21.325 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:21.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:21.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:21.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:21.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:21.326 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:21.326 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:21.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:21.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:21.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:21.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:21.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:21.362 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:49:21.841 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 02:49:22.319 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 02:49:22.797 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 02:49:23.274 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 02:49:23.752 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 02:49:24.229 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 02:49:24.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:24.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:24.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:24.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:24.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:24.669 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=6931 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:24.670 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=6931 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:24.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:24.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:24.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:24.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:24.670 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:24.670 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:24.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:24.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:24.703 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:24.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:24.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:24.707 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 02:49:25.184 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 02:49:25.662 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 02:49:26.140 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 02:49:26.617 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 02:49:27.095 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 02:49:27.573 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 02:49:27.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:28.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:28.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:28.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:28.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:28.013 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=7645 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:28.013 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=7645 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:28.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:28.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:28.014 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:28.014 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:28.014 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:28.014 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:28.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:28.045 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:28.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:28.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:28.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:28.050 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 02:49:28.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:28.528 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 02:49:28.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:28.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:28.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:28.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:28.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:28.978 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:28.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:28.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:28.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:28.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:28.980 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:28.980 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:29.006 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 02:49:29.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:29.032 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:49:29.032 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:49:29.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:29.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:29.484 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 02:49:29.963 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 02:49:30.441 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 02:49:30.919 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 02:49:31.398 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 02:49:31.876 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 02:49:32.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:32.354 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 02:49:32.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:32.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:32.748 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:32.748 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:32.749 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:49:32.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:32.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:32.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:32.749 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:32.749 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:32.750 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:32.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:32.776 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:49:32.776 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:49:32.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:32.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:32.832 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 02:49:33.310 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 02:49:33.788 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 02:49:34.267 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 02:49:34.745 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 02:49:35.224 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 02:49:35.702 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 02:49:35.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:36.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:36.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:36.097 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:36.097 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:36.097 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:49:36.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:36.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:36.098 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:36.098 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:36.098 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:36.098 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:36.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:36.124 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:49:36.124 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:49:36.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:36.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:36.180 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 02:49:36.658 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 02:49:37.136 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 02:49:37.615 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 02:49:38.092 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 02:49:38.570 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 02:49:39.048 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 02:49:39.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:39.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:39.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:39.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:39.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:39.443 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:49:39.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:39.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:39.444 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:39.444 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:39.444 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:39.444 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:39.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:49:39.470 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:49:39.470 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:49:39.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:39.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:39.526 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 02:49:40.004 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 02:49:40.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:40.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:40.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:40.400 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:40.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:40.400 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:49:40.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:49:40.411 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:49:40.412 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:49:40.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:49:40.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:49:40.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:49:40.416 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:49:40.416 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:49:40.416 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:49:40.416 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:49:40.416 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:49:40.416 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=10291 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:40.417 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=10291 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:40.417 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=10291 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:40.417 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=10291 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:40.417 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=10291 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:40.417 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=10291 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:45.417 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:49:45.417 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:49:45.417 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:49:45.417 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:49:45.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:49:45.417 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:49:45.424 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:49:45.424 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:49:45.424 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:49:45.424 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:49:45.424 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:49:45.426 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:49:45.426 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:49:45.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:49:45.426 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:49:45.426 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:49:45.427 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:49:45.427 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:49:45.427 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:49:45.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:49:45.430 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:49:45.430 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:49:45.430 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:49:45.430 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:49:45.430 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:49:45.430 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:49:45.430 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:49:45.430 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:49:45.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:49:45.433 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:49:45.433 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:49:45.433 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:49:45.433 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:49:45.433 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:49:45.433 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:49:45.433 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:49:45.433 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:49:45.433 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:49:45.437 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:49:45.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:49:45.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:49:45.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:49:45.437 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:49:45.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:49:45.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:49:45.438 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:49:45.438 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:49:45.438 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:45.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:45.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:45.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:45.443 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:49:45.926 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:49:45.966 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:49:45.967 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:49:45.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:49:45.969 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:49:45.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:45.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:45.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:49:45.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:49:45.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:49:45.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:49:45.974 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:49:45.974 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:49:46.398 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:49:46.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:49:46.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:49:46.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:49:46.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:49:46.876 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:49:47.353 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:49:47.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:49:47.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:49:47.444 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:49:47.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:49:47.831 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:49:48.307 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:49:48.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:49:48.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:49:48.445 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:49:48.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:49:48.786 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:49:49.257 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:49:49.444 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:49:49.444 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:49:49.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:49:49.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:49:49.729 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:49:50.205 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:49:50.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:49:50.446 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:49:50.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:49:50.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:49:50.680 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:49:51.150 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:49:51.620 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:49:52.090 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:49:52.560 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:49:53.037 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:49:53.509 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:49:53.980 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:49:54.450 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:49:54.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:49:54.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:49:54.835 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:49:54.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:49:54.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:49:54.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:49:54.839 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:49:54.839 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:49:54.840 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:49:54.840 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:49:54.840 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:49:54.840 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:49:54.840 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:49:54.840 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:54.840 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:54.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:54.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:54.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:54.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:49:59.838 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:49:59.838 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:49:59.839 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:49:59.840 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:49:59.841 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:49:59.841 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:49:59.847 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:49:59.849 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:49:59.849 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:49:59.849 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:49:59.849 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:49:59.854 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:49:59.854 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:49:59.854 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:49:59.854 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:49:59.854 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:49:59.854 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:49:59.854 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:49:59.855 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:49:59.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:49:59.857 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:49:59.857 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:49:59.857 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:49:59.857 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:49:59.858 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:49:59.858 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:49:59.858 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:49:59.858 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:49:59.858 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:49:59.860 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:49:59.860 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:49:59.860 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:49:59.860 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:49:59.860 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:49:59.860 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:49:59.860 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:49:59.860 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:49:59.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:49:59.863 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:49:59.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:49:59.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:49:59.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:49:59.863 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:49:59.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:49:59.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:49:59.864 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:49:59.864 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:49:59.864 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:59.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:59.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:49:59.869 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:50:00.351 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:50:00.411 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:50:00.412 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:50:00.413 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:50:00.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:00.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:00.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:00.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:00.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:00.416 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:00.416 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:00.416 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:00.416 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:00.828 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:50:00.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:00.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:00.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:00.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:01.302 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:50:01.772 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:50:01.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:01.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:01.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:01.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:02.242 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:50:02.712 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:50:02.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:02.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:02.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:02.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:03.190 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:50:03.662 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:50:03.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:03.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:03.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:03.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:04.133 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:50:04.604 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:50:04.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:04.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:04.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:04.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:05.075 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:50:05.551 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:50:06.029 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:50:06.504 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:50:06.974 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:50:07.444 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:50:07.914 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:50:08.386 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:50:08.856 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:50:09.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:09.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:09.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:09.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:09.243 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:09.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:09.246 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:50:09.246 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:50:09.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:50:09.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:50:09.247 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:50:09.247 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:50:09.247 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:50:09.247 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.247 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.247 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2024 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2025 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2025 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2025 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2025 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2025 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2025 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2025 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:09.248 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2025 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:14.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:50:14.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:50:14.248 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:50:14.249 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:50:14.250 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:50:14.250 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:50:14.263 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:50:14.264 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:50:14.264 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:14.264 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:50:14.265 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:50:14.266 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:50:14.267 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:50:14.267 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:50:14.267 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:14.267 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:50:14.268 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:50:14.268 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:50:14.268 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:50:14.268 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:14.269 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:50:14.269 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:50:14.269 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:50:14.269 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:14.269 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:50:14.269 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:50:14.269 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:50:14.269 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:50:14.269 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:14.271 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:50:14.271 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:50:14.271 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:50:14.271 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:14.271 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:50:14.271 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:50:14.271 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:50:14.271 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:50:14.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:50:14.274 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:50:14.274 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:50:14.274 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:14.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:14.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:14.279 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:50:14.764 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:50:14.797 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:50:14.798 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:50:14.799 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:50:14.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:14.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:14.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:14.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:15.242 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:50:15.278 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:15.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:15.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:15.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:15.722 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:50:15.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:15.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:15.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:15.803 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:15.803 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:16.197 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:50:16.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:16.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:16.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:16.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:16.675 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:50:17.147 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:50:17.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:17.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:17.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:17.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:17.620 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:50:18.096 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:50:18.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:18.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:18.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:18.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:18.569 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:50:19.040 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:50:19.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:19.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:19.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:19.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:19.510 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:50:19.980 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:50:20.451 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:50:20.921 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:50:21.392 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:50:21.863 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:50:22.335 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:50:22.807 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:50:23.279 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:50:23.753 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:50:24.225 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:50:24.696 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:50:25.174 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:50:25.651 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:50:26.129 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:50:26.607 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:50:27.084 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:50:27.562 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:50:27.602 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:27.602 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:27.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:27.608 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:27.608 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:27.608 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:27.610 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:50:27.610 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:50:27.610 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:50:27.610 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:50:27.610 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:50:27.610 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:50:27.610 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:50:27.610 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2868 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:27.610 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2868 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:27.610 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2868 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:27.610 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2868 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:27.610 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2868 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:27.610 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2868 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:32.610 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:50:32.610 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:50:32.614 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:50:32.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:50:32.614 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:50:32.614 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:50:32.623 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:50:32.625 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:50:32.625 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:32.626 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:50:32.626 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:50:32.630 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:50:32.631 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:50:32.631 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:50:32.631 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:32.631 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:50:32.631 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:50:32.631 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:50:32.632 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:50:32.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:32.634 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:50:32.634 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:50:32.634 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:50:32.634 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:32.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:50:32.634 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:50:32.634 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:50:32.634 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:50:32.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:32.636 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:50:32.636 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:50:32.636 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:50:32.636 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:32.637 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:50:32.637 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:50:32.637 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:50:32.637 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:50:32.637 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:50:32.639 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:50:32.639 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:50:32.639 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:50:32.639 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:32.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:32.644 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:50:33.128 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:50:33.165 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:50:33.167 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:50:33.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:33.169 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:50:33.172 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:33.172 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:33.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:33.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:33.172 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:33.173 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:33.173 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:33.173 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:33.606 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:50:33.642 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:33.642 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:33.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:33.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:34.083 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:50:34.219 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:50:34.560 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:50:34.643 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:34.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:34.644 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:34.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:34.763 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:50:35.038 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:50:35.286 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:50:35.515 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:50:35.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:35.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:35.645 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:35.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:35.993 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:50:36.471 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:50:36.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:36.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:36.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:36.650 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:36.948 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:50:37.308 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:50:37.426 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:50:37.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:37.647 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:37.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:37.651 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:37.817 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:50:37.904 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:50:38.341 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:50:38.381 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:50:38.858 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:50:38.871 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:50:39.335 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:50:39.813 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:50:40.291 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:50:40.769 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:50:40.892 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:50:41.246 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:50:41.724 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:50:42.202 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:50:42.680 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:50:42.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:42.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:42.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:42.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:42.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:42.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:42.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:50:42.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:50:42.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:50:42.913 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:50:42.913 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:50:42.913 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:50:42.913 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:50:42.914 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.914 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.914 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.914 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.914 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.914 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.914 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2193 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.914 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.914 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.915 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.915 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.915 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.915 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.915 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:42.915 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2194 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:47.912 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:50:47.912 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:50:47.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:50:47.915 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:50:47.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:50:47.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:50:47.924 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:50:47.926 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:50:47.926 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:47.926 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:50:47.927 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:50:47.929 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:50:47.930 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:50:47.930 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:50:47.930 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:47.931 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:50:47.931 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:50:47.931 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:50:47.932 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:50:47.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:47.932 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:50:47.932 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:50:47.932 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:50:47.932 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:47.933 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:50:47.933 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:50:47.933 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:50:47.933 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:50:47.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:47.935 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:50:47.935 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:50:47.935 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:50:47.935 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:47.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:50:47.935 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:50:47.935 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:50:47.935 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:50:47.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:47.938 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:50:47.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:50:47.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:50:47.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:50:47.938 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:50:47.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:50:47.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:50:47.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:50:47.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:50:47.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:47.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:47.938 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:50:47.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:50:47.939 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:50:47.939 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:50:47.939 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:47.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:47.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:47.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:47.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:47.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:47.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:47.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:47.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:47.944 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:50:48.427 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:50:48.470 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:50:48.473 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:50:48.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:48.475 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:50:48.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:48.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:48.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:48.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:48.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:48.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:48.505 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:48.505 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:48.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:48.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:48.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:48.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:48.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:48.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:48.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:48.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:48.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:48.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:48.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:48.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:48.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:48.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:48.616 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:48.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:48.616 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:48.616 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:48.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:48.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:48.671 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:48.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:48.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:48.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:48.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:48.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:48.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:48.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:48.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:48.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:48.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:48.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:48.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:48.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:48.872 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:48.872 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:48.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:48.904 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:50:48.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:48.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:48.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:48.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:48.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:48.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:48.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:48.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:49.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:49.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.139 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.139 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.139 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:49.139 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:49.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:49.192 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.193 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.373 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.381 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:50:49.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:49.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.391 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:49.391 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:49.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:49.435 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:49.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.459 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:49.460 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:49.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:49.472 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:50:49.472 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 02:50:49.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.475 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:50:49.482 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.482 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:49.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.483 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.483 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.483 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:49.483 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:49.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:49.523 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:50:49.523 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-05 02:50:49.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.535 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.535 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.535 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:50:49.550 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:49.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.551 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.551 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.551 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:49.551 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:49.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:49.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:49.565 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.565 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.569 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:49.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.582 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.582 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.582 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:49.582 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:49.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:49.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.626 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.657 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:49.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.658 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:49.658 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:49.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:49.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:49.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.664 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.664 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:49.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.674 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.674 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:49.674 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:49.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:49.721 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:50:49.721 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:50:49.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.735 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:50:49.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:49.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.750 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.750 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:49.750 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:49.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:49.753 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:50:49.753 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:50:49.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.767 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.767 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:50:49.778 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:49.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.779 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.779 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.779 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:49.779 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:49.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:49.805 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:50:49.805 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:50:49.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.853 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:50:49.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:49.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.921 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:50:49.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:49.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:49.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:49.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.929 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:49.929 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:49.929 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:49.929 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:49.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:49.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:49.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:49.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:49.946 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:50:49.946 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:50:49.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:49.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:49.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:50.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:50.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:50.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:50.177 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:50:50.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:50.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:50.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:50.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.196 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:50.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:50.196 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:50.196 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:50.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:50.231 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:50:50.231 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:50:50.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.328 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:50:50.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:50.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:50.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:50.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:50.443 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:50:50.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:50.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:50.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:50.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:50.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:50.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:50.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:50.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:50.538 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:50:50.538 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:50:50.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:50.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:50.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:50.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:50.689 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:50:50.707 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:50.707 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:50.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:50.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:50.709 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:50.709 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:50.709 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:50.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:50.757 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:50:50.758 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:50:50.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.804 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:50:50.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:50.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:50.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:50.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:50.943 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:50:50.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:50.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:50.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:50.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:50.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:50.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:50.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:50.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.965 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:50.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:50.965 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:50.965 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:50.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:50.987 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:50:50.987 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:50:50.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:50.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:51.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:51.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:51.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:51.197 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:51.197 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:51.197 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:50:51.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:51.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:51.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:51.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:51.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:51.209 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:51.209 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:51.209 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:51.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:51.217 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:50:51.218 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:50:51.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:51.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:51.280 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:50:51.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:51.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:51.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:51.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:51.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:51.470 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:50:51.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:51.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:51.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:51.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:51.487 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:51.487 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:51.488 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:51.488 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:51.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:51.519 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:50:51.520 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:50:51.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:51.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:51.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:51.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:51.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:51.713 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:51.713 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:51.714 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:50:51.719 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:51.719 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:51.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:51.719 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:51.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:50:51.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:50:51.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:50:51.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:50:51.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:50:51.719 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:50:51.720 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:50:51.720 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=811 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:51.720 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=811 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:51.720 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=811 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:51.720 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=811 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:51.720 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=811 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:51.720 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=811 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:51.720 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=811 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:51.720 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=811 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:56.722 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:50:56.722 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:50:56.724 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:50:56.725 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:50:56.726 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:50:56.726 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:50:56.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:50:56.742 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:50:56.742 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:56.742 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:50:56.742 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:50:56.746 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:50:56.746 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:50:56.746 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:50:56.747 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:56.747 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:50:56.747 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:50:56.748 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:50:56.748 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:50:56.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:56.749 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:50:56.749 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:50:56.749 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:50:56.749 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:56.749 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:50:56.750 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:50:56.750 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:50:56.750 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:50:56.750 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:56.751 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:50:56.751 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:50:56.751 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:50:56.751 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:50:56.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:50:56.751 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:50:56.752 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:50:56.752 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:50:56.752 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:56.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:50:56.755 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:50:56.755 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:50:56.755 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:50:56.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:56.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:56.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:50:56.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:56.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:56.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:56.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:50:56.760 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:50:57.244 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:50:57.286 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:50:57.288 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:50:57.290 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:50:57.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:57.313 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:57.314 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:57.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:50:57.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:57.319 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:57.319 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:57.320 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:50:57.320 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:50:57.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 02:50:57.345 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:50:57.346 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:50:57.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:57.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:50:57.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:50:57.722 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:50:57.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:57.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:57.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:57.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:58.200 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:50:58.678 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:50:58.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:58.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:58.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:58.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:59.155 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:50:59.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:50:59.406 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:50:59.409 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:50:59.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:50:59.409 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:50:59.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:50:59.411 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:50:59.411 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:50:59.411 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:50:59.411 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:50:59.411 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:50:59.411 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:50:59.411 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:50:59.411 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=567 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:50:59.411 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=567 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:51:04.412 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:51:04.412 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:51:04.413 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:04.416 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:04.416 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:04.416 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:04.423 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:04.423 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:51:04.423 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:04.423 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:51:04.423 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:51:04.425 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:51:04.425 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:51:04.425 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:51:04.425 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:04.425 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:04.426 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:51:04.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:51:04.426 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:51:04.426 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:04.428 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:51:04.428 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:51:04.428 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:51:04.428 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:04.428 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:04.428 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:51:04.429 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:51:04.429 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:51:04.429 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:04.431 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:51:04.431 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:51:04.431 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:51:04.431 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:04.431 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:04.431 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:51:04.432 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:51:04.432 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:51:04.432 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:51:04.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:04.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:04.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:04.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:04.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:04.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:04.437 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:51:04.437 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:51:04.437 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:51:04.437 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:51:04.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:04.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:04.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:04.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:51:04.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:04.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:04.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:04.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:04.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:04.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:04.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:04.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:04.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:04.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:04.440 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:51:04.440 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:51:04.440 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:51:09.443 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:51:09.443 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:51:09.445 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:09.446 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:09.447 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:09.447 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:09.455 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:09.457 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:51:09.457 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:09.457 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:51:09.458 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:51:09.461 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:51:09.461 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:51:09.462 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:51:09.462 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:09.462 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:09.463 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:51:09.463 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:51:09.463 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:51:09.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:09.464 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:51:09.464 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:51:09.464 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:51:09.464 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:09.464 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:09.464 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:51:09.464 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:51:09.465 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:51:09.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:09.466 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:51:09.466 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:51:09.466 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:51:09.466 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:09.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:09.467 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:51:09.467 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:51:09.467 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:51:09.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:09.469 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:51:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:51:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:51:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:51:09.469 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:51:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:51:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:51:09.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:51:09.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:51:09.470 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:51:09.470 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:51:09.470 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:09.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:09.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:09.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:09.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:09.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:09.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:09.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:09.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:09.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:09.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:09.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:09.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:09.475 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:51:09.957 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:51:09.999 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:51:10.000 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:51:10.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:51:10.001 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:51:10.426 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:51:10.473 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:10.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:10.473 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:10.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:10.895 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:51:11.370 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:51:11.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:11.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:11.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:11.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:11.842 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:51:12.317 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:51:12.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:12.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:12.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:12.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:12.798 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:51:13.279 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:51:13.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:13.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:13.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:13.481 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:13.761 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:51:14.241 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:51:14.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:14.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:14.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:14.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:14.721 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:51:15.203 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:51:15.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:15.489 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:15.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:15.489 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:15.492 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:15.492 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:15.492 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:51:15.492 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:51:15.492 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:51:15.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:15.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:15.493 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1288 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:51:15.493 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1288 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:51:15.493 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1288 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:51:15.493 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1288 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:51:15.493 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1288 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:51:15.493 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1288 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:51:15.493 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1288 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:51:20.491 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:51:20.491 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:51:20.492 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:20.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:20.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:20.494 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:20.501 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:20.501 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:51:20.501 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:20.502 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:51:20.502 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:51:20.504 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:51:20.504 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:51:20.504 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:51:20.504 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:20.505 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:20.505 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:51:20.505 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:51:20.505 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:51:20.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:20.507 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:51:20.507 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:51:20.507 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:51:20.507 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:20.507 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:20.507 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:51:20.507 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:51:20.507 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:51:20.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:20.509 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:51:20.509 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:51:20.509 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:51:20.509 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:20.509 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:20.509 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:51:20.509 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:51:20.509 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:51:20.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:51:20.512 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:51:20.512 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:51:20.512 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:51:20.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:20.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:20.517 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:51:21.001 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:51:21.042 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:51:21.045 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:51:21.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:51:21.047 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:51:21.478 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:51:21.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:21.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:21.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:21.519 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:21.946 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:51:22.416 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:51:22.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:22.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:22.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:22.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:22.894 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:51:23.372 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:51:23.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:23.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:23.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:23.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:23.852 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:51:24.333 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:51:24.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:24.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:24.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:24.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:24.814 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:51:25.293 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:51:25.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:25.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:25.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:25.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:25.771 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:51:26.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:26.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:26.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:26.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:26.057 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:26.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:26.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:26.057 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:51:26.057 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:51:26.057 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:51:26.057 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:31.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:51:31.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:51:31.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:31.064 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:31.064 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:31.064 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:31.076 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:31.077 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:51:31.077 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:31.077 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:51:31.077 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:51:31.079 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:51:31.080 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:51:31.080 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:51:31.080 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:31.080 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:31.080 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:51:31.081 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:51:31.081 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:51:31.081 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:31.082 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:51:31.082 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:51:31.082 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:51:31.082 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:31.082 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:31.082 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:51:31.082 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:51:31.082 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:51:31.082 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:31.083 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:51:31.083 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:51:31.083 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:51:31.083 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:31.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:31.083 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:51:31.083 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:51:31.083 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:51:31.083 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:51:31.085 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:51:31.085 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:51:31.085 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:31.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:31.086 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:31.087 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:51:31.087 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:51:31.087 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:51:36.090 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:51:36.090 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:51:36.094 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:36.094 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:36.094 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:36.094 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:36.096 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:36.097 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:51:36.097 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:36.097 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:51:36.097 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:51:36.097 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:51:36.097 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:51:36.098 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:51:36.098 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:36.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:36.098 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:51:36.098 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:51:36.098 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:51:36.098 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:36.099 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:51:36.099 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:51:36.099 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:51:36.099 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:36.099 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:36.099 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:51:36.099 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:51:36.099 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:51:36.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:36.100 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:51:36.100 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:51:36.100 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:51:36.100 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:36.100 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:51:36.100 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:36.100 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:51:36.100 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:51:36.100 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:36.101 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:51:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:51:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:51:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:51:36.101 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:51:36.101 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:51:36.102 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:51:36.102 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:51:36.102 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:36.102 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:36.107 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:51:36.586 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:51:36.623 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:51:36.624 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:51:36.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:51:36.625 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:51:36.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:51:36.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:51:36.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:51:37.064 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:51:37.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:37.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:37.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:37.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:37.544 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:51:37.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:51:37.628 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:51:37.629 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:51:37.629 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:51:37.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:51:38.021 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:51:38.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:38.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:38.106 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:38.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:38.493 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:51:38.964 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:51:39.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:39.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:39.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:39.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:39.434 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:51:39.905 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:51:40.107 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:40.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:40.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:40.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:40.376 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:51:40.847 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:51:41.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:41.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:41.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:41.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:41.321 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:51:41.799 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:51:42.276 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:51:42.751 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:51:43.225 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:51:43.702 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:51:44.181 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:51:44.659 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:51:45.137 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:51:45.609 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:51:46.080 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:51:46.552 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:51:47.030 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:51:47.508 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:51:47.985 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:51:48.462 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:51:48.940 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:51:49.418 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:51:49.896 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:51:50.374 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:51:50.851 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:51:51.329 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:51:51.420 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:51:51.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:51:51.427 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:51.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:51.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:51.428 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:51.429 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:51.429 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:51.429 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:51.429 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:51:51.429 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:51:51.429 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:51:51.429 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:56.430 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:51:56.431 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:51:56.432 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:56.433 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:56.434 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:56.435 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:56.443 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:51:56.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:51:56.445 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:56.445 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:51:56.445 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:51:56.448 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:51:56.448 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:51:56.449 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:51:56.449 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:56.449 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:51:56.449 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:51:56.450 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:51:56.450 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:51:56.450 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:56.451 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:51:56.451 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:51:56.451 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:51:56.451 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:56.452 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:51:56.452 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:51:56.452 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:51:56.452 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:51:56.452 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:56.453 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:51:56.453 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:51:56.454 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:51:56.454 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:51:56.454 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:51:56.454 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:51:56.454 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:51:56.454 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:51:56.454 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:56.456 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:51:56.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:51:56.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:51:56.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:51:56.456 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:51:56.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:51:56.457 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:51:56.457 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:51:56.457 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:56.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:56.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:51:56.462 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:51:56.945 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:51:56.980 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:51:56.981 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:51:56.982 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:51:56.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:51:57.004 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:51:57.004 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:51:57.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:51:57.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:51:57.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:51:57.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:51:57.010 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:51:57.010 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:51:57.037 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:51:57.040 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:51:57.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:51:57.057 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:51:57.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:51:57.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:51:57.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:51:57.422 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:51:57.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:57.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:57.464 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:57.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:57.900 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:51:58.378 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:51:58.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:58.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:58.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:58.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:58.857 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:51:59.335 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:51:59.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:51:59.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:51:59.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:51:59.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:51:59.813 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:52:00.291 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:52:00.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:00.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:00.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:00.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:00.769 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:52:01.246 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:52:01.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:01.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:01.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:01.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:01.724 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:52:02.202 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:52:02.681 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:52:03.159 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:52:03.638 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:52:04.115 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:52:04.593 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:52:05.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:05.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:05.063 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:05.063 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:05.071 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:52:05.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:05.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:05.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:05.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:05.074 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:05.074 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:05.075 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:05.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:05.075 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:52:05.075 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:52:05.075 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:52:05.075 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:05.075 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:05.075 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:10.076 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:52:10.076 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:52:10.077 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:10.079 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:10.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:10.080 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:10.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:10.086 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:52:10.086 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:10.086 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:52:10.086 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:52:10.089 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:52:10.089 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:52:10.089 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:52:10.089 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:10.089 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:10.089 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:52:10.089 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:52:10.089 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:52:10.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:10.092 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:52:10.092 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:52:10.092 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:52:10.092 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:10.092 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:10.092 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:52:10.092 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:52:10.092 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:52:10.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:10.094 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:52:10.094 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:52:10.094 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:52:10.094 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:10.094 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:10.094 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:52:10.095 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:52:10.095 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:52:10.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:10.097 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:52:10.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:52:10.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:52:10.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:52:10.097 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:52:10.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:52:10.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:52:10.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:52:10.098 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:52:10.098 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:52:10.098 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:10.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:10.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:10.103 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:52:10.588 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:52:10.629 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:52:10.632 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:52:10.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:10.634 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:52:10.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:10.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:10.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:52:10.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:10.667 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:52:10.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:52:10.667 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:52:10.667 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:52:10.692 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:52:10.696 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:52:10.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:10.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:52:10.713 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:52:10.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:10.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:11.065 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:52:11.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:11.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:11.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:11.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:11.542 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:52:12.020 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:52:12.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:12.102 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:12.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:12.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:12.498 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:52:12.976 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:52:13.102 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:13.102 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:13.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:13.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:13.453 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:52:13.931 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:52:14.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:14.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:14.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:14.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:14.408 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:52:14.886 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:52:15.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:15.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:15.106 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:15.110 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:15.364 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:52:15.842 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:52:16.320 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:52:16.798 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:52:17.276 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:52:17.754 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:52:18.232 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:52:18.709 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:52:18.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:18.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:18.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:18.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:18.729 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:18.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:18.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:18.730 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:18.733 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:18.733 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:18.733 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:18.733 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:18.733 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:52:18.733 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:52:18.733 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:52:18.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:18.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:18.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:18.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:18.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:18.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:18.733 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:23.732 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:52:23.732 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:52:23.734 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:23.735 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:23.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:23.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:23.743 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:23.744 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:52:23.744 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:23.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:52:23.745 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:52:23.747 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:52:23.747 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:52:23.748 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:52:23.748 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:23.748 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:23.748 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:52:23.749 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:52:23.749 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:52:23.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:23.750 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:52:23.750 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:52:23.750 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:52:23.750 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:23.750 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:23.750 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:52:23.751 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:52:23.751 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:52:23.751 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:23.752 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:52:23.752 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:52:23.752 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:52:23.752 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:23.752 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:23.752 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:52:23.752 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:52:23.752 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:52:23.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:23.755 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:52:23.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:52:23.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:52:23.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:52:23.755 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:52:23.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:52:23.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:52:23.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:52:23.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:52:23.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:23.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:23.755 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:52:23.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:52:23.756 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:52:23.756 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:52:23.756 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:23.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:23.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:23.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:23.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:23.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:23.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:23.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:23.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:23.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:23.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:23.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:23.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:23.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:23.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:23.761 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:52:24.244 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:52:24.286 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:52:24.288 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:52:24.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:24.290 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:52:24.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:24.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:24.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:52:24.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:24.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:52:24.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:52:24.322 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:52:24.322 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:52:24.335 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:52:24.338 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:52:24.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:24.351 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:52:24.351 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:52:24.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:24.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:24.720 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:52:24.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:24.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:24.761 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:24.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:24.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:24.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:24.914 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:52:24.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:24.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:24.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:24.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:24.922 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:24.922 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:24.922 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:24.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:24.922 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:52:24.922 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:52:24.922 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=248 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=248 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=248 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=248 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=248 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=248 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:24.922 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:29.921 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:52:29.921 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:52:29.922 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:29.924 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:29.924 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:29.924 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:29.929 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:29.930 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:52:29.931 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:29.931 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:52:29.931 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:52:29.934 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:52:29.934 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:52:29.934 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:52:29.935 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:29.935 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:29.936 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:52:29.936 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:52:29.936 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:52:29.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:29.937 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:52:29.937 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:52:29.937 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:52:29.938 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:29.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:29.938 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:52:29.938 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:52:29.938 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:52:29.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:29.940 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:52:29.940 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:52:29.940 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:52:29.940 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:29.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:29.941 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:52:29.941 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:52:29.941 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:52:29.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:29.944 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:52:29.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:52:29.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:52:29.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:52:29.944 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:52:29.944 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:52:29.944 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:52:29.944 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:52:29.945 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:52:29.945 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:52:29.945 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:29.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:29.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:29.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:29.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:29.950 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:52:30.432 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:52:30.478 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:52:30.480 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:52:30.482 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:52:30.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:30.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:30.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:30.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:52:30.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:30.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:52:30.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:52:30.505 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:52:30.505 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:52:30.525 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:52:30.528 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:52:30.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:30.535 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:52:30.535 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:52:30.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:30.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:30.910 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:52:30.949 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:30.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:30.949 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:30.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:31.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:31.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:31.103 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:52:31.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:31.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:31.106 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:31.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:31.110 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:31.110 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:31.110 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:31.110 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:31.111 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:52:31.111 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:52:31.111 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:52:31.111 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=248 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:31.111 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=248 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:31.111 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=248 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:31.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=248 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:31.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=248 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:31.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=248 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:31.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:31.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:31.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:31.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:31.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:31.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:31.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:31.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:36.110 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:52:36.110 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:52:36.111 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:36.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:36.114 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:36.114 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:36.123 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:36.125 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:52:36.125 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:36.126 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:52:36.126 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:52:36.129 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:52:36.130 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:52:36.130 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:52:36.130 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:36.130 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:36.131 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:52:36.131 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:52:36.131 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:52:36.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:36.132 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:52:36.132 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:52:36.132 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:52:36.132 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:36.133 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:36.133 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:52:36.133 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:52:36.133 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:52:36.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:36.135 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:52:36.135 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:52:36.135 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:52:36.135 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:36.135 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:36.135 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:52:36.135 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:52:36.135 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:52:36.135 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:36.137 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:52:36.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:52:36.138 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:52:36.138 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:52:36.138 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:36.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:36.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:36.143 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:52:36.628 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:52:36.663 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:52:36.664 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:52:36.665 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:52:36.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:36.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:36.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:36.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:52:36.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:36.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:52:36.692 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:52:36.692 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:52:36.692 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:52:36.720 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:52:36.723 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:52:36.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:36.737 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:52:36.737 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:52:36.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:36.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:37.105 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:52:37.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:37.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:37.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:37.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:37.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:37.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:37.302 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:52:37.305 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:37.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:37.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:37.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:37.309 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:37.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:37.309 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:37.309 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:52:37.309 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:52:37.309 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:52:37.310 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:37.310 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.310 [WARNING] transceiver.py:257 (TRX3@172.18.201.20:5700/3) RX TRXD message (ver=1 fn=249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.310 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.310 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.310 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.310 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.310 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=250 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=250 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=250 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=250 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=250 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=250 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=250 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:37.311 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=250 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:42.308 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:52:42.309 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:52:42.310 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:42.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:42.313 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:42.316 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:42.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:42.324 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:52:42.324 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:42.324 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:52:42.324 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:52:42.325 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:52:42.326 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:52:42.326 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:52:42.326 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:42.326 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:42.326 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:52:42.327 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:52:42.327 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:52:42.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:42.327 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:52:42.327 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:52:42.327 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:52:42.327 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:42.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:42.328 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:52:42.328 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:52:42.328 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:52:42.328 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:42.329 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:52:42.329 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:52:42.329 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:52:42.329 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:42.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:42.329 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:52:42.329 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:52:42.329 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:52:42.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:52:42.331 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:52:42.331 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:52:42.331 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:42.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:42.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:42.336 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:52:42.820 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:52:42.854 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:52:42.856 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:52:42.858 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:52:42.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:42.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:42.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:42.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:52:42.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:42.877 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:52:42.877 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:52:42.877 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:52:42.877 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:52:42.913 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:52:42.917 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:52:42.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:42.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:52:42.926 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:52:42.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:42.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:43.297 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:52:43.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:43.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:43.334 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:43.337 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:43.775 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:52:44.253 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:52:44.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:44.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:44.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:44.338 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:44.731 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:52:45.209 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:52:45.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:45.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:45.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:45.339 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:45.687 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:52:46.165 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:52:46.336 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:46.336 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:46.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:46.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:46.643 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:52:47.121 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:52:47.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:47.337 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:47.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:47.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:47.599 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:52:48.076 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:52:48.555 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:52:49.027 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:52:49.501 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:52:49.979 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:52:50.457 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:52:50.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:50.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:50.931 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:50.931 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:50.935 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:52:50.950 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:50.950 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:50.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:52:50.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:50.952 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:52:50.952 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:52:50.952 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:52:50.952 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:52:50.981 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:52:50.986 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:52:50.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:50.994 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:52:50.994 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 02:52:50.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:50.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:51.413 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:52:51.891 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:52:52.128 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:52.128 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:52.129 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:52:52.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:52.134 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:52.134 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:52.134 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:52.138 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:52.138 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:52.138 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:52.138 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:52.138 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:52:52.138 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:52:52.138 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:52:52.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2094 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:52.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2094 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:52.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2094 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:52.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2094 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:52.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2094 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:52.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2094 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:52.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2095 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:52.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2095 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:52.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2095 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:52.140 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2095 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:52.140 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2095 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:52.140 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2095 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:52.140 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2095 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:52.140 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2095 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:52:57.137 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:52:57.138 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:52:57.139 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:57.141 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:57.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:57.142 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:57.148 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:57.149 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:52:57.149 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:57.150 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:52:57.150 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:52:57.152 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:52:57.152 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:52:57.153 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:52:57.153 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:57.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:57.154 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:52:57.154 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:52:57.154 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:52:57.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:57.155 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:52:57.155 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:52:57.155 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:52:57.155 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:57.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:57.156 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:52:57.156 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:52:57.156 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:52:57.156 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:57.157 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:52:57.157 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:52:57.157 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:52:57.157 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:52:57.158 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:52:57.158 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:52:57.158 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:52:57.158 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:52:57.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:57.160 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:52:57.160 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:52:57.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:52:57.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:52:57.160 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:52:57.161 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:52:57.161 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:52:57.161 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:57.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:52:57.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:57.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:57.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:52:57.166 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:52:57.646 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:52:57.689 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:52:57.689 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:52:57.690 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:52:57.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:57.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:57.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:57.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:52:57.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:57.715 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:52:57.715 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:52:57.715 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:52:57.715 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:52:57.738 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:52:57.742 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:52:57.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:52:57.756 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:52:57.756 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:52:57.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:57.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:52:58.124 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:52:58.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:58.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:58.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:58.169 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:58.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:52:58.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:52:58.318 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:52:58.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:52:58.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:52:58.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:52:58.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:52:58.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:52:58.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:52:58.323 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:52:58.323 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:52:58.323 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:52:58.323 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:52:58.323 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:53:03.330 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:53:03.331 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:53:03.331 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:53:03.331 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:53:03.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:53:03.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:53:03.339 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:53:03.341 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:53:03.342 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:03.342 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:53:03.343 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:53:03.346 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:53:03.347 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:53:03.347 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:53:03.347 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:03.347 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:53:03.347 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:53:03.347 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:53:03.347 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:53:03.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:03.350 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:53:03.350 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:53:03.351 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:53:03.351 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:03.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:53:03.352 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:53:03.352 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:53:03.352 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:53:03.352 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:03.353 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:53:03.353 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:53:03.353 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:53:03.353 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:03.353 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:53:03.353 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:53:03.353 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:53:03.353 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:53:03.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:03.356 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:53:03.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:53:03.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:53:03.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:53:03.356 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:53:03.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:53:03.357 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:53:03.357 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:53:03.357 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:53:03.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:03.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:03.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:03.362 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:53:03.846 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:53:03.893 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:53:03.895 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:53:03.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:03.898 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:53:03.926 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:53:03.926 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:53:03.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:53:03.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:03.933 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:53:03.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:53:03.935 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:53:03.935 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:53:03.939 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:53:03.942 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:53:03.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:03.952 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:53:03.952 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:53:03.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:03.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:04.324 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:53:04.361 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:04.362 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:04.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:04.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:04.802 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:53:05.280 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:53:05.362 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:05.362 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:05.366 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:05.369 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:05.758 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:53:06.236 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:53:06.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:06.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:06.366 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:06.370 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:06.713 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:53:07.190 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:53:07.364 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:07.364 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:07.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:07.371 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:07.668 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:53:08.146 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:53:08.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:08.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:08.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:08.372 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:08.624 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:53:09.101 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:53:09.579 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:53:10.058 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:53:10.536 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:53:11.014 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:53:11.491 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:53:11.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:11.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:11.958 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:53:11.958 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:53:11.969 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:53:11.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:53:11.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:53:11.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:53:11.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:11.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:53:11.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:53:11.983 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:53:11.983 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:53:12.015 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:53:12.020 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:53:12.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:12.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:53:12.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:53:12.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:12.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:12.446 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:53:12.924 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:53:13.402 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:53:13.879 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:53:14.357 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:53:14.835 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:53:15.313 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:53:15.791 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:53:16.269 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:53:16.747 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:53:17.225 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:53:17.702 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:53:18.179 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:53:18.657 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:53:19.132 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:53:19.610 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:53:20.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:20.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:20.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:53:20.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:53:20.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:53:20.056 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:53:20.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:53:20.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:20.059 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:53:20.059 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:53:20.059 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:53:20.059 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:53:20.079 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:53:20.083 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:53:20.087 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:53:20.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:20.094 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:53:20.094 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:53:20.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:20.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:20.564 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:53:21.042 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:53:21.519 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:53:21.998 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:53:22.475 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:53:22.953 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:53:23.430 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:53:23.908 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:53:24.386 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:53:24.864 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:53:25.341 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:53:25.819 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:53:26.297 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:53:26.774 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:53:27.252 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:53:27.730 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:53:28.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:28.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:28.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:53:28.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:53:28.100 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=5284 tn=2 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:28.110 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:53:28.110 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:53:28.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:53:28.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:28.112 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:53:28.112 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:53:28.112 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:53:28.112 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:53:28.150 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:53:28.152 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:53:28.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:28.155 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:53:28.155 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:53:28.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:28.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:28.207 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:53:28.685 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:53:29.163 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:53:29.640 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:53:30.118 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:53:30.595 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:53:31.073 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:53:31.550 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:53:32.028 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:53:32.506 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:53:32.984 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 02:53:33.462 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 02:53:33.939 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 02:53:34.417 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 02:53:34.895 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 02:53:35.372 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 02:53:35.850 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 02:53:36.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:36.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:36.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:53:36.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:53:36.172 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:36.173 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:36.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:36.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:36.176 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:53:36.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:53:36.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:53:36.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:53:36.177 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:53:36.177 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:53:36.177 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:53:36.177 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7008 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:36.177 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7008 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:36.178 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7008 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:36.178 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7008 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:36.178 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7008 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:36.178 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7008 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:41.175 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:53:41.175 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:53:41.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:53:41.179 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:53:41.179 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:53:41.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:53:41.188 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:53:41.190 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:53:41.190 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:41.190 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:53:41.191 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:53:41.195 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:53:41.195 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:53:41.196 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:53:41.196 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:41.196 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:53:41.196 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:53:41.196 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:53:41.196 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:53:41.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:41.199 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:53:41.199 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:53:41.200 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:53:41.200 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:41.200 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:53:41.200 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:53:41.200 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:53:41.200 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:53:41.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:41.203 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:53:41.203 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:53:41.203 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:53:41.203 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:41.203 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:53:41.203 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:53:41.203 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:53:41.203 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:53:41.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:41.206 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:53:41.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:53:41.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:53:41.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:41.207 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:53:41.207 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:53:41.207 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:53:41.208 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:41.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:41.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:41.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:41.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:41.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:41.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:41.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:41.212 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:53:41.696 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:53:41.735 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:53:41.737 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:53:41.739 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:53:41.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:41.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:53:41.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:53:41.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:53:41.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:41.768 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:53:41.768 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:53:41.768 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:53:41.768 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:53:41.787 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:53:41.791 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:53:41.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:41.802 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:53:41.802 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:53:41.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:41.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:42.172 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:53:42.210 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:42.211 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:42.212 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:42.217 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:42.651 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:53:43.129 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:53:43.212 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:43.212 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:43.214 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:43.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:43.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:53:43.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:53:43.359 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:53:43.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:43.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:43.363 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:43.363 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:43.364 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:53:43.364 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:53:43.364 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:53:43.365 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:53:43.365 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:53:43.365 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:53:43.365 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:53:43.365 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=461 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:43.365 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=461 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:43.365 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=461 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:43.365 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=461 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:43.365 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=461 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:43.365 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=461 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:43.365 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=461 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:43.365 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=461 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:48.366 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:53:48.366 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:53:48.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:53:48.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:53:48.369 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:53:48.370 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:53:48.378 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:53:48.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:53:48.379 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:48.380 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:53:48.380 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:53:48.383 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:53:48.383 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:53:48.383 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:53:48.383 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:48.383 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:53:48.383 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:53:48.384 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:53:48.384 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:53:48.384 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:48.388 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:53:48.388 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:53:48.388 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:53:48.388 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:48.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:53:48.388 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:53:48.389 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:53:48.389 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:53:48.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:48.391 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:53:48.391 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:53:48.391 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:53:48.391 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:48.392 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:53:48.392 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:53:48.392 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:53:48.392 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:53:48.392 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:48.395 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:53:48.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:48.396 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:53:48.396 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:53:48.396 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:53:48.397 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:48.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:48.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:48.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:48.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:48.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:48.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:48.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:48.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:48.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:48.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:48.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:48.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:48.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:48.401 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:53:48.884 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:53:48.923 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:53:48.924 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:53:48.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:48.927 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:53:48.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:53:48.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:53:48.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:53:48.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:48.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:53:48.944 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:53:48.944 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:53:48.944 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:53:48.974 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:53:48.976 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:53:48.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:48.988 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:53:48.989 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:53:48.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:48.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:49.362 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:53:49.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:49.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:49.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:49.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:49.556 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:53:49.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:53:49.557 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:53:49.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:49.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:49.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:49.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:49.562 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:53:49.562 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:53:49.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:53:49.562 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:53:49.562 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:53:49.562 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:53:49.562 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:53:49.562 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:49.562 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:49.562 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:49.562 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:49.562 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:49.562 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=249 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:53:54.564 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:53:54.564 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:53:54.566 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:53:54.567 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:53:54.569 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:53:54.571 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:53:54.582 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:53:54.582 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:53:54.583 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:54.583 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:53:54.583 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:53:54.585 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:53:54.585 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:53:54.585 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:53:54.585 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:54.586 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:53:54.586 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:53:54.586 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:53:54.586 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:53:54.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:54.587 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:53:54.587 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:53:54.587 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:53:54.587 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:54.587 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:53:54.587 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:53:54.587 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:53:54.587 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:53:54.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:54.588 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:53:54.588 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:53:54.589 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:53:54.589 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:53:54.589 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:53:54.589 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:53:54.589 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:53:54.589 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:53:54.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:53:54.591 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:53:54.591 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:53:54.591 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:54.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:54.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:53:54.596 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:53:55.078 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:53:55.114 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:53:55.116 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:53:55.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:55.118 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:53:55.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:53:55.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:53:55.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:53:55.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:55.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:53:55.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:53:55.137 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:53:55.137 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:53:55.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:53:55.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:53:55.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:53:55.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:55.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:53:55.556 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:53:55.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:55.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:55.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:55.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:56.034 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:53:56.511 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:53:56.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:56.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:56.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:56.597 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:56.990 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:53:57.464 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:53:57.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:57.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:57.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:57.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:57.939 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:53:58.417 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:53:58.595 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:58.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:58.597 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:58.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:58.894 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:53:59.372 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:53:59.595 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:53:59.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:53:59.598 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:53:59.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:53:59.850 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:54:00.328 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:54:00.806 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:54:01.284 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:54:01.762 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:54:02.240 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:54:02.718 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:54:03.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:54:03.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:54:03.191 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:54:03.191 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:54:03.196 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:54:03.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:03.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:03.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:03.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:03.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:03.211 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:03.211 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:03.211 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:03.212 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:54:03.212 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:54:03.212 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:54:03.212 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1841 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:03.212 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1841 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:03.212 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1841 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:03.212 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1841 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:03.213 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1841 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:03.213 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1841 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:08.213 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:54:08.213 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:54:08.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:08.214 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:08.214 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:08.214 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:08.223 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:08.225 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:54:08.225 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:08.225 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:54:08.225 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:54:08.229 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:54:08.229 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:54:08.229 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:54:08.229 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:08.230 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:08.230 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:54:08.231 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:54:08.231 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:54:08.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:08.232 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:54:08.232 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:54:08.232 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:54:08.232 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:08.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:08.233 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:54:08.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:54:08.233 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:54:08.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:08.234 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:54:08.235 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:54:08.235 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:54:08.235 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:08.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:08.235 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:54:08.235 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:54:08.235 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:54:08.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:08.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:54:08.239 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:54:08.239 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:54:08.239 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:08.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:08.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:08.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:08.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:08.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:08.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:08.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:08.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:08.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:08.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:08.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:08.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:08.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:08.244 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:54:08.726 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:54:08.759 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:54:08.761 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:54:08.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:54:08.762 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:54:08.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:54:08.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:54:08.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:54:08.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:54:08.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:54:08.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:54:08.778 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:54:08.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:54:08.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:54:08.831 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:54:08.832 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:54:08.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:54:08.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:54:09.204 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:54:09.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:09.242 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:09.243 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:09.246 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:09.682 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:54:10.160 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:54:10.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:10.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:10.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:10.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:10.639 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:54:11.117 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:54:11.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:11.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:11.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:11.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:11.595 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:54:12.073 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:54:12.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:12.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:12.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:12.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:12.552 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:54:13.031 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:54:13.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:13.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:13.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:13.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:13.509 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:54:13.988 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:54:14.467 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:54:14.945 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:54:15.424 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:54:15.903 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:54:16.380 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:54:16.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:54:16.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:54:16.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:54:16.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:54:16.841 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:54:16.856 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:16.856 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:16.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:16.857 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:16.859 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:54:16.860 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:16.860 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:16.860 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:16.860 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:54:16.860 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:54:16.860 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:54:16.860 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:16.860 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:16.860 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:16.860 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:16.860 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:16.860 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:16.860 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:16.860 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:16.860 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:21.860 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:54:21.860 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:54:21.862 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:21.864 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:21.864 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:21.864 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:21.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:21.872 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:54:21.873 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:21.873 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:54:21.873 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:54:21.876 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:54:21.876 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:54:21.876 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:54:21.877 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:21.877 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:21.877 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:54:21.878 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:54:21.878 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:54:21.878 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:21.879 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:54:21.879 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:54:21.879 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:54:21.879 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:21.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:21.879 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:54:21.879 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:54:21.879 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:54:21.879 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:21.883 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:54:21.883 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:54:21.883 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:54:21.883 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:21.883 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:21.883 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:54:21.883 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:54:21.883 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:54:21.883 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:21.886 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:54:21.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:54:21.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:54:21.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:54:21.886 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:21.887 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:54:21.887 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:54:21.887 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:54:21.887 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:21.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:21.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:21.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:21.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:21.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:21.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:21.892 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:54:22.375 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:54:22.420 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:54:22.421 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:54:22.422 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:54:22.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:54:22.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:54:22.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:54:22.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:54:22.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:54:22.442 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:54:22.442 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:54:22.442 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:54:22.442 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:54:22.851 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:54:22.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:22.891 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:22.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:22.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:23.330 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:54:23.807 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:54:23.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:23.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:23.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:23.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:24.284 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:54:24.762 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:54:24.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:24.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:24.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:24.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:25.239 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:54:25.717 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:54:25.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:25.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:25.897 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:25.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:26.195 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:54:26.673 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:54:26.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:26.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:26.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:26.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:27.150 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:54:27.628 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:54:28.106 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:54:28.584 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:54:28.925 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:54:28.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:54:28.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:28.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:28.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:28.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:28.937 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:28.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:28.937 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:28.937 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:28.937 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:54:28.937 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:54:28.937 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:54:33.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:54:33.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:54:33.941 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:33.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:33.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:33.941 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:33.950 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:33.951 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:54:33.951 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:33.951 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:54:33.951 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:54:33.955 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:54:33.955 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:54:33.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:54:33.955 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:33.955 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:33.955 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:54:33.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:54:33.955 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:54:33.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:33.958 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:54:33.958 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:54:33.958 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:54:33.958 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:33.958 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:33.959 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:54:33.959 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:54:33.959 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:54:33.959 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:33.961 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:54:33.961 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:54:33.961 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:54:33.961 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:33.961 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:33.961 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:54:33.961 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:54:33.961 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:54:33.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:33.964 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:54:33.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:54:33.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:54:33.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:54:33.964 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:54:33.965 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:54:33.965 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:54:33.965 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:54:33.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:33.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:33.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:33.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:33.970 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:54:34.452 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:54:34.502 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:54:34.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:54:34.504 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:54:34.506 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:54:34.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:54:34.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:54:34.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:54:34.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:54:34.536 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:54:34.536 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:54:34.536 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:54:34.536 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:54:34.930 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:54:34.968 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:34.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:34.970 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:34.975 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:35.407 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:54:35.885 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:54:35.968 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:35.969 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:35.971 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:35.976 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:36.362 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:54:36.840 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:54:36.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:36.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:36.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:36.977 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:37.317 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:54:37.795 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:54:37.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:37.971 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:37.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:37.979 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:38.273 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:54:38.750 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:54:38.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:38.972 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:38.975 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:38.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:39.009 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:39.009 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:39.009 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:39.009 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:39.009 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:39.009 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:39.009 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:39.009 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:54:39.009 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:54:39.009 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:39.009 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1078 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:39.010 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1078 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:39.010 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1078 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:39.010 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1078 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:39.010 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1078 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:39.010 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1078 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:39.010 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1078 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:54:39.231 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:54:39.717 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:54:40.202 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:54:40.687 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:54:41.173 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:54:41.659 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:54:42.144 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:54:42.631 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:54:43.117 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:54:43.603 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:54:44.012 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:54:44.012 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:54:44.013 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:44.014 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:54:44.014 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:54:44.014 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:54:44.015 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:44.016 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:44.017 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:44.020 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:44.020 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:54:44.020 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:44.020 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:54:44.020 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:54:44.021 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:54:44.021 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:54:44.021 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:54:44.021 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:44.021 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:44.021 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:54:44.021 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:54:44.021 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:54:44.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:44.022 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:54:44.022 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:54:44.022 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:54:44.022 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:44.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:44.023 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:54:44.023 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:54:44.023 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:54:44.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:44.024 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:54:44.024 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:54:44.024 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:54:44.024 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:44.024 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:44.024 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:54:44.024 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:54:44.024 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:54:44.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:44.026 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:54:44.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:54:44.027 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:54:44.027 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:54:44.027 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:44.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:44.028 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:44.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:44.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:44.028 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:54:44.028 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:54:44.028 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:54:44.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:44.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:44.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:44.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:44.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:49.031 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:54:49.031 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:54:49.033 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:49.034 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:49.035 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:49.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:49.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:49.044 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:54:49.045 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:49.045 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:54:49.045 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:54:49.048 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:54:49.049 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:54:49.049 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:54:49.049 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:49.050 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:54:49.050 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:54:49.050 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:54:49.051 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:54:49.051 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:49.051 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:54:49.051 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:54:49.051 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:54:49.051 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:49.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:54:49.052 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:54:49.052 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:54:49.052 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:54:49.052 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:49.054 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:54:49.054 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:54:49.054 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:54:49.054 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:54:49.054 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:54:49.054 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:54:49.054 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:54:49.054 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:54:49.054 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:49.056 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:54:49.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:54:49.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:54:49.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:54:49.057 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:54:49.057 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:54:49.057 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:49.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:49.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:54:49.062 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:54:49.546 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:54:49.586 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:54:49.588 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:54:49.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:54:49.591 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:54:49.616 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:54:49.616 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:54:49.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:54:49.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:54:49.624 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:54:49.624 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:54:49.624 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:54:49.624 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:54:50.024 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:54:50.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:50.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:50.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:50.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:50.501 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:54:50.978 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:54:51.061 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:51.062 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:51.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:51.066 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:51.456 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:54:51.934 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:54:52.063 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:52.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:52.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:52.067 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:52.411 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:54:52.889 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:54:53.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:53.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:53.065 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:53.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:53.367 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:54:53.844 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:54:54.065 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:54.066 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:54:54.066 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:54:54.069 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:54:54.312 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:54:54.782 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:54:55.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:55.251 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:54:55.726 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:54:56.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:56.199 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:54:56.674 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:54:57.095 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:57.150 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:54:57.626 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:54:58.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:58.100 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:54:58.576 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:54:59.048 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:54:59.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:54:59.098 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:54:59.523 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:55:00.000 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:55:00.475 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:55:00.952 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:55:01.422 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:55:01.890 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:55:02.358 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:55:02.827 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:55:03.096 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:55:03.295 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:55:03.769 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:55:04.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:04.243 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:55:04.717 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:55:05.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:05.189 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:55:05.663 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:55:06.098 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:06.135 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:55:06.611 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:55:07.086 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:55:07.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:07.559 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:55:08.033 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:55:08.100 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:08.505 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:55:08.981 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:55:09.457 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:55:09.933 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:55:10.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:55:10.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:55:10.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:10.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:55:10.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:55:10.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:55:10.283 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:55:10.283 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:55:10.283 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:55:10.283 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:55:10.283 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:55:10.283 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:55:10.283 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:55:15.285 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:55:15.286 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:55:15.287 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:55:15.289 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:55:15.290 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:55:15.293 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:55:15.300 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:55:15.301 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:55:15.301 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:55:15.301 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:55:15.301 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:55:15.303 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:55:15.304 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:55:15.304 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:55:15.304 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:55:15.304 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:55:15.305 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:55:15.305 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:55:15.305 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:55:15.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:55:15.306 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:55:15.306 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:55:15.306 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:55:15.306 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:55:15.307 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:55:15.307 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:55:15.307 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:55:15.307 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:55:15.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:55:15.308 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:55:15.308 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:55:15.308 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:55:15.308 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:55:15.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:55:15.308 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:55:15.308 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:55:15.308 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:55:15.308 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:55:15.310 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:55:15.311 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:55:15.311 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:55:15.311 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:15.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:15.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:15.316 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:55:15.795 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:55:15.834 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:55:15.835 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:55:15.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:55:15.836 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:55:15.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:55:15.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:55:15.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:55:15.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:15.858 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:55:15.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:55:15.858 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:55:15.858 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:55:15.887 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:55:15.890 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:55:15.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:55:15.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:55:15.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:55:15.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:15.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:16.270 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:55:16.314 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:55:16.314 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:16.314 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:55:16.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:55:16.742 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:55:17.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:55:17.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:17.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:55:17.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:55:17.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:17.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:55:17.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:55:17.198 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:55:17.201 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:55:17.202 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:55:17.202 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:55:17.202 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:55:17.202 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:55:17.202 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:55:17.202 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:17.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:22.201 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:55:22.201 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:55:22.203 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:55:22.204 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:55:22.205 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:55:22.205 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:55:22.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:55:22.215 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:55:22.215 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:55:22.216 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:55:22.216 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:55:22.219 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:55:22.220 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:55:22.220 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:55:22.220 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:55:22.221 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:55:22.221 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:55:22.221 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:55:22.221 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:55:22.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:55:22.222 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:55:22.223 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:55:22.223 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:55:22.223 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:55:22.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:55:22.223 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:55:22.223 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:55:22.223 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:55:22.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:55:22.225 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:55:22.225 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:55:22.225 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:55:22.225 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:55:22.225 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:55:22.225 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:55:22.225 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:55:22.226 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:55:22.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:55:22.228 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:55:22.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:55:22.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:55:22.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:55:22.228 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:55:22.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:55:22.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:55:22.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:55:22.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:55:22.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:55:22.229 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:55:22.229 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:55:22.229 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:22.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:22.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:22.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:22.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:22.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:22.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:22.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:22.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:22.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:22.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:22.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:22.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:22.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:22.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:22.234 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:55:22.718 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:55:22.755 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:55:22.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:55:22.758 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:55:22.759 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:55:22.780 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:55:22.780 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:55:22.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:55:22.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:22.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:55:22.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:55:22.785 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:55:22.785 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:55:22.811 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:55:22.815 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:55:22.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:55:22.822 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:55:22.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:55:22.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:22.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:23.196 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:55:23.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:23.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:55:23.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:55:23.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:55:23.674 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:55:24.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 02:55:24.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:24.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:55:24.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:55:24.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:24.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:55:24.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:55:24.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:55:24.133 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:55:24.133 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:55:24.133 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:55:24.133 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:55:24.134 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:55:24.134 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:55:24.134 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:55:24.134 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:24.134 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:24.134 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:24.134 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:24.134 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:24.134 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=407 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:55:29.135 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:55:29.135 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:55:29.135 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:55:29.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:55:29.135 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:55:29.135 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:55:29.144 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:55:29.146 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:55:29.146 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:55:29.147 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:55:29.147 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:55:29.151 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:55:29.151 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:55:29.152 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:55:29.152 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:55:29.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:55:29.153 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:55:29.153 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:55:29.153 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:55:29.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:55:29.154 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:55:29.155 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:55:29.155 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:55:29.155 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:55:29.155 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:55:29.155 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:55:29.155 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:55:29.155 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:55:29.156 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:55:29.157 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:55:29.158 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:55:29.158 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:55:29.158 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:55:29.158 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:55:29.158 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:55:29.158 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:55:29.158 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:55:29.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:55:29.161 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:55:29.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:55:29.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:55:29.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:55:29.161 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:55:29.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:55:29.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:55:29.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:55:29.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:55:29.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:55:29.162 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:55:29.162 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:55:29.162 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:55:29.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:29.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:55:29.167 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:55:29.652 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:55:29.693 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:55:29.695 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:55:29.697 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:55:29.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:55:29.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:55:29.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:55:29.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:55:29.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:29.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:55:29.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:55:29.721 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:55:29.721 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:55:29.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:55:29.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:55:29.754 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:55:29.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:29.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:30.129 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:55:30.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:55:30.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:55:30.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:30.167 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:55:30.607 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:55:31.085 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:55:31.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:55:31.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:55:31.167 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:31.168 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:55:31.563 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:55:32.040 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:55:32.167 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:55:32.167 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:32.167 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:55:32.169 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:55:32.518 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:55:32.996 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:55:33.168 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:33.168 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:55:33.168 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:55:33.169 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:55:33.474 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:55:33.952 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:55:34.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:55:34.169 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:55:34.169 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:55:34.170 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:55:34.430 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:55:34.908 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:55:35.386 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:55:35.864 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:55:36.342 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:55:36.820 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:55:37.298 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:55:37.776 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:55:38.254 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:55:38.731 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:55:39.209 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:55:39.687 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:55:40.165 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:55:40.642 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:55:41.120 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:55:41.598 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:55:42.075 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:55:42.553 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:55:43.031 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:55:43.509 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:55:43.987 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:55:44.465 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:55:44.943 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:55:45.420 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:55:45.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:55:45.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:45.730 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:55:45.731 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:55:45.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:55:45.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:55:45.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:55:45.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:45.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:55:45.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:55:45.747 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:55:45.747 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:55:45.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:55:45.804 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:55:45.804 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 02:55:45.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:45.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:55:45.898 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:55:46.376 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:55:46.854 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:55:47.333 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:55:47.812 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:55:48.291 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:55:48.770 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:55:49.248 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:55:49.726 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:55:50.205 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:55:50.683 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:55:51.161 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:55:51.639 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:55:52.118 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:55:52.597 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:55:53.074 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:55:53.549 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:55:54.027 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:55:54.505 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:55:54.983 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 02:55:55.462 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 02:55:55.940 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 02:55:56.419 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 02:55:56.898 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 02:55:57.376 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 02:55:57.854 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 02:55:58.332 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 02:55:58.811 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 02:55:59.290 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 02:55:59.768 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 02:56:00.247 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 02:56:00.725 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 02:56:01.204 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 02:56:01.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:56:01.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:01.398 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:56:01.398 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:56:01.398 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:56:01.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:56:01.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:56:01.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:56:01.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:01.414 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:56:01.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:56:01.414 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:56:01.414 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:56:01.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:56:01.444 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:56:01.445 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-05 02:56:01.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:01.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:01.682 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 02:56:02.160 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 02:56:02.638 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 02:56:03.117 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 02:56:03.596 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 02:56:04.074 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 02:56:04.553 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 02:56:05.031 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 02:56:05.510 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 02:56:05.988 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 02:56:06.466 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 02:56:06.945 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 02:56:07.432 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 02:56:07.910 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 02:56:08.388 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 02:56:08.866 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 02:56:09.345 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 02:56:09.823 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 02:56:10.302 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 02:56:10.781 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 02:56:11.259 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 02:56:11.738 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 02:56:12.215 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 02:56:12.694 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 02:56:13.173 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 02:56:13.650 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 02:56:14.129 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 02:56:14.607 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 02:56:15.086 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 02:56:15.564 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 02:56:16.042 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 02:56:16.520 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 02:56:16.999 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 02:56:17.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:56:17.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:17.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:56:17.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:56:17.079 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:56:17.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:56:17.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:56:17.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:56:17.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:17.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:56:17.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:56:17.103 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:56:17.103 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:56:17.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:17.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:56:17.147 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:56:17.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:56:17.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:17.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:17.477 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 02:56:17.954 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 02:56:18.432 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 02:56:18.910 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 02:56:19.387 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 02:56:19.865 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 02:56:20.343 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 02:56:20.821 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 02:56:21.299 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 02:56:21.777 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 02:56:22.254 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 02:56:22.732 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 02:56:23.210 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 02:56:23.687 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 02:56:24.166 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 02:56:24.643 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 02:56:25.122 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 02:56:25.599 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 02:56:26.077 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 02:56:26.554 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 02:56:27.032 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 02:56:27.510 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 02:56:27.988 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 02:56:28.466 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 02:56:28.943 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 02:56:29.421 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 02:56:29.899 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-05 02:56:30.376 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-05 02:56:30.854 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-05 02:56:31.332 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-05 02:56:31.810 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-05 02:56:32.288 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-05 02:56:32.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:56:32.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:32.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:56:32.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:56:32.733 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:56:32.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:56:32.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:56:32.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:56:32.737 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:56:32.737 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:56:32.737 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:56:32.737 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:56:32.737 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:56:32.738 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:56:32.738 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:56:32.738 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.738 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.738 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.738 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.739 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.739 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.739 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.739 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13562 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.739 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.739 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.739 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.739 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.739 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.739 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.739 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:32.740 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=13563 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:37.737 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:56:37.737 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:56:37.739 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:56:37.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:56:37.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:56:37.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:56:37.750 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:56:37.752 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:56:37.752 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:56:37.752 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:56:37.753 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:56:37.757 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:56:37.757 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:56:37.758 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:56:37.758 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:56:37.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:56:37.759 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:56:37.759 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:56:37.759 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:56:37.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:56:37.760 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:56:37.760 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:56:37.760 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:56:37.760 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:56:37.761 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:56:37.761 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:56:37.761 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:56:37.761 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:56:37.761 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:56:37.763 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:56:37.764 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:56:37.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:56:37.764 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:56:37.764 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:56:37.764 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:56:37.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:56:37.764 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:56:37.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:56:37.768 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:56:37.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:56:37.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:56:37.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:56:37.768 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:56:37.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:56:37.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:56:37.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:56:37.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:56:37.768 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:37.768 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:37.768 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:37.769 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:56:37.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:37.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:37.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:37.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:56:37.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:37.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:37.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:37.769 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:56:37.769 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:56:37.769 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:56:37.769 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:56:37.769 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:37.769 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:37.769 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:37.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:56:37.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:37.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:37.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:37.771 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:56:37.771 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:56:37.771 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:56:37.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:37.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:37.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:42.774 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:56:42.774 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:56:42.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:56:42.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:56:42.778 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:56:42.778 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:56:42.787 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:56:42.788 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:56:42.788 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:56:42.789 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:56:42.789 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:56:42.792 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:56:42.793 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:56:42.793 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:56:42.793 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:56:42.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:56:42.794 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:56:42.795 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:56:42.795 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:56:42.795 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:56:42.795 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:56:42.796 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:56:42.796 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:56:42.796 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:56:42.796 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:56:42.796 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:56:42.796 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:56:42.796 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:56:42.796 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:56:42.798 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:56:42.798 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:56:42.798 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:56:42.798 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:56:42.798 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:56:42.798 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:56:42.798 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:56:42.798 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:56:42.798 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:42.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:56:42.802 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:56:42.802 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:56:42.802 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:42.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:42.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:42.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:42.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:42.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:42.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:42.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:42.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:42.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:42.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:42.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:42.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:42.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:42.807 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:56:43.291 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:56:43.329 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:56:43.331 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:56:43.333 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:56:43.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:56:43.367 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:56:43.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:56:43.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:56:43.374 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:56:43.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:43.377 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:56:43.377 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:56:43.377 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:56:43.377 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:56:43.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:56:43.387 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:56:43.387 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:56:43.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:43.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:43.767 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:56:43.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:56:43.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:56:43.805 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:56:43.808 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:56:44.245 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:56:44.723 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:56:44.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:56:44.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:56:44.806 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:56:44.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:56:45.201 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:56:45.679 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:56:45.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:56:45.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:56:45.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:56:45.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:56:46.156 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:56:46.634 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:56:46.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:56:46.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:56:46.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:56:46.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:56:47.112 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:56:47.590 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:56:47.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:56:47.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:56:47.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:56:47.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:56:48.068 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:56:48.546 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:56:49.024 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:56:49.502 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:56:49.980 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:56:50.458 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:56:50.936 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:56:51.413 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:56:51.890 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:56:52.368 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:56:52.846 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:56:53.324 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:56:53.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:56:53.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:53.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:56:53.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:56:53.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:56:53.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:56:53.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:56:53.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:56:53.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:56:53.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:56:53.789 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:56:53.789 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:56:53.789 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:56:53.789 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:56:53.789 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:56:53.789 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:53.789 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:53.789 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:53.789 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:53.789 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:53.790 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:53.790 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2346 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:56:58.790 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:56:58.790 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:56:58.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:56:58.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:56:58.793 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:56:58.793 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:56:58.800 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:56:58.802 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:56:58.802 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:56:58.802 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:56:58.803 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:56:58.805 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:56:58.806 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:56:58.806 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:56:58.806 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:56:58.807 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:56:58.807 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:56:58.808 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:56:58.808 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:56:58.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:56:58.809 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:56:58.809 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:56:58.810 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:56:58.810 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:56:58.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:56:58.810 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:56:58.810 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:56:58.810 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:56:58.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:56:58.812 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:56:58.812 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:56:58.812 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:56:58.812 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:56:58.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:56:58.812 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:56:58.812 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:56:58.812 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:56:58.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:56:58.815 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:56:58.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:56:58.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:56:58.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:56:58.815 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:56:58.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:56:58.816 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:56:58.816 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:56:58.816 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:56:58.816 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:56:58.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:58.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:58.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:58.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:56:58.821 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:56:59.306 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:56:59.350 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:56:59.352 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:56:59.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:56:59.354 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:56:59.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:56:59.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:56:59.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:56:59.394 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:56:59.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:59.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:56:59.396 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:56:59.396 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:56:59.396 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:56:59.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:56:59.458 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:56:59.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:56:59.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:59.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:56:59.783 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:56:59.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:56:59.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:56:59.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:56:59.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:00.261 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:57:00.739 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:57:00.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:00.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:00.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:00.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:01.217 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:57:01.695 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:57:01.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:01.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:01.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:01.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:02.173 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:57:02.651 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:57:02.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:02.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:02.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:02.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:03.128 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:57:03.606 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:57:03.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:03.823 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:03.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:03.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:04.084 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:57:04.562 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:57:05.039 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:57:05.517 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:57:05.995 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:57:06.473 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:57:06.950 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:57:07.428 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:57:07.906 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:57:08.384 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:57:08.861 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:57:09.339 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:57:09.818 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:57:10.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:57:10.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:57:10.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:57:10.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:57:10.295 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:10.295 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:57:10.296 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:10.296 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:10.296 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:10.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:57:10.299 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:57:10.299 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:57:10.299 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:57:10.299 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:57:10.299 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:57:10.300 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:57:15.298 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:57:15.298 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:57:15.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:57:15.302 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:57:15.302 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:57:15.302 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:57:15.311 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:57:15.313 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:57:15.314 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:57:15.314 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:57:15.314 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:57:15.318 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:57:15.319 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:57:15.319 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:57:15.319 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:57:15.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:57:15.320 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:57:15.321 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:57:15.321 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:57:15.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:15.322 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:57:15.322 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:57:15.323 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:57:15.323 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:57:15.323 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:57:15.323 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:57:15.323 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:57:15.323 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:57:15.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:15.325 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:57:15.325 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:57:15.325 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:57:15.325 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:57:15.326 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:57:15.326 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:57:15.326 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:57:15.326 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:57:15.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:15.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:57:15.330 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:57:15.330 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:57:15.330 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:15.330 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:15.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:15.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:15.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:15.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:15.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:15.331 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:15.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:15.331 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:15.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:15.331 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:15.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:15.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:15.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:15.335 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:57:15.819 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:57:15.860 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:57:15.862 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:57:15.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:57:15.863 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:57:15.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:57:15.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:57:15.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:57:15.896 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:57:15.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:57:15.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:57:15.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:57:15.898 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:57:15.898 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:57:15.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:57:15.915 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:57:15.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:57:15.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:57:15.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:57:16.296 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:57:16.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:16.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:16.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:16.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:16.775 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:57:16.791 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:57:17.253 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:57:17.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:17.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:17.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:17.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:17.731 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:57:18.209 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:57:18.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:18.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:18.338 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:18.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:18.687 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:57:19.165 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:57:19.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:19.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:19.338 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:19.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:19.643 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:57:20.120 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:57:20.336 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:20.336 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:20.339 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:20.343 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:20.598 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:57:21.076 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:57:21.554 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:57:22.032 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:57:22.510 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:57:22.987 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:57:23.465 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:57:23.942 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:57:24.420 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:57:24.897 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:57:25.375 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:57:25.853 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:57:26.331 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:57:26.809 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:57:27.287 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:57:27.765 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:57:28.243 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:57:28.721 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:57:29.199 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:57:29.677 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:57:30.155 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:57:30.633 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:57:31.111 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:57:31.589 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:57:32.066 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:57:32.543 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:57:33.021 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:57:33.500 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:57:33.977 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:57:34.455 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:57:34.934 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:57:35.412 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:57:35.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:57:35.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:57:35.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:57:35.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:57:35.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:35.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:35.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:35.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:35.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:57:35.521 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:57:35.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:57:35.521 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:57:35.521 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:57:35.521 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:57:35.521 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:57:35.521 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:57:35.521 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:57:35.522 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:57:35.522 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:57:35.522 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:57:35.522 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:57:35.522 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4309 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:57:40.521 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:57:40.521 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:57:40.524 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:57:40.524 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:57:40.524 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:57:40.524 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:57:40.534 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:57:40.535 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:57:40.536 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:57:40.536 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:57:40.536 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:57:40.540 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:57:40.541 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:57:40.541 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:57:40.541 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:57:40.542 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:57:40.542 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:57:40.542 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:57:40.543 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:57:40.543 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:40.544 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:57:40.544 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:57:40.544 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:57:40.544 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:57:40.545 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:57:40.545 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:57:40.545 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:57:40.545 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:57:40.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:40.547 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:57:40.547 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:57:40.547 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:57:40.547 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:57:40.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:57:40.547 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:57:40.547 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:57:40.547 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:57:40.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:40.550 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:57:40.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:57:40.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:57:40.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:57:40.550 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:57:40.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:57:40.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:57:40.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:57:40.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:57:40.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:40.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:40.550 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:57:40.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:57:40.551 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:57:40.551 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:57:40.551 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:40.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:40.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:40.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:40.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:40.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:40.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:40.552 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:40.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:40.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:40.552 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:40.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:40.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:40.556 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:57:41.041 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:57:41.087 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:57:41.091 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:57:41.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:57:41.093 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:57:41.116 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:57:41.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:57:41.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:57:41.122 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:57:41.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:57:41.124 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:57:41.124 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:57:41.124 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:57:41.124 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:57:41.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:57:41.135 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:57:41.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:57:41.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:57:41.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:57:41.518 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:57:41.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:41.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:41.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:41.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:41.996 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:57:42.012 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:57:42.474 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:57:42.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:42.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:42.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:42.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:42.952 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:57:42.986 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:57:43.430 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:57:43.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:43.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:43.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:43.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:43.908 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:57:43.960 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:57:44.386 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:57:44.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:44.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:44.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:44.564 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:44.864 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:57:44.935 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:57:45.342 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:57:45.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:45.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:45.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:45.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:45.820 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:57:45.910 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:57:46.298 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:57:46.776 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:57:46.884 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:57:47.254 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:57:47.732 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:57:47.859 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:57:48.210 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:57:48.688 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:57:48.833 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:57:49.166 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:57:49.644 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:57:49.808 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:57:50.122 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:57:50.599 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:57:50.781 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:57:51.077 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:57:51.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:57:51.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:57:51.524 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:57:51.524 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:57:51.527 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:51.527 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:51.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:51.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:51.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:57:51.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:57:51.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:57:51.528 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:57:51.528 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:57:51.528 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:57:51.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:57:56.530 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:57:56.530 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:57:56.532 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:57:56.533 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:57:56.534 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:57:56.535 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:57:56.542 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:57:56.542 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:57:56.542 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:57:56.543 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:57:56.543 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:57:56.545 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:57:56.545 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:57:56.545 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:57:56.545 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:57:56.546 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:57:56.546 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:57:56.546 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:57:56.546 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:57:56.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:56.548 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:57:56.548 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:57:56.548 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:57:56.548 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:57:56.548 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:57:56.548 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:57:56.548 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:57:56.548 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:57:56.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:56.550 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:57:56.550 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:57:56.550 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:57:56.551 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:57:56.551 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:57:56.551 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:57:56.551 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:57:56.551 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:57:56.551 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:56.553 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:57:56.553 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:57:56.553 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:57:56.554 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:57:56.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:57:56.558 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:57:57.042 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:57:57.082 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:57:57.085 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:57:57.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:57:57.087 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:57:57.126 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:57:57.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:57:57.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:57:57.132 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:57:57.134 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:57:57.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:57:57.135 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:57:57.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:57:57.136 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:57:57.136 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:57:57.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:57:57.195 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:57:57.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:57:57.196 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:57:57.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:57:57.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:57:57.519 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:57:57.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:57.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:57.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:57.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:57.998 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:57:58.476 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:57:58.501 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:57:58.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:58.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:58.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:58.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:58.954 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:57:59.432 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:57:59.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:57:59.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:57:59.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:57:59.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:57:59.910 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:58:00.387 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:58:00.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:00.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:00.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:00.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:00.864 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:58:01.342 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:58:01.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:01.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:01.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:01.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:01.820 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:58:02.298 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:58:02.775 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:58:03.253 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:58:03.731 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:58:04.209 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:58:04.687 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:58:05.165 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:58:05.644 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:58:06.122 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:58:06.599 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:58:07.077 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:58:07.555 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:58:08.033 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:58:08.244 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:58:08.510 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:58:08.988 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:58:09.465 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:58:09.944 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:58:10.421 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:58:10.899 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:58:11.377 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:58:11.855 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:58:12.333 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:58:12.811 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:58:13.289 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:58:13.767 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:58:14.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:14.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:14.097 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:14.097 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:14.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:14.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:14.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:14.110 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:14.114 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:58:14.114 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:58:14.137 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:58:14.137 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:58:14.137 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:58:14.137 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:58:14.137 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3748 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3748 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3748 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3748 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3748 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3748 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3748 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3749 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3749 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3749 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3749 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3749 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3749 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3749 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3749 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3750 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3750 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3750 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3750 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3750 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3750 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3750 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3750 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3751 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3751 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3751 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3751 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.138 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3751 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3751 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3751 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3751 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3752 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3752 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3752 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3752 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3752 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3752 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3752 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3752 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3753 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3753 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3753 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3753 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3753 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3753 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3753 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3753 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3754 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3754 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3754 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3754 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3754 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3754 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3754 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:14.139 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3754 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:19.114 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:58:19.114 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:58:19.116 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:58:19.117 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:58:19.118 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:58:19.118 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:58:19.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:58:19.126 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:58:19.126 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:19.126 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:58:19.126 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:58:19.127 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:58:19.127 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:58:19.128 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:58:19.128 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:19.128 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:58:19.128 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:58:19.129 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:58:19.129 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:58:19.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:19.129 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:58:19.129 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:58:19.130 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:58:19.130 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:19.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:58:19.130 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:58:19.130 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:58:19.130 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:58:19.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:19.131 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:58:19.132 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:58:19.132 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:58:19.132 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:19.132 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:58:19.132 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:58:19.132 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:58:19.132 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:58:19.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:19.134 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:58:19.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:58:19.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:58:19.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:58:19.134 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:58:19.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:58:19.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:58:19.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:58:19.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:58:19.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:19.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:19.134 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:58:19.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:58:19.135 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:58:19.135 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:58:19.135 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:19.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:19.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:19.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:19.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:19.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:19.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:19.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:19.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:19.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:19.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:19.140 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:58:19.623 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:58:19.658 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:58:19.659 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:58:19.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:19.661 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:58:19.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:19.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:19.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:58:19.701 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:58:19.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:19.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:19.703 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:19.704 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:58:19.704 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:58:19.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:19.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:19.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:19.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:19.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:20.100 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:58:20.137 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:20.138 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:20.138 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:20.142 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:20.578 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:58:20.594 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:58:21.056 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:58:21.138 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:21.139 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:21.139 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:21.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:21.534 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:58:22.012 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:58:22.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:22.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:22.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:22.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:22.490 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:58:22.968 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:58:23.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:23.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:23.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:23.144 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:23.445 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:58:23.923 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:58:24.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:24.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:24.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:24.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:24.401 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:58:24.879 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:58:25.357 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:58:25.835 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:58:26.312 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:58:26.790 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:58:27.268 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:58:27.746 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:58:28.224 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:58:28.702 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:58:29.180 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:58:29.659 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:58:29.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:29.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:29.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:29.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:29.737 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:29.738 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:29.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:29.738 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:29.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:58:29.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:58:29.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:58:29.741 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:58:29.741 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:58:29.741 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:58:29.741 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:58:29.741 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2263 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:29.742 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2263 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:29.742 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2263 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:29.742 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2263 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:29.742 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2263 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:29.742 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2263 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:29.742 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2263 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:34.741 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:58:34.741 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:58:34.742 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:58:34.744 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:58:34.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:58:34.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:58:34.748 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:58:34.748 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:58:34.748 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:34.748 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:58:34.748 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:58:34.750 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:58:34.750 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:58:34.750 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:58:34.750 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:34.750 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:58:34.750 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:58:34.750 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:58:34.750 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:58:34.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:34.752 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:58:34.752 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:58:34.752 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:58:34.752 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:34.752 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:58:34.752 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:58:34.752 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:58:34.752 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:58:34.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:34.754 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:58:34.754 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:58:34.754 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:58:34.754 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:34.754 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:58:34.754 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:58:34.754 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:58:34.754 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:58:34.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:34.757 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:58:34.757 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:58:34.757 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:34.757 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:34.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:34.762 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:58:35.245 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:58:35.287 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:58:35.289 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:58:35.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:35.292 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:58:35.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:35.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:35.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:58:35.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:35.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:35.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:35.329 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:58:35.329 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:58:35.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:35.345 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:35.345 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:35.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:35.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:35.722 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:58:35.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:35.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:35.729 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:35.729 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:35.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:35.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:35.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:58:35.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:35.750 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:35.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:35.750 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:58:35.750 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:58:35.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:35.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:35.761 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:35.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:35.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:35.772 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:58:35.772 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:58:35.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:35.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:36.195 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:58:36.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:36.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:36.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:36.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:36.456 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:58:36.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:36.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:36.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:58:36.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:36.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:36.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:36.476 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:58:36.476 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:58:36.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:36.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:36.532 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:36.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:36.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:36.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:36.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:36.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:36.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:36.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:36.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:36.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:58:36.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:36.655 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:36.655 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:36.655 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:58:36.655 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:58:36.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:36.663 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:58:36.663 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:58:36.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:36.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:36.667 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:58:36.761 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:36.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:36.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:36.765 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:37.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:37.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:37.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:37.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:37.059 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:58:37.064 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:37.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:37.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:37.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:37.064 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:58:37.064 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:58:37.064 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:58:37.064 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:58:37.064 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:58:37.064 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:58:37.064 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:58:42.067 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:58:42.067 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:58:42.068 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:58:42.070 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:58:42.071 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:58:42.071 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:58:42.074 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:58:42.074 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:58:42.074 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:42.075 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:58:42.075 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:58:42.075 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:58:42.076 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:58:42.076 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:58:42.076 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:42.076 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:58:42.077 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:58:42.077 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:58:42.077 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:58:42.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:42.078 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:58:42.078 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:58:42.078 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:58:42.078 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:42.078 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:58:42.078 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:58:42.078 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:58:42.078 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:58:42.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:42.080 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:58:42.080 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:58:42.080 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:58:42.080 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:42.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:58:42.080 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:58:42.080 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:58:42.080 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:58:42.080 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:42.083 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:58:42.083 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:58:42.083 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:42.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:42.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:42.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:42.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:42.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:42.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:42.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:42.089 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:58:42.572 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:58:42.613 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:58:42.616 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:58:42.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:42.618 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:58:42.638 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:42.638 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:42.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:58:42.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:42.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:42.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:42.644 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:58:42.644 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:58:42.664 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:58:42.668 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 02:58:42.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:42.678 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:42.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:42.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:42.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:43.049 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:58:43.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:43.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:43.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:43.056 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:43.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:43.067 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:43.067 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:43.067 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:43.071 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:58:43.071 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:58:43.071 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:58:43.071 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:58:43.071 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:58:43.071 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:58:43.071 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:58:43.072 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=210 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:43.072 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=210 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:43.072 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=210 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:43.072 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=210 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:43.072 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=210 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:43.072 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=210 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:48.070 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:58:48.070 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:58:48.071 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:58:48.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:58:48.074 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:58:48.074 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:58:48.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:58:48.084 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:58:48.084 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:48.085 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:58:48.085 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:58:48.087 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:58:48.087 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:58:48.088 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:58:48.088 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:48.089 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:58:48.089 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:58:48.089 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:58:48.089 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:58:48.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:48.090 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:58:48.090 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:58:48.090 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:58:48.090 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:48.091 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:58:48.091 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:58:48.091 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:58:48.091 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:58:48.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:48.093 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:58:48.093 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:58:48.093 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:58:48.093 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:58:48.093 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:58:48.093 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:58:48.093 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:58:48.093 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:58:48.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:48.096 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:58:48.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:58:48.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:58:48.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:58:48.096 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:58:48.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:58:48.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:58:48.097 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:58:48.097 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:48.097 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:48.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:48.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:48.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:58:48.102 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:58:48.586 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:58:48.625 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:58:48.628 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:58:48.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:48.630 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:58:48.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:48.657 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:48.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:58:48.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:48.660 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:48.660 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:48.660 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:58:48.660 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:58:48.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:48.690 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:48.691 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:48.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:48.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:48.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:49.063 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:58:49.100 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:49.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:49.101 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:49.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:49.540 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:58:50.018 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:58:50.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:50.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:50.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:50.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:50.496 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:58:50.974 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:58:51.102 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:51.102 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:51.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:51.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:51.451 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:58:51.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:51.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:51.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:51.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:51.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:51.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:51.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:58:51.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:51.836 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:51.836 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:51.836 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:58:51.836 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:58:51.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:51.881 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:58:51.881 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 02:58:51.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:51.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:51.924 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:58:52.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:52.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:52.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:52.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:52.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:52.393 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:58:52.864 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:58:53.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:58:53.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:58:53.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:58:53.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:58:53.339 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:58:53.812 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:58:54.291 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:58:54.770 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:58:55.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:55.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:55.054 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:55.054 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:55.054 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:58:55.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:55.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:55.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:58:55.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:55.076 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:55.076 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:55.076 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:58:55.076 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:58:55.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:55.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:55.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:55.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:55.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:55.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:55.247 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:58:55.725 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:58:56.203 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:58:56.681 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:58:57.158 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:58:57.636 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:58:58.113 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:58:58.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:58.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:58.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:58.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:58.244 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=2172 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:58:58.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:58:58.264 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:58:58.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:58:58.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:58.265 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:58:58.265 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:58:58.265 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:58:58.265 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:58:58.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:58.307 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:58:58.307 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:58:58.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:58.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:58:58.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:58:58.591 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:58:59.069 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:58:59.547 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:59:00.025 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:59:00.504 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:59:00.982 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:59:01.453 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:59:01.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:59:01.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:59:01.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:59:01.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:59:01.512 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:59:01.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:01.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:01.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:01.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:01.525 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:59:01.525 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:59:01.525 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:59:01.525 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:59:01.525 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:59:01.525 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:59:01.526 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:59:01.526 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:01.526 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:01.526 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:01.526 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:01.526 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:01.526 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:01.527 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2873 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:06.524 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:59:06.525 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:59:06.526 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:59:06.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:59:06.527 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:59:06.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:59:06.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:59:06.534 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:59:06.534 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:59:06.534 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:59:06.534 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:59:06.537 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:59:06.537 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:59:06.537 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:59:06.537 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:59:06.537 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:59:06.537 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:59:06.538 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:59:06.538 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:59:06.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:06.540 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:59:06.540 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:59:06.540 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:59:06.540 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:59:06.541 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:59:06.541 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:59:06.541 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:59:06.541 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:59:06.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:06.543 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:59:06.543 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:59:06.543 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:59:06.543 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:59:06.543 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:59:06.543 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:59:06.543 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:59:06.543 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:59:06.543 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:06.546 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:59:06.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:59:06.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:59:06.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:59:06.546 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:59:06.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:59:06.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:59:06.547 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:59:06.547 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:59:06.547 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:06.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:06.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:06.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:06.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:06.552 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:59:07.037 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:59:07.081 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:59:07.083 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:59:07.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:59:07.085 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:59:07.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:59:07.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:59:07.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:59:07.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:59:07.089 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:59:07.089 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:59:07.090 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:59:07.090 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:59:07.514 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:59:07.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:07.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:07.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:07.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:07.992 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:59:08.469 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:59:08.551 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:08.552 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:08.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:08.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:08.946 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:59:09.424 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:59:09.552 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:09.552 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:09.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:09.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:09.901 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:59:10.379 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:59:10.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:10.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:10.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:10.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:10.856 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:59:11.334 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:59:11.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:11.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:11.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:11.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:11.812 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:59:12.289 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:59:12.766 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:59:13.244 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:59:13.722 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:59:14.200 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:59:14.678 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:59:15.156 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:59:15.634 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:59:16.111 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:59:16.589 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:59:17.067 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:59:17.545 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:59:18.022 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:59:18.500 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:59:18.978 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:59:19.455 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:59:19.933 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:59:20.411 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:59:20.890 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:59:21.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:59:21.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:59:21.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:21.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:21.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:21.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:21.187 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:59:21.187 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:59:21.187 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:59:21.187 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:59:21.187 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:59:21.187 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:59:21.187 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:59:21.187 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:21.187 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:21.187 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:21.187 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3126 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:21.187 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:21.187 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:21.187 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:21.187 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:21.187 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:21.187 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:21.187 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:26.188 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:59:26.188 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:59:26.189 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:59:26.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:59:26.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:59:26.192 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:59:26.204 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:59:26.205 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:59:26.205 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:59:26.205 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:59:26.205 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:59:26.207 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:59:26.208 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:59:26.208 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:59:26.208 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:59:26.208 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:59:26.208 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:59:26.208 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:59:26.208 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:59:26.209 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:26.209 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:59:26.209 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:59:26.210 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:59:26.210 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:59:26.210 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:59:26.210 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:59:26.210 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:59:26.210 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:59:26.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:26.211 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:59:26.211 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:59:26.211 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:59:26.211 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:59:26.211 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:59:26.211 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:59:26.211 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:59:26.211 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:59:26.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:59:26.213 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:59:26.213 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:59:26.213 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:26.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:26.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:26.218 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:59:26.701 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:59:26.734 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:59:26.737 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:59:26.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:59:26.739 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:59:26.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:59:26.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:59:26.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:59:26.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:59:26.771 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:59:26.771 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:59:26.771 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:59:26.772 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:59:26.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:59:26.805 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 02:59:26.805 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 02:59:26.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:59:26.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:59:27.179 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:59:27.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:27.216 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:27.216 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:27.217 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:27.657 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:59:28.135 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:59:28.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:28.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:28.217 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:28.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:28.614 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:59:28.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:59:28.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:59:28.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:59:28.807 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 02:59:28.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:59:28.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:59:28.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:59:28.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:59:28.810 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:59:28.810 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:59:29.092 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:59:29.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:29.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:29.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:29.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:29.569 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 02:59:30.047 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 02:59:30.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:30.219 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:30.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:30.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:30.525 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 02:59:31.003 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 02:59:31.220 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:31.220 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:31.221 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:31.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:31.481 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 02:59:31.959 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 02:59:32.437 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 02:59:32.914 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 02:59:33.392 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 02:59:33.870 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 02:59:34.348 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 02:59:34.825 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 02:59:35.303 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 02:59:35.780 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 02:59:36.258 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 02:59:36.736 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 02:59:37.214 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 02:59:37.692 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 02:59:38.169 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 02:59:38.647 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 02:59:39.125 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 02:59:39.602 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 02:59:40.080 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 02:59:40.558 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 02:59:41.035 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 02:59:41.513 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 02:59:41.991 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 02:59:42.469 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 02:59:42.946 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 02:59:43.424 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 02:59:43.902 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 02:59:44.380 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 02:59:44.858 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 02:59:45.336 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 02:59:45.814 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 02:59:46.291 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 02:59:46.769 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 02:59:47.247 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 02:59:47.724 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 02:59:48.202 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 02:59:48.680 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 02:59:49.158 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 02:59:49.636 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 02:59:50.114 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 02:59:50.592 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 02:59:51.069 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 02:59:51.548 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 02:59:51.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:59:51.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:59:51.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:59:51.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:51.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:51.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:51.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:51.841 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:59:51.841 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:59:51.841 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:59:51.841 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:59:51.841 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:59:51.841 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 02:59:51.841 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:59:51.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5471 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:51.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5471 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:51.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5471 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:51.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5471 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:51.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5471 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:51.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5471 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:51.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5471 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 02:59:56.842 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 02:59:56.842 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 02:59:56.844 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:59:56.845 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:59:56.846 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:59:56.846 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:59:56.851 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 02:59:56.852 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:59:56.853 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:59:56.853 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 02:59:56.853 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 02:59:56.855 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 02:59:56.856 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 02:59:56.856 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:59:56.857 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:59:56.857 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 02:59:56.857 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 02:59:56.858 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 02:59:56.858 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 02:59:56.858 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:56.859 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 02:59:56.859 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 02:59:56.859 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:59:56.859 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:59:56.859 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 02:59:56.859 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 02:59:56.859 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 02:59:56.859 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 02:59:56.860 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:56.862 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 02:59:56.862 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 02:59:56.862 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:59:56.862 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 02:59:56.862 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 02:59:56.862 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 02:59:56.862 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 02:59:56.862 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 02:59:56.862 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:56.865 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 02:59:56.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 02:59:56.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 02:59:56.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 02:59:56.865 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 02:59:56.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 02:59:56.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 02:59:56.866 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 02:59:56.866 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 02:59:56.866 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:56.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:56.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:56.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 02:59:56.871 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 02:59:57.356 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 02:59:57.394 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 02:59:57.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 02:59:57.397 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 02:59:57.400 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 02:59:57.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 02:59:57.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 02:59:57.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 02:59:57.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 02:59:57.404 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 02:59:57.404 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 02:59:57.404 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 02:59:57.404 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 02:59:57.829 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 02:59:57.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:57.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:57.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:57.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:58.308 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 02:59:58.785 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 02:59:58.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:58.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:58.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:58.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 02:59:59.263 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 02:59:59.741 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 02:59:59.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 02:59:59.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 02:59:59.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 02:59:59.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:00.219 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:00:00.696 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:00:00.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:00.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:00.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:00.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:01.174 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:00:01.652 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:00:01.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:01.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:01.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:01.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:02.127 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:00:02.604 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:00:03.081 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:00:03.559 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:00:04.037 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:00:04.515 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:00:04.993 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:00:05.470 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:00:05.948 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:00:06.426 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:00:06.904 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:00:07.381 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:00:07.859 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:00:08.337 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:00:08.814 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:00:09.292 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:00:09.770 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:00:10.248 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:00:10.725 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:00:11.203 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:00:11.681 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:00:12.158 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:00:12.635 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:00:13.113 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:00:13.591 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:00:14.066 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:00:14.541 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:00:15.013 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:00:15.491 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:00:15.968 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:00:16.445 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:00:16.922 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:00:17.399 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:00:17.877 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:00:18.355 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:00:18.832 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:00:18.886 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:00:18.886 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:00:18.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:18.891 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:18.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:18.891 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:18.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:00:18.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:00:18.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:00:18.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:00:18.895 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:00:18.895 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:00:18.895 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:00:18.896 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4706 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.896 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4706 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.896 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4706 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.896 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4706 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.896 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4706 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.896 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4706 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.896 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4706 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4707 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4707 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4707 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4707 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4707 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4707 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4707 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:18.897 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4707 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:00:23.894 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:00:23.894 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:00:23.897 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:00:23.897 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:00:23.897 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:00:23.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:00:23.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:00:23.909 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:00:23.909 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:00:23.910 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:00:23.910 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:00:23.915 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:00:23.915 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:00:23.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:00:23.916 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:00:23.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:00:23.917 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:00:23.917 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:00:23.918 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:00:23.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:23.919 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:00:23.919 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:00:23.919 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:00:23.920 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:00:23.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:00:23.920 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:00:23.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:00:23.921 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:00:23.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:23.922 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:00:23.922 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:00:23.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:00:23.922 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:00:23.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:00:23.922 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:00:23.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:00:23.923 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:00:23.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:23.925 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:00:23.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:00:23.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:00:23.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:00:23.925 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:00:23.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:00:23.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:00:23.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:00:23.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:00:23.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:23.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:23.925 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:00:23.926 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:00:23.926 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:00:23.926 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:23.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:23.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:23.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:23.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:23.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:23.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:23.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:23.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:23.931 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:00:24.415 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:00:24.454 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:00:24.456 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:00:24.458 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:00:24.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:00:24.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:00:24.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:00:24.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:00:24.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:00:24.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:00:24.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:00:24.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:00:24.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:00:24.892 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:00:24.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:24.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:24.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:24.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:25.370 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:00:25.847 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:00:25.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:25.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:25.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:25.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:26.325 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:00:26.803 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:00:26.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:26.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:26.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:26.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:27.281 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:00:27.758 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:00:27.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:27.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:27.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:27.933 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:28.235 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:00:28.713 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:00:28.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:28.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:28.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:28.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:29.191 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:00:29.668 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:00:30.146 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:00:30.624 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:00:31.101 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:00:31.579 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:00:32.057 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:00:32.534 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:00:33.012 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:00:33.490 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:00:33.967 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:00:34.445 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:00:34.922 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:00:35.400 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:00:35.877 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:00:36.355 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:00:36.832 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:00:37.310 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:00:37.787 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:00:38.265 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:00:38.742 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:00:39.220 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:00:39.697 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:00:40.175 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:00:40.653 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:00:41.131 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:00:41.609 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:00:42.087 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:00:42.564 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:00:43.042 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:00:43.519 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:00:43.997 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:00:44.474 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:00:44.952 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:00:45.429 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:00:45.907 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:00:45.945 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:00:45.945 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:00:45.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:45.947 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:45.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:45.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:45.948 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:00:45.948 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:00:45.948 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:00:45.948 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:00:45.948 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:00:45.948 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:00:45.948 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:00:50.951 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:00:50.951 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:00:50.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:00:50.954 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:00:50.955 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:00:50.955 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:00:50.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:00:50.962 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:00:50.962 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:00:50.962 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:00:50.962 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:00:50.963 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:00:50.963 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:00:50.964 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:00:50.964 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:00:50.964 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:00:50.964 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:00:50.964 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:00:50.964 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:00:50.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:50.966 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:00:50.966 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:00:50.966 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:00:50.966 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:00:50.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:00:50.967 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:00:50.967 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:00:50.967 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:00:50.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:50.969 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:00:50.969 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:00:50.969 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:00:50.969 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:00:50.969 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:00:50.969 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:00:50.969 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:00:50.969 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:00:50.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:50.971 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:50.972 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:00:50.972 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:00:50.972 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:00:50.972 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:50.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:00:50.977 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:00:51.461 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:00:51.504 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:00:51.506 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:00:51.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:00:51.508 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:00:51.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:00:51.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:00:51.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:00:51.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:00:51.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:00:51.514 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:00:51.515 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:00:51.515 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:00:51.938 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:00:51.975 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:51.975 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:51.976 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:51.979 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:52.416 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:00:52.893 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:00:52.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:52.977 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:52.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:52.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:53.371 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:00:53.848 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:00:53.977 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:53.977 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:53.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:53.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:54.325 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:00:54.803 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:00:54.978 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:54.979 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:54.979 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:54.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:55.281 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:00:55.759 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:00:55.979 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:00:55.979 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:00:55.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:00:55.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:00:56.236 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:00:56.714 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:00:57.192 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:00:57.670 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:00:58.147 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:00:58.625 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:00:59.103 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:00:59.581 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:01:00.058 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:01:00.536 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:01:01.014 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:01:01.492 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:01:01.969 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:01:02.447 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:01:02.925 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:01:03.403 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:01:03.880 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:01:04.358 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:01:04.836 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:01:05.314 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:01:05.791 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:01:06.269 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:01:06.747 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:01:07.225 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:01:07.703 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:01:08.180 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:01:08.658 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:01:09.135 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:01:09.613 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:01:10.091 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:01:10.569 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:01:11.047 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:01:11.525 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:01:12.002 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:01:12.480 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:01:12.958 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:01:13.436 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:01:13.913 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:01:14.391 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:01:14.868 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:01:15.346 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:01:15.824 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:01:16.301 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:01:16.779 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:01:17.257 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:01:17.734 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 03:01:18.212 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 03:01:18.690 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 03:01:19.167 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 03:01:19.645 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 03:01:20.123 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 03:01:20.601 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 03:01:21.079 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 03:01:21.556 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 03:01:22.034 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 03:01:22.512 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 03:01:22.990 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 03:01:23.467 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 03:01:23.944 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 03:01:24.422 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 03:01:24.899 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 03:01:24.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:01:24.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:01:25.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:01:25.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:01:25.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:01:25.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:01:25.005 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:01:25.005 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:01:25.005 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:01:25.005 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:01:25.006 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:01:25.006 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:01:25.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:01:25.006 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7266 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.006 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7266 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.006 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7266 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.007 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7266 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.007 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7266 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.007 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7266 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.007 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7266 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.007 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7266 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.007 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7267 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.007 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7267 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.007 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7267 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.007 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7267 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.007 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7267 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.007 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7267 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.007 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7267 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:25.008 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7267 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:30.005 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:01:30.005 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:01:30.006 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:01:30.008 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:01:30.009 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:01:30.009 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:01:30.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:01:30.015 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:01:30.016 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:01:30.016 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:01:30.016 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:01:30.019 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:01:30.020 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:01:30.020 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:01:30.020 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:01:30.021 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:01:30.021 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:01:30.022 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:01:30.022 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:01:30.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:01:30.022 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:01:30.023 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:01:30.023 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:01:30.023 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:01:30.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:01:30.023 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:01:30.023 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:01:30.023 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:01:30.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:01:30.025 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:01:30.025 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:01:30.025 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:01:30.025 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:01:30.025 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:01:30.025 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:01:30.025 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:01:30.025 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:01:30.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:01:30.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:01:30.029 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:01:30.029 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:01:30.029 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:01:30.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:01:30.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:01:30.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:01:30.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:01:30.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:01:30.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:01:30.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:01:30.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:01:30.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:01:30.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:01:30.034 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:01:30.518 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:01:30.559 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:01:30.560 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:01:30.562 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:01:30.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:01:30.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:01:30.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:01:30.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:01:30.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:01:30.566 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:01:30.566 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:01:30.566 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:01:30.566 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:01:30.995 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:01:31.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:01:31.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:01:31.034 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:01:31.038 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:01:31.473 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:01:31.950 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:01:32.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:01:32.033 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:01:32.034 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:01:32.039 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:01:32.428 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:01:32.906 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:01:33.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:01:33.034 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:01:33.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:01:33.040 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:01:33.383 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:01:33.861 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:01:34.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:01:34.035 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:01:34.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:01:34.041 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:01:34.337 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:01:34.814 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:01:35.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:01:35.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:01:35.037 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:01:35.041 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:01:35.292 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:01:35.770 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:01:36.248 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:01:36.726 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:01:37.203 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:01:37.681 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:01:38.159 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:01:38.636 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:01:39.113 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:01:39.591 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:01:40.069 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:01:40.546 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:01:41.024 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:01:41.502 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:01:41.979 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:01:42.457 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:01:42.934 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:01:43.412 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:01:43.890 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:01:44.368 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:01:44.845 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:01:45.323 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:01:45.801 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:01:46.278 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:01:46.756 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:01:47.234 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:01:47.711 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:01:48.189 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:01:48.667 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:01:49.145 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:01:49.622 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:01:50.100 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:01:50.578 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:01:51.056 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:01:51.534 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:01:52.012 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:01:52.489 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:01:52.967 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:01:53.444 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:01:53.921 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:01:54.399 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:01:54.877 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:01:55.354 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:01:55.832 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:01:56.310 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:01:56.788 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 03:01:57.265 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 03:01:57.743 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 03:01:58.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:01:58.052 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:01:58.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:01:58.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:01:58.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:01:58.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:01:58.060 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:01:58.060 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:01:58.061 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:01:58.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:01:58.061 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:01:58.061 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:01:58.061 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:01:58.061 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5986 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:58.061 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5986 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:58.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5986 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:58.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5986 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:58.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5986 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:01:58.062 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5986 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:03.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:02:03.061 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:02:03.064 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:03.064 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:03.064 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:03.064 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:03.074 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:03.075 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:02:03.075 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:03.076 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:02:03.076 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:02:03.080 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:02:03.081 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:02:03.081 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:02:03.081 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:03.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:03.082 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:02:03.082 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:02:03.082 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:02:03.083 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:03.085 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:02:03.085 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:02:03.086 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:02:03.086 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:03.086 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:03.086 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:02:03.086 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:02:03.086 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:02:03.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:03.089 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:02:03.089 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:02:03.089 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:02:03.089 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:03.089 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:03.089 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:02:03.089 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:02:03.089 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:02:03.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:03.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:03.094 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:02:03.094 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:02:03.094 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:02:03.094 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:02:03.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:03.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:03.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:03.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:02:03.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:03.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:03.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:03.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:03.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:03.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:03.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:03.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:03.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:03.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:03.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:03.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:03.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:03.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:03.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:03.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:03.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:03.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:03.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:03.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:03.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:03.099 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:02:03.580 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:02:03.625 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:02:03.627 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:02:03.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:02:03.630 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:02:03.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:03.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:03.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:03.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:03.642 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:03.643 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:03.643 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:03.643 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:03.643 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:02:03.643 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:02:03.643 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:02:03.643 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:03.643 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:03.643 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:03.643 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:03.643 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:03.643 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:03.643 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:08.647 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:02:08.647 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:02:08.647 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:08.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:08.647 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:08.647 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:08.655 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:08.657 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:02:08.657 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:08.658 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:02:08.658 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:02:08.663 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:02:08.663 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:02:08.664 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:02:08.664 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:08.664 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:08.665 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:02:08.665 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:02:08.665 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:02:08.665 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:08.667 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:02:08.667 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:02:08.667 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:02:08.667 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:08.667 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:08.668 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:02:08.668 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:02:08.668 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:02:08.668 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:08.669 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:02:08.670 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:02:08.670 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:02:08.670 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:08.670 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:08.670 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:02:08.670 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:02:08.670 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:02:08.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:08.673 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:02:08.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:02:08.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:02:08.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:02:08.673 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:02:08.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:02:08.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:02:08.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:02:08.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:02:08.673 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:08.673 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:08.673 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:02:08.673 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:02:08.674 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:02:08.674 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:02:08.674 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:08.674 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:08.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:08.679 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:02:09.164 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:02:09.201 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:02:09.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:02:09.204 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:02:09.207 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:02:09.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:09.218 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:09.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:09.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:09.221 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:09.221 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:09.221 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:09.221 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:09.221 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:02:09.221 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:02:09.221 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:02:09.221 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:09.221 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:09.221 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:09.221 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:09.221 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:09.222 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:09.222 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:09.222 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:09.222 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:09.222 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:09.222 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:14.222 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:02:14.222 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:02:14.223 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:14.225 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:14.225 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:14.225 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:14.232 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:14.233 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:02:14.234 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:14.234 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:02:14.234 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:02:14.236 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:02:14.236 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:02:14.236 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:02:14.236 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:14.237 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:14.237 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:02:14.237 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:02:14.237 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:02:14.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:14.238 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:02:14.239 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:02:14.239 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:02:14.239 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:14.239 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:14.239 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:02:14.239 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:02:14.239 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:02:14.239 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:14.240 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:02:14.241 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:02:14.241 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:02:14.241 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:14.241 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:14.241 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:02:14.241 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:02:14.241 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:02:14.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:14.243 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:02:14.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:02:14.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:02:14.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:02:14.243 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:02:14.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:02:14.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:02:14.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:02:14.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:02:14.244 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:02:14.244 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:02:14.244 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:14.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:14.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:14.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:14.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:14.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:14.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:14.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:14.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:14.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:14.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:14.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:14.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:14.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:14.249 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:02:14.734 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:02:14.775 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:02:14.777 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:02:14.779 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:02:14.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:02:14.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:14.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:14.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:14.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:14.795 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:14.795 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:14.795 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:14.795 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:14.795 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:02:14.795 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:02:14.795 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:02:14.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:14.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:14.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:14.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:14.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:14.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:14.796 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:19.795 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:02:19.795 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:02:19.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:19.799 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:19.799 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:19.799 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:19.807 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:19.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:02:19.807 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:19.808 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:02:19.808 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:02:19.810 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:02:19.810 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:02:19.811 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:02:19.811 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:19.811 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:19.811 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:02:19.812 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:02:19.812 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:02:19.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:19.813 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:02:19.813 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:02:19.813 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:02:19.813 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:19.813 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:19.813 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:02:19.813 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:02:19.813 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:02:19.814 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:19.815 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:02:19.815 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:02:19.815 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:02:19.815 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:19.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:19.815 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:02:19.815 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:02:19.815 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:02:19.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:02:19.818 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:02:19.818 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:02:19.818 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:02:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:19.823 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:02:20.308 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:02:20.344 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:02:20.347 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:02:20.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:02:20.349 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:02:20.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:02:20.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:02:20.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:02:20.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:02:20.354 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:02:20.355 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:02:20.355 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:02:20.355 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:02:20.785 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:02:20.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:20.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:20.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:20.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:21.263 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:02:21.741 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:02:21.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:21.823 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:21.823 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:21.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:22.218 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:02:22.696 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:02:22.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:22.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:22.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:22.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:23.174 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:02:23.651 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:02:23.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:23.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:23.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:23.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:24.129 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:02:24.606 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:02:24.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:24.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:24.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:24.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:25.084 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:02:25.561 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:02:26.039 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:02:26.517 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:02:26.994 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:02:27.472 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:02:27.950 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:02:28.406 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:02:28.406 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:02:28.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:28.411 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:28.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:28.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:28.414 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:28.414 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:28.414 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:28.414 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:02:28.414 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:02:28.414 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:02:28.414 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:28.414 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:28.414 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:28.414 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:28.414 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:28.414 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:28.414 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:28.414 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:28.414 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:33.414 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:02:33.414 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:02:33.418 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:33.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:33.418 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:33.418 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:33.430 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:33.430 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:02:33.430 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:33.430 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:02:33.430 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:02:33.431 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:02:33.431 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:02:33.431 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:02:33.431 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:33.431 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:33.431 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:02:33.431 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:02:33.431 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:02:33.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:33.433 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:02:33.433 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:02:33.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:02:33.433 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:33.433 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:02:33.433 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:33.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:02:33.433 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:02:33.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:33.435 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:02:33.435 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:02:33.435 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:02:33.435 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:33.435 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:02:33.435 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:33.435 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:02:33.435 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:02:33.435 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:33.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:02:33.438 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:02:33.438 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:02:33.438 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:33.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:33.442 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:02:33.926 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:02:33.965 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:02:33.967 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:02:33.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:02:33.969 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:02:33.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:02:33.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:02:33.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:02:33.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:02:33.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:02:33.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:02:33.974 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:02:33.974 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:02:34.404 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:02:34.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:34.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:34.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:34.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:34.881 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:02:35.358 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:02:35.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:35.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:35.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:35.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:35.836 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:02:36.313 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:02:36.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:36.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:36.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:36.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:36.791 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:02:37.268 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:02:37.444 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:37.444 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:37.444 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:37.444 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:37.746 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:02:38.224 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:02:38.444 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:38.445 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:38.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:38.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:38.701 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:02:39.178 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:02:39.656 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:02:40.133 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:02:40.611 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:02:41.088 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:02:41.566 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:02:42.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:02:42.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:02:42.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:42.026 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:42.026 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:42.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:42.029 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:42.029 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:42.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:42.029 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:42.029 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:02:42.029 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:02:42.029 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:02:42.029 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:42.029 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:42.029 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:42.029 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:42.029 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:42.029 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:42.029 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:47.030 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:02:47.030 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:02:47.032 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:47.033 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:47.034 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:47.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:47.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:47.045 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:02:47.045 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:47.046 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:02:47.046 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:02:47.050 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:02:47.051 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:02:47.051 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:02:47.051 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:47.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:47.052 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:02:47.053 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:02:47.053 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:02:47.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:47.054 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:02:47.054 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:02:47.055 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:02:47.055 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:47.055 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:47.055 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:02:47.056 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:02:47.056 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:02:47.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:47.057 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:02:47.057 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:02:47.057 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:02:47.057 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:02:47.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:47.058 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:02:47.058 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:02:47.058 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:02:47.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:47.061 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:02:47.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:02:47.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:02:47.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:02:47.061 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:02:47.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:02:47.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:02:47.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:02:47.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:02:47.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:47.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:02:47.062 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:02:47.062 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:02:47.062 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:47.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:47.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:02:47.067 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:02:47.551 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:02:47.592 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:02:47.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:02:47.595 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:02:47.599 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:02:47.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:02:47.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:02:47.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:02:47.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:02:47.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:02:47.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:02:47.606 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:02:47.606 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:02:48.029 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:02:48.066 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:48.066 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:48.067 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:48.070 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:48.506 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:02:48.983 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:02:49.066 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:49.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:49.067 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:49.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:49.461 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:02:49.938 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:02:50.068 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:50.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:50.068 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:50.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:50.416 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:02:50.893 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:02:51.069 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:51.069 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:51.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:51.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:51.370 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:02:51.848 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:02:52.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:52.070 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:52.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:52.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:52.326 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:02:52.804 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:02:53.281 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:02:53.758 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:02:54.236 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:02:54.713 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:02:55.191 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:02:55.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:02:55.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:02:55.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:02:55.656 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:02:55.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:02:55.656 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:02:55.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:02:55.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:02:55.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:02:55.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:02:55.659 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:02:55.659 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:02:55.659 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:02:55.659 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:55.659 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:55.659 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:55.659 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1836 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:55.659 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:55.659 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:55.659 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:55.659 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:55.659 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:55.659 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:55.659 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:02:55.659 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:00.662 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:03:00.662 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:03:00.662 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:03:00.662 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:03:00.662 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:03:00.662 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:03:00.672 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:03:00.674 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:03:00.674 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:00.675 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:03:00.675 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:03:00.679 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:03:00.679 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:03:00.680 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:03:00.680 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:00.680 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:03:00.681 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:03:00.681 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:03:00.681 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:03:00.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:00.682 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:03:00.683 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:03:00.683 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:03:00.683 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:00.683 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:03:00.683 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:03:00.683 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:03:00.683 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:03:00.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:00.686 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:03:00.686 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:03:00.686 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:03:00.686 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:00.686 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:03:00.686 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:03:00.686 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:03:00.686 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:03:00.686 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:00.689 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:03:00.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:03:00.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:03:00.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:03:00.689 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:03:00.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:03:00.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:03:00.690 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:03:00.690 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:03:00.690 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:00.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:00.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:00.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:00.695 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:03:01.179 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:03:01.219 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:03:01.221 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:03:01.222 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:03:01.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:03:01.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:03:01.223 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:03:01.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:03:01.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:03:01.224 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:03:01.224 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:03:01.224 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:03:01.224 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:03:01.656 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:03:01.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:01.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:01.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:01.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:02.134 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:03:02.611 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:03:02.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:02.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:02.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:02.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:03.089 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:03:03.566 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:03:03.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:03.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:03.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:03.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:04.044 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:03:04.522 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:03:04.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:04.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:04.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:04.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:04.999 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:03:05.477 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:03:05.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:05.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:05.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:05.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:05.955 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:03:06.433 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:03:06.911 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:03:07.388 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:03:07.866 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:03:08.344 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:03:08.821 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:03:09.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:03:09.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:03:09.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:09.285 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:09.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:09.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:09.288 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:03:09.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:03:09.288 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:03:09.289 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:03:09.289 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:03:09.289 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:03:09.289 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:03:09.289 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:09.289 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:09.289 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:09.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:09.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:09.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:09.290 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1837 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:14.287 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:03:14.287 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:03:14.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:03:14.290 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:03:14.290 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:03:14.291 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:03:14.303 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:03:14.304 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:03:14.305 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:14.305 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:03:14.305 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:03:14.308 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:03:14.308 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:03:14.309 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:03:14.309 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:14.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:03:14.310 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:03:14.310 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:03:14.310 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:03:14.310 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:14.311 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:03:14.311 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:03:14.311 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:03:14.311 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:14.311 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:03:14.311 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:03:14.311 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:03:14.312 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:03:14.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:14.313 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:03:14.313 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:03:14.314 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:03:14.314 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:14.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:03:14.314 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:03:14.314 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:03:14.314 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:03:14.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:14.316 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:03:14.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:14.317 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:03:14.317 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:03:14.317 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:03:14.317 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:14.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:14.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:14.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:14.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:14.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:14.322 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:03:14.807 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:03:14.851 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:03:14.854 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:03:14.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:03:14.856 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:03:14.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:03:14.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:03:14.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:03:14.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:03:14.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:03:14.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:03:14.862 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:03:14.862 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:03:15.284 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:03:15.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:15.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:15.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:15.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:15.762 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:03:16.239 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:03:16.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:16.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:16.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:16.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:16.717 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:03:17.194 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:03:17.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:17.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:17.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:17.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:17.672 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:03:18.149 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:03:18.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:18.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:18.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:18.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:18.627 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:03:19.105 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:03:19.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:19.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:19.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:19.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:19.582 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:03:20.060 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:03:20.537 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:03:21.015 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:03:21.493 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:03:21.970 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:03:22.448 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:03:22.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:03:22.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:03:22.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:22.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:22.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:22.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:22.904 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:03:22.905 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:03:22.905 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:03:22.905 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:03:22.905 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:03:22.905 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:03:22.905 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:03:22.905 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:22.905 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:22.905 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:22.905 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:22.905 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:22.905 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:22.905 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:22.905 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:27.908 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:03:27.908 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:03:27.909 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:03:27.914 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:03:27.914 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:03:27.915 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:03:27.922 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:03:27.924 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:03:27.924 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:27.924 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:03:27.925 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:03:27.928 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:03:27.928 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:03:27.929 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:03:27.929 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:27.929 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:03:27.929 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:03:27.929 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:03:27.929 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:03:27.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:27.932 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:03:27.932 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:03:27.932 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:03:27.933 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:27.933 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:03:27.933 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:03:27.933 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:03:27.933 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:03:27.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:27.935 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:03:27.935 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:03:27.935 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:03:27.935 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:27.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:03:27.935 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:03:27.935 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:03:27.935 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:03:27.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:27.938 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:03:27.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:03:27.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:03:27.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:03:27.938 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:03:27.939 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:03:27.939 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:03:27.939 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:03:27.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:27.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:27.941 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:27.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:27.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:27.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:27.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:27.944 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:03:28.428 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:03:28.470 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:03:28.472 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:03:28.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:03:28.474 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:03:28.477 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:03:28.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:03:28.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:03:28.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:03:28.480 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:03:28.480 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:03:28.481 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:03:28.481 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:03:28.905 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:03:28.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:28.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:28.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:28.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:29.383 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:03:29.860 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:03:29.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:29.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:29.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:29.949 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:30.338 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:03:30.816 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:03:30.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:30.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:30.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:30.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:31.293 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:03:31.771 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:03:31.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:31.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:31.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:31.951 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:32.248 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:03:32.725 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:03:32.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:32.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:32.948 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:32.952 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:33.203 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:03:33.681 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:03:34.158 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:03:34.636 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:03:35.113 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:03:35.591 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:03:36.069 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:03:36.547 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:03:37.024 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:03:37.502 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:03:37.979 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:03:38.457 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:03:38.934 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:03:39.412 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:03:39.890 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:03:40.367 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:03:40.844 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:03:41.322 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:03:41.800 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:03:42.277 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:03:42.755 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:03:43.232 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:03:43.710 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:03:44.188 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:03:44.532 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:03:44.532 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:03:44.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:44.537 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:44.537 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:44.537 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:44.541 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:03:44.541 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:03:44.541 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:03:44.541 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:03:44.541 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:03:44.541 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:03:44.541 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:03:44.542 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3546 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:44.542 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3546 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:44.542 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3546 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:44.542 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3546 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:44.542 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3546 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:44.542 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3546 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:49.539 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:03:49.540 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:03:49.542 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:03:49.543 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:03:49.543 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:03:49.544 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:03:49.548 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:03:49.549 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:03:49.549 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:49.549 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:03:49.549 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:03:49.549 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:03:49.549 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:03:49.550 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:03:49.550 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:49.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:03:49.550 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:03:49.551 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:03:49.551 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:03:49.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:49.552 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:03:49.552 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:03:49.552 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:03:49.552 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:49.552 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:03:49.552 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:03:49.552 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:03:49.552 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:03:49.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:49.554 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:03:49.554 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:03:49.554 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:03:49.554 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:03:49.554 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:03:49.554 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:03:49.554 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:03:49.554 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:03:49.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:49.557 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:03:49.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:03:49.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:03:49.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:03:49.557 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:03:49.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:03:49.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:03:49.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:03:49.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:03:49.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:49.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:03:49.558 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:03:49.558 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:03:49.558 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:49.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:49.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:03:49.563 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:03:50.046 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:03:50.090 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:03:50.092 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:03:50.094 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:03:50.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:03:50.105 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:03:50.105 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:03:50.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:03:50.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:03:50.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:03:50.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:03:50.105 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:03:50.105 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:03:50.523 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:03:50.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:50.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:50.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:50.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:51.001 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:03:51.479 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:03:51.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:51.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:51.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:51.567 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:51.956 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:03:52.434 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:03:52.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:52.563 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:52.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:52.568 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:52.912 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:03:53.389 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:03:53.563 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:53.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:53.564 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:53.569 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:53.866 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:03:54.344 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:03:54.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:54.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:54.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:54.570 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:54.821 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:03:55.299 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:03:55.776 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:03:56.254 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:03:56.732 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:03:57.209 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:03:57.687 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:03:58.146 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:03:58.146 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:03:58.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:03:58.159 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:03:58.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:03:58.159 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:03:58.163 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:03:58.163 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:03:58.163 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:03:58.163 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:03:58.164 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:03:58.164 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:03:58.164 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:03:58.164 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1838 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:58.164 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1838 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:58.164 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1838 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:58.164 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1838 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:58.165 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1838 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:58.165 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1838 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:58.165 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:58.165 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:58.165 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:58.165 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:58.165 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:58.165 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:58.165 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:03:58.165 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1839 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:03.162 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:03.162 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:03.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:03.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:03.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:03.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:03.175 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:03.177 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:03.177 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:03.177 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:03.178 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:04:03.180 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:04:03.181 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:04:03.181 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:03.182 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:03.182 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:03.183 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:04:03.183 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:03.183 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:04:03.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:03.184 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:04:03.184 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:04:03.185 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:03.185 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:03.185 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:03.185 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:04:03.186 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:03.186 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:04:03.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:03.187 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:04:03.187 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:04:03.187 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:03.187 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:03.187 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:03.187 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:04:03.187 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:03.187 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:04:03.188 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:03.190 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:04:03.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:04:03.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:04:03.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:04:03.190 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:04:03.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:04:03.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:04:03.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:04:03.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:04:03.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:04:03.191 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:04:03.191 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:04:03.191 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:03.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:03.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:03.196 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:04:03.680 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:04:03.726 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:04:03.728 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:04:03.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:04:03.730 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:04:03.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:04:03.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:04:03.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:04:03.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:04:03.739 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:04:03.740 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:04:03.740 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:04:03.740 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:04:04.157 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:04:04.195 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:04.195 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:04.197 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:04.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:04.634 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:04:05.112 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:04:05.195 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:05.196 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:05.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:05.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:05.590 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:04:06.067 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:04:06.197 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:06.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:06.199 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:06.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:06.545 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:04:07.023 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:04:07.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:07.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:07.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:07.206 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:07.500 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:04:07.978 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:04:08.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:08.200 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:08.202 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:08.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:08.455 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:04:08.933 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:04:09.411 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:04:09.888 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:04:10.366 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:04:10.844 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:04:11.322 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:04:11.814 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:04:12.292 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:04:12.769 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:04:13.246 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:04:13.724 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:04:14.201 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:04:14.679 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:04:15.157 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:04:15.634 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:04:16.112 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:04:16.590 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:04:17.067 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:04:17.545 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:04:18.023 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:04:18.500 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:04:18.978 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:04:19.456 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:04:19.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:04:19.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:04:19.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:19.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:19.790 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:19.790 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:19.793 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:19.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:19.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:19.794 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:19.794 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:19.794 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:04:19.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:19.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3543 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:19.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3543 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:19.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3543 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:19.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3543 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:19.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3543 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:19.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3543 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:19.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3543 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:24.793 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:24.793 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:24.795 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:24.796 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:24.797 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:24.797 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:24.806 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:24.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:24.807 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:24.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:24.808 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:04:24.810 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:04:24.810 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:04:24.810 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:24.810 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:24.811 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:24.811 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:04:24.812 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:24.812 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:04:24.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:24.813 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:04:24.814 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:04:24.814 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:24.814 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:24.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:24.815 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:04:24.815 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:24.815 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:04:24.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:24.816 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:04:24.816 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:04:24.816 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:24.816 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:24.817 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:24.817 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:04:24.817 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:24.817 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:04:24.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:24.820 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:04:24.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:04:24.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:04:24.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:04:24.820 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:04:24.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:04:24.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:04:24.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:04:24.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:04:24.821 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:04:24.821 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:04:24.821 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:24.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:24.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:24.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:24.826 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:04:25.310 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:04:25.356 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:04:25.358 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:04:25.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:04:25.360 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:04:25.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:04:25.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:04:25.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:04:25.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:25.396 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:25.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:25.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:25.399 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:25.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:25.399 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:25.399 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:25.399 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:04:25.399 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:25.399 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:25.399 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:25.399 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:25.399 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:25.399 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:25.399 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:25.399 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:25.399 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:30.400 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:30.401 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:30.402 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:30.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:30.404 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:30.404 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:30.411 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:30.412 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:30.412 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:30.413 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:30.413 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:04:30.416 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:04:30.416 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:04:30.417 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:30.417 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:30.417 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:30.417 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:04:30.418 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:30.418 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:04:30.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:30.419 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:04:30.419 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:04:30.419 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:30.419 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:30.419 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:30.419 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:04:30.420 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:30.420 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:04:30.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:30.422 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:04:30.422 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:04:30.422 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:30.422 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:30.422 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:30.422 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:04:30.422 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:30.422 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:04:30.422 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:30.425 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:04:30.425 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:04:30.425 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:04:30.425 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:04:30.425 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:04:30.425 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:04:30.425 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:04:30.425 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:04:30.426 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:04:30.426 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:04:30.426 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:04:30.426 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:30.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:30.431 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:04:30.915 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:04:30.954 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:04:30.956 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:04:30.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:04:30.959 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:04:30.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:04:30.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:04:30.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:04:30.993 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:30.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:30.993 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:30.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:30.996 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:30.996 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:30.996 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:30.996 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:30.997 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:30.997 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:30.997 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:04:30.997 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:30.997 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:30.997 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:30.997 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:30.997 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:30.997 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:35.997 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:35.997 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:36.000 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:36.000 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:36.000 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:36.000 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:36.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:36.012 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:36.012 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:36.013 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:36.013 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:04:36.017 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:04:36.017 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:04:36.017 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:36.018 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:36.018 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:36.018 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:04:36.018 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:36.018 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:04:36.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:36.021 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:04:36.021 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:04:36.021 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:36.021 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:36.021 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:36.021 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:04:36.022 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:36.022 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:04:36.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:36.024 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:04:36.024 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:04:36.024 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:36.024 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:36.024 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:36.024 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:04:36.025 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:36.025 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:04:36.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:36.028 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:04:36.028 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:04:36.028 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:04:36.029 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:04:36.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:36.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:36.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:36.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:04:36.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:36.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:36.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:36.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:36.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:36.029 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:36.029 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:36.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:36.029 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:36.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:36.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:36.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:36.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:36.030 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:36.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:36.030 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:36.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:36.030 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:36.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:36.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:36.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:36.033 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:04:36.517 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:04:36.563 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:04:36.564 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:04:36.566 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:04:36.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:04:36.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:04:36.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:04:36.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:04:36.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:36.608 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:36.608 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:36.608 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:36.611 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:36.611 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:36.611 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:36.611 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:36.611 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:36.611 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:36.611 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:04:36.611 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.611 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.611 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.611 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.611 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.611 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.612 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.612 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.612 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.612 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.612 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.612 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.612 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.612 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:36.612 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:41.615 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:41.615 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:41.615 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:41.615 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:41.615 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:41.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:41.624 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:41.626 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:41.626 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:41.627 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:41.627 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:04:41.631 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:04:41.631 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:04:41.631 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:41.631 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:41.632 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:41.632 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:04:41.632 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:41.632 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:04:41.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:41.634 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:04:41.635 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:04:41.635 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:41.635 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:41.636 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:41.636 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:04:41.636 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:41.636 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:04:41.637 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:41.637 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:04:41.637 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:04:41.637 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:41.638 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:41.638 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:41.638 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:04:41.638 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:41.638 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:04:41.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:41.641 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:41.642 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:41.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:41.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:41.642 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:04:41.642 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:04:41.642 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:04:41.642 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:04:41.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:41.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:41.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:41.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:04:41.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:41.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:41.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:41.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:41.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:41.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:41.647 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:04:42.130 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:04:42.177 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:04:42.179 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:04:42.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:04:42.181 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:04:42.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:04:42.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:04:42.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:04:42.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:42.225 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:42.225 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:42.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:42.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:42.227 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:42.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:42.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:42.227 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:42.227 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:42.227 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:04:42.228 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:42.228 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:42.228 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:42.228 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:42.228 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:42.228 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:04:47.229 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:47.229 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:47.232 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:47.232 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:47.232 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:47.232 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:47.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:47.240 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:47.240 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:47.240 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:47.241 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:04:47.243 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:04:47.244 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:04:47.244 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:47.244 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:47.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:47.244 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:04:47.244 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:47.244 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:04:47.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:47.247 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:04:47.247 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:04:47.247 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:47.247 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:47.248 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:47.248 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:04:47.248 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:47.248 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:04:47.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:47.250 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:04:47.250 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:04:47.250 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:47.250 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:47.250 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:47.251 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:04:47.251 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:47.251 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:04:47.251 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:47.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:47.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:47.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:47.255 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:04:47.255 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:04:47.255 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:04:47.255 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:04:47.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:47.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:47.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:47.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:04:47.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:47.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:47.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:47.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:47.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:47.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:47.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:47.260 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:04:47.743 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:04:47.790 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:04:47.792 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:04:47.794 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:04:47.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:04:47.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:04:47.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:04:47.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:04:47.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:04:47.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:04:47.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:04:47.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:47.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:47.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:47.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:47.839 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:47.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:47.840 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:47.840 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:47.840 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:47.840 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:47.840 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:04:52.842 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:52.843 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:52.844 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:52.845 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:52.846 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:52.846 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:52.857 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:52.858 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:52.858 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:52.858 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:52.858 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:04:52.860 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:04:52.860 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:04:52.860 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:52.860 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:52.861 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:52.861 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:04:52.861 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:52.861 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:04:52.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:52.863 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:04:52.863 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:04:52.863 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:52.863 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:52.863 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:52.863 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:04:52.863 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:52.863 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:04:52.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:52.865 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:04:52.865 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:04:52.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:52.865 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:52.866 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:52.866 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:04:52.866 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:52.866 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:04:52.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:52.868 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:04:52.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:04:52.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:04:52.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:04:52.868 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:04:52.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:04:52.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:04:52.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:04:52.869 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:04:52.869 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:04:52.869 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:52.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:52.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:52.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:52.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:52.874 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:04:53.356 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:04:53.397 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:04:53.398 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:04:53.399 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:04:53.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:04:53.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:04:53.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:04:53.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:04:53.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:04:53.425 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:04:53.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:04:53.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:53.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:53.429 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:53.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:53.430 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:53.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:53.430 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:53.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:53.430 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:53.430 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:53.430 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:04:58.433 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:04:58.433 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:04:58.436 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:58.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:58.436 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:58.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:58.443 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:04:58.445 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:58.445 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:58.446 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:04:58.446 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:04:58.450 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:04:58.450 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:04:58.451 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:58.451 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:58.451 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:04:58.452 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:04:58.452 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:04:58.453 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:04:58.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:58.453 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:04:58.454 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:04:58.454 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:58.454 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:58.454 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:04:58.455 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:04:58.455 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:04:58.455 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:04:58.455 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:58.456 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:04:58.456 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:04:58.457 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:58.457 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:04:58.457 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:04:58.457 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:04:58.457 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:04:58.457 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:04:58.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:58.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:04:58.461 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:04:58.461 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:04:58.461 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:58.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:58.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:58.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:58.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:58.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:58.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:58.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:04:58.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:58.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:04:58.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:04:58.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:58.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:58.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:58.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:04:58.466 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:04:58.950 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:04:58.995 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:04:58.998 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:04:58.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:04:59.000 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:04:59.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:04:59.007 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:04:59.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:04:59.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:04:59.007 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:04:59.008 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:04:59.008 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:04:59.008 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:04:59.427 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:04:59.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:04:59.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:04:59.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:04:59.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:04:59.904 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:05:00.382 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:05:00.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:00.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:00.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:00.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:00.860 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:05:01.337 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:05:01.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:01.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:01.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:01.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:01.815 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:05:02.292 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:05:02.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:02.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:02.468 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:02.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:02.770 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:05:03.247 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:05:03.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:03.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:03.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:03.474 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:03.724 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:05:04.202 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:05:04.680 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:05:05.157 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:05:05.634 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:05:06.112 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:05:06.590 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:05:07.067 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:05:07.544 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:05:08.022 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:05:08.499 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:05:08.976 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:05:09.454 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:05:09.932 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:05:10.410 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:05:10.887 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:05:11.365 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:05:11.843 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:05:12.321 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:05:12.799 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:05:13.276 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:05:13.754 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:05:14.232 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:05:14.709 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:05:15.187 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:05:15.665 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:05:16.142 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:05:16.620 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:05:17.097 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:05:17.575 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:05:18.051 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:05:18.528 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:05:19.007 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:05:19.484 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:05:19.962 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:05:20.439 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:05:20.917 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:05:21.394 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:05:21.872 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:05:22.350 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:05:22.828 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:05:23.305 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:05:23.782 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:05:24.259 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:05:24.737 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:05:25.215 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 03:05:25.692 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 03:05:26.170 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 03:05:26.646 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 03:05:27.124 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 03:05:27.602 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 03:05:28.080 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 03:05:28.557 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 03:05:29.035 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 03:05:29.513 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 03:05:29.991 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 03:05:30.468 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 03:05:30.946 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 03:05:31.424 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 03:05:31.901 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 03:05:32.378 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 03:05:32.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:05:32.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:05:32.487 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:32.487 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:32.487 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:32.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:32.488 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:05:32.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:05:32.488 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:05:32.488 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:05:32.488 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:05:32.488 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:05:32.488 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:05:37.495 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:05:37.495 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:05:37.495 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:05:37.495 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:05:37.495 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:05:37.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:05:37.503 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:05:37.505 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:05:37.505 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:05:37.506 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:05:37.506 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:05:37.509 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:05:37.510 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:05:37.510 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:05:37.511 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:05:37.511 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:05:37.511 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:05:37.512 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:05:37.512 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:05:37.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:37.513 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:05:37.513 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:05:37.514 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:05:37.514 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:05:37.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:05:37.515 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:05:37.515 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:05:37.515 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:05:37.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:37.516 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:05:37.516 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:05:37.516 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:05:37.516 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:05:37.516 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:05:37.516 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:05:37.517 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:05:37.517 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:05:37.517 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:37.519 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:37.520 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:05:37.520 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:05:37.520 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:05:37.521 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:37.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:37.522 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:37.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:37.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:37.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:37.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:37.525 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:05:38.009 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:05:38.050 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:05:38.052 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:05:38.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:05:38.055 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:05:38.477 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:05:38.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:38.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:38.524 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:38.529 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:38.947 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:05:39.421 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:05:39.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:39.525 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:39.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:39.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:39.899 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:05:40.373 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:05:40.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:40.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:40.527 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:40.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:40.851 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:05:41.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:05:41.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:41.081 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:41.082 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:41.082 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:41.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:05:41.083 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:05:41.083 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:05:41.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:05:41.083 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:05:41.083 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:05:41.083 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:05:41.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=766 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:05:41.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=766 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:05:41.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=766 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:05:41.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=766 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:05:41.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=766 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:05:41.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=766 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:05:46.084 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:05:46.084 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:05:46.085 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:05:46.086 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:05:46.086 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:05:46.087 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:05:46.092 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:05:46.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:05:46.094 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:05:46.094 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:05:46.094 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:05:46.097 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:05:46.098 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:05:46.098 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:05:46.098 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:05:46.099 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:05:46.099 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:05:46.099 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:05:46.099 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:05:46.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:46.101 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:05:46.101 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:05:46.101 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:05:46.101 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:05:46.101 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:05:46.101 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:05:46.102 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:05:46.102 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:05:46.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:46.103 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:05:46.103 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:05:46.103 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:05:46.103 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:05:46.103 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:05:46.104 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:05:46.104 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:05:46.104 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:05:46.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:46.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:05:46.107 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:05:46.107 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:05:46.107 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:46.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:46.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:46.111 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:05:46.594 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:05:46.633 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:05:46.635 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:05:46.635 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:05:46.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:05:47.072 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:05:47.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:47.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:47.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:47.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:47.552 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:05:48.032 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:05:48.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:48.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:48.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:48.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:48.513 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:05:48.993 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:05:49.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:49.112 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:49.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:49.114 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:49.474 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:05:49.955 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:05:50.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:50.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:50.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:50.115 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:50.436 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:05:50.918 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:05:51.114 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:51.114 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:51.115 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:51.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:51.399 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:05:51.877 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:05:52.356 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:05:52.647 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:52.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:52.647 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:52.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:52.648 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:05:52.648 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:05:52.648 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:05:52.648 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:05:52.649 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:05:52.649 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:05:52.649 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:05:52.649 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1391 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:05:52.649 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1391 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:05:52.649 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1391 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:05:52.649 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1391 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:05:52.649 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1391 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:05:52.649 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1391 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:05:57.655 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:05:57.655 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:05:57.655 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:05:57.655 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:05:57.655 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:05:57.655 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:05:57.664 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:05:57.666 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:05:57.666 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:05:57.667 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:05:57.667 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:05:57.671 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:05:57.671 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:05:57.671 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:05:57.671 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:05:57.672 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:05:57.672 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:05:57.672 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:05:57.672 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:05:57.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:57.675 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:05:57.675 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:05:57.675 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:05:57.675 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:05:57.676 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:05:57.676 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:05:57.677 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:05:57.677 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:05:57.677 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:57.678 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:05:57.678 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:05:57.678 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:05:57.678 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:05:57.679 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:05:57.679 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:05:57.679 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:05:57.679 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:05:57.679 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:57.683 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:05:57.683 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:05:57.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:05:57.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:57.684 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:57.684 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:57.684 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:05:57.684 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:05:57.684 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:05:57.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:57.684 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:57.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:57.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:57.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:57.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:57.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:57.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:57.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:57.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:05:57.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:05:57.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:57.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:05:57.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:57.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:57.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:57.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:05:57.689 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:05:58.173 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:05:58.221 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:05:58.223 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:05:58.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:05:58.227 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:05:58.645 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:05:58.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:58.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:58.690 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:58.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:05:59.117 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:05:59.595 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:05:59.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:05:59.709 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:05:59.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:05:59.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:00.076 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:06:00.557 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:06:00.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:00.711 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:00.711 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:00.711 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:01.037 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:06:01.518 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:06:01.711 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:01.712 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:01.712 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:01.712 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:01.999 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:06:02.479 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:06:02.712 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:02.713 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:02.713 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:02.713 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:02.957 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:06:03.435 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:06:03.914 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:06:04.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:04.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:04.243 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:04.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:04.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:04.245 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:04.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:04.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:04.245 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:06:04.245 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:06:04.245 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:06:09.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:06:09.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:06:09.248 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:09.249 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:09.250 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:09.250 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:09.259 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:09.260 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:06:09.260 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:09.261 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:06:09.261 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:06:09.263 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:06:09.264 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:06:09.264 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:06:09.264 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:09.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:09.265 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:06:09.266 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:06:09.266 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:06:09.266 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:09.267 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:06:09.267 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:06:09.267 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:06:09.267 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:09.267 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:09.267 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:06:09.267 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:06:09.267 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:06:09.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:09.269 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:06:09.269 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:06:09.269 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:06:09.269 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:09.269 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:09.270 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:06:09.270 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:06:09.270 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:06:09.270 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:09.272 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:06:09.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:09.273 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:06:09.273 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:06:09.273 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:06:09.273 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:09.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:09.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:09.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:09.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:09.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:09.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:09.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:09.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:09.278 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:06:09.761 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:06:09.806 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:06:09.808 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:06:09.810 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:06:09.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:06:10.242 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:06:10.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:10.277 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:10.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:10.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:10.722 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:06:11.203 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:06:11.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:11.278 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:11.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:11.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:11.684 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:06:12.160 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:06:12.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:12.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:12.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:12.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:12.638 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:06:13.116 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:06:13.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:13.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:13.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:13.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:13.597 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:06:14.076 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:06:14.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:14.283 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:14.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:14.288 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:14.554 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:06:15.035 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:06:15.513 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:06:15.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:15.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:15.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:15.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:15.828 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:15.828 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:15.828 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:06:15.828 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:06:15.828 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:06:15.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:15.828 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1395 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1395 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1395 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1395 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1395 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1395 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1395 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:15.828 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1396 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:20.829 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:06:20.829 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:06:20.830 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:20.832 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:20.833 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:20.833 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:20.842 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:20.843 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:06:20.843 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:20.843 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:06:20.844 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:06:20.848 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:06:20.849 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:06:20.849 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:06:20.849 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:20.850 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:20.850 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:06:20.850 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:06:20.851 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:06:20.851 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:20.851 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:06:20.852 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:06:20.852 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:06:20.852 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:20.852 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:20.852 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:06:20.852 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:06:20.852 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:06:20.852 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:20.854 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:06:20.854 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:06:20.854 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:06:20.854 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:20.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:20.855 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:06:20.855 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:06:20.855 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:06:20.855 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:20.857 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:06:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:06:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:06:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:06:20.857 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:06:20.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:06:20.858 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:06:20.858 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:06:20.858 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:20.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:20.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:20.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:20.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:20.863 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:06:21.347 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:06:21.386 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:06:21.389 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:06:21.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:06:21.392 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:06:21.828 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:06:21.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:21.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:21.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:21.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:22.308 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:06:22.786 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:06:22.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:22.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:22.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:22.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:23.267 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:06:23.746 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:06:23.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:23.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:23.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:23.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:24.227 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:06:24.708 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:06:24.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:24.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:24.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:24.867 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:25.187 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:06:25.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:06:25.666 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:06:25.867 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:25.867 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:25.867 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:25.869 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:26.144 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:06:26.622 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:06:27.103 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:06:27.584 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:06:28.062 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:06:28.543 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:06:29.025 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:06:29.420 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:29.421 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:29.421 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:29.421 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:29.421 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:29.422 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:29.422 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:29.422 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:29.422 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:06:29.422 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:06:29.422 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:06:34.426 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:06:34.426 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:06:34.426 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:34.426 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:34.426 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:34.426 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:34.433 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:34.433 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:06:34.434 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:34.434 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:06:34.434 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:06:34.437 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:06:34.437 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:06:34.437 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:06:34.437 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:34.437 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:34.437 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:06:34.438 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:06:34.438 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:06:34.438 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:34.440 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:06:34.441 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:06:34.441 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:06:34.441 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:34.441 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:34.442 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:06:34.442 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:06:34.442 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:06:34.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:34.444 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:06:34.444 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:06:34.444 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:06:34.444 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:34.445 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:34.445 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:06:34.445 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:06:34.445 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:06:34.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:34.447 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:06:34.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:06:34.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:34.448 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:06:34.449 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:06:34.449 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:06:34.449 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:06:34.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:34.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:34.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:34.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:06:34.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:34.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:34.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:34.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:34.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:34.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:34.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:34.453 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:06:34.938 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:06:34.978 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:06:34.979 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:06:34.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:06:34.981 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:06:35.417 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:06:35.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:35.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:35.460 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:35.460 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:35.894 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:06:36.375 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:06:36.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:36.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:36.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:36.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:36.856 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:06:37.337 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:06:37.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:37.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:37.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:37.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:37.815 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:06:38.293 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:06:38.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:38.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:38.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:38.464 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:38.770 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:06:38.993 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:38.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:38.993 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:38.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:38.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:38.994 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:38.994 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:38.994 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:38.994 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:06:38.994 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:06:38.994 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:06:38.994 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=968 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:38.994 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=968 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:38.994 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=968 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:38.995 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=968 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:38.995 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=968 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:38.995 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=968 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:43.997 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:06:43.997 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:06:43.999 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:44.000 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:44.001 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:44.001 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:44.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:44.011 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:06:44.011 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:44.011 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:06:44.011 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:06:44.015 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:06:44.015 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:06:44.016 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:06:44.016 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:44.016 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:44.016 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:06:44.017 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:06:44.017 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:06:44.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:44.018 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:06:44.018 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:06:44.018 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:06:44.018 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:44.018 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:44.018 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:06:44.018 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:06:44.018 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:06:44.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:44.020 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:06:44.020 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:06:44.020 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:06:44.020 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:44.020 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:44.020 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:06:44.021 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:06:44.021 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:06:44.021 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:44.023 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:06:44.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:06:44.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:06:44.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:06:44.023 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:06:44.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:06:44.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:06:44.023 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:06:44.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:06:44.023 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:44.023 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:06:44.024 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:06:44.024 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:06:44.024 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:44.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:44.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:44.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:44.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:44.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:44.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:44.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:44.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:44.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:44.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:44.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:44.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:44.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:44.029 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:06:44.512 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:06:44.552 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:06:44.554 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:06:44.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:06:44.557 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:06:44.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:44.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:44.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:44.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:44.570 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:44.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:44.570 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:44.570 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:44.571 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:06:44.571 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:06:44.571 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:06:44.571 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:44.571 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:44.571 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:44.571 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:44.572 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:44.572 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:49.570 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:06:49.570 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:06:49.571 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:49.573 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:49.574 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:49.574 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:49.582 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:49.584 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:06:49.584 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:49.584 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:06:49.584 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:06:49.588 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:06:49.588 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:06:49.588 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:06:49.589 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:49.589 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:49.589 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:06:49.590 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:06:49.590 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:06:49.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:49.591 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:06:49.591 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:06:49.591 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:06:49.591 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:49.591 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:49.592 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:06:49.592 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:06:49.592 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:06:49.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:49.593 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:06:49.593 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:06:49.593 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:06:49.593 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:49.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:49.594 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:06:49.594 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:06:49.594 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:06:49.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:49.596 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:06:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:06:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:06:49.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:06:49.596 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:06:49.597 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:06:49.597 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:06:49.597 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:06:49.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:49.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:49.602 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:06:50.086 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:06:50.124 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:06:50.126 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:06:50.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:06:50.128 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:06:50.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:06:50.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:50.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:50.145 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:50.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:50.145 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:50.145 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:50.145 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:50.145 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:50.145 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:06:50.145 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:06:50.145 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:06:50.145 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:50.145 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:50.145 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:55.147 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:06:55.147 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:06:55.149 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:55.149 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:55.149 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:55.150 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:55.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:55.153 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:06:55.153 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:55.153 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:06:55.153 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:06:55.154 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:06:55.154 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:06:55.154 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:06:55.154 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:55.154 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:55.155 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:06:55.155 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:06:55.155 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:06:55.155 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:55.155 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:06:55.155 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:06:55.155 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:06:55.155 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:55.155 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:55.155 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:06:55.155 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:06:55.155 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:06:55.155 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:55.156 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:06:55.156 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:06:55.156 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:06:55.156 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:06:55.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:55.157 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:06:55.157 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:06:55.157 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:06:55.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:55.158 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:06:55.158 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:06:55.158 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:06:55.158 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:06:55.158 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:06:55.158 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:06:55.158 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:06:55.158 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:06:55.159 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:06:55.159 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:06:55.159 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:55.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:06:55.160 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:06:55.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:55.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:55.160 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:06:55.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:55.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:55.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:55.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:06:55.164 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:06:55.647 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:06:55.686 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:06:55.688 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:06:55.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:06:55.690 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:06:55.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:06:55.704 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:06:55.705 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:06:55.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:06:55.708 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:06:55.708 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:06:55.708 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:06:55.708 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:06:55.708 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:06:55.709 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:06:55.709 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:06:55.709 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:55.709 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:55.709 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:55.709 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:55.709 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:06:55.709 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:00.707 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:07:00.707 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:07:00.708 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:00.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:00.711 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:00.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:00.720 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:00.721 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:07:00.721 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:00.722 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:07:00.722 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:07:00.728 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:07:00.728 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:07:00.729 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:07:00.729 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:00.729 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:00.730 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:07:00.730 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:07:00.730 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:07:00.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:00.732 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:07:00.732 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:07:00.732 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:07:00.733 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:00.733 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:00.733 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:07:00.733 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:07:00.733 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:07:00.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:00.735 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:07:00.735 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:07:00.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:07:00.735 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:00.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:00.735 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:07:00.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:07:00.735 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:07:00.736 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:00.738 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:00.739 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:07:00.739 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:07:00.739 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:07:00.740 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:07:00.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:00.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:00.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:00.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:07:00.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:00.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:00.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:00.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:00.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:00.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:00.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:00.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:00.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:00.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:00.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:00.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:00.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:00.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:00.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:00.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:00.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:00.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:00.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:00.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:00.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:00.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:00.744 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:07:01.229 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:07:01.269 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:07:01.270 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:07:01.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:07:01.271 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:07:01.279 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:07:01.279 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:07:01.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:07:01.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:01.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:07:01.279 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:07:01.279 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:07:01.279 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:07:01.706 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:07:01.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:01.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:01.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:01.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:02.184 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:07:02.661 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:07:02.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:02.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:02.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:02.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:03.139 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:07:03.617 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:07:03.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:03.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:03.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:03.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:04.094 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:07:04.337 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:07:04.338 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-05 03:07:04.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:04.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:04.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:07:04.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:07:04.383 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:07:04.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:07:04.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:04.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:04.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:04.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:04.389 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:04.389 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:04.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:04.389 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:04.389 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:07:04.389 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:07:04.389 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:07:04.390 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=779 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:04.390 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=779 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:04.390 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=779 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:04.390 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=779 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:04.390 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=779 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:04.390 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=779 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:04.390 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=779 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:09.391 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:07:09.392 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:07:09.393 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:09.395 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:09.396 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:09.396 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:09.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:09.403 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:07:09.403 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:09.403 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:07:09.403 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:07:09.405 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:07:09.405 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:07:09.405 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:07:09.406 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:09.406 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:09.406 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:07:09.406 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:07:09.407 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:07:09.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:09.408 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:07:09.408 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:07:09.408 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:07:09.408 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:09.408 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:09.408 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:07:09.408 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:07:09.408 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:07:09.409 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:09.410 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:07:09.410 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:07:09.410 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:07:09.410 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:09.410 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:09.410 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:07:09.410 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:07:09.410 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:07:09.410 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:09.413 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:07:09.413 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:07:09.413 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:07:09.414 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:09.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:09.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:09.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:09.418 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:07:09.901 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:07:09.947 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:07:09.950 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:07:09.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:07:09.952 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:07:09.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:07:09.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:07:09.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:07:09.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:09.963 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:07:09.963 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:07:09.963 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:07:09.963 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:07:10.380 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:07:10.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:10.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:10.418 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:10.422 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:10.857 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:07:11.335 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:07:11.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:11.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:11.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:11.423 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:11.813 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:07:12.291 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:07:12.419 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:12.419 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:12.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:12.424 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:12.768 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:07:13.011 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:07:13.011 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-05 03:07:13.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:13.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:13.246 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:07:13.420 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:13.420 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:13.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:13.425 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:13.724 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:07:13.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:07:13.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:07:13.736 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:07:13.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:07:13.742 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:13.743 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:13.743 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:13.743 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:13.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:13.746 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:13.746 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:13.747 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:07:13.747 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:07:13.747 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:07:13.747 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:13.747 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=924 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:13.747 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=924 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:13.748 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=924 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:13.748 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=924 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:13.748 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=924 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:13.748 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=924 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:13.748 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=924 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:18.746 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:07:18.746 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:07:18.748 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:18.749 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:18.750 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:18.750 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:18.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:18.760 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:07:18.760 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:18.760 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:07:18.760 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:07:18.763 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:07:18.764 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:07:18.764 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:07:18.764 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:18.765 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:18.765 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:07:18.765 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:07:18.766 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:07:18.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:18.766 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:07:18.767 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:07:18.767 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:07:18.767 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:18.768 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:18.768 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:07:18.768 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:07:18.768 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:07:18.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:18.769 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:07:18.769 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:07:18.769 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:07:18.769 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:18.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:18.769 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:07:18.769 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:07:18.769 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:07:18.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:07:18.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:07:18.773 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:07:18.773 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:07:18.773 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:18.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:18.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:18.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:18.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:18.774 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:18.774 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:18.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:18.774 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:18.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:18.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:18.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:18.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:18.778 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:07:19.260 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:07:19.305 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:07:19.307 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:07:19.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:07:19.310 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:07:19.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:07:19.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:07:19.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:07:19.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:19.319 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:07:19.319 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:07:19.319 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:07:19.319 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:07:19.737 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:07:19.775 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:19.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:19.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:19.779 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:20.214 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:07:20.692 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:07:20.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:20.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:20.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:20.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:21.170 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:07:21.648 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:07:21.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:21.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:21.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:21.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:22.123 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:07:22.361 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:07:22.361 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-05 03:07:22.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:22.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:22.601 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:07:22.779 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:22.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:22.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:22.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:23.074 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:07:23.543 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:07:23.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:23.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:23.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:23.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:24.020 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:07:24.498 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:07:24.976 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:07:25.454 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:07:25.926 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:07:26.403 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:07:26.882 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:07:27.360 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:07:27.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:07:27.364 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:07:27.364 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:07:27.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:07:27.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:27.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:27.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:27.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:27.384 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:27.384 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:27.385 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:27.385 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:07:27.385 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:07:27.385 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:07:27.385 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:27.385 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1843 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:32.384 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:07:32.385 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:07:32.386 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:32.387 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:32.387 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:32.388 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:32.395 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:32.395 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:07:32.396 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:32.396 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:07:32.396 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:07:32.398 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:07:32.398 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:07:32.399 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:07:32.399 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:32.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:32.400 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:07:32.400 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:07:32.400 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:07:32.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:32.401 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:07:32.401 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:07:32.401 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:07:32.401 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:32.401 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:32.401 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:07:32.401 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:07:32.401 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:07:32.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:32.403 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:07:32.403 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:07:32.403 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:07:32.403 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:32.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:32.403 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:07:32.403 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:07:32.403 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:07:32.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:07:32.406 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:07:32.406 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:07:32.406 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:32.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:32.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:32.411 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:07:32.895 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:07:32.936 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:07:32.939 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:07:32.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:07:32.941 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:07:32.949 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:07:32.949 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:07:32.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:07:32.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:32.950 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:07:32.950 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:07:32.950 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:07:32.950 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:07:33.372 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:07:33.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:33.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:33.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:33.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:33.850 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:07:34.328 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:07:34.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:34.411 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:34.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:34.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:34.806 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:07:35.282 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:07:35.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:35.411 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:35.412 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:35.415 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:35.760 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:07:36.002 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:07:36.002 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-05 03:07:36.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:36.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:36.238 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:07:36.412 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:36.413 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:36.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:36.416 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:36.716 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:07:37.194 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:07:37.413 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:37.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:37.413 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:37.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:37.672 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:07:38.150 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:07:38.624 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:07:39.093 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:07:39.570 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:07:40.048 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:07:40.527 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:07:41.004 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:07:41.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:07:41.006 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:07:41.006 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:07:41.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:07:41.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:41.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:41.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:41.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:41.025 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:41.025 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:41.025 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:41.025 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:41.025 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:07:41.025 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:07:41.025 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:07:41.025 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:41.025 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:41.025 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:41.025 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:41.025 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:41.025 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:41.025 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1842 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:07:46.025 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:07:46.025 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:07:46.026 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:46.028 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:46.029 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:46.029 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:46.037 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:46.038 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:07:46.038 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:46.038 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:07:46.039 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:07:46.041 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:07:46.041 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:07:46.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:07:46.042 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:46.042 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:46.042 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:07:46.043 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:07:46.043 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:07:46.043 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:46.043 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:07:46.043 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:07:46.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:07:46.044 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:46.044 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:46.044 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:07:46.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:07:46.044 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:07:46.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:46.045 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:07:46.045 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:07:46.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:07:46.046 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:46.046 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:46.046 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:07:46.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:07:46.046 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:07:46.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:46.048 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:07:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:07:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:07:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:07:46.048 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:07:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:07:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:07:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:07:46.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:07:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:46.048 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:07:46.049 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:07:46.049 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:07:46.049 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:46.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:46.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:46.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:46.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:46.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:46.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:46.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:46.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:46.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:46.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:46.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:46.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:46.054 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:07:46.536 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:07:46.575 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:07:46.577 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:07:46.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:07:46.579 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:07:46.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:07:46.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:07:46.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:07:46.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:46.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:07:46.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:07:46.588 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:07:46.588 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:07:47.013 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:07:47.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:47.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:47.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:47.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:47.491 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:07:47.969 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:07:48.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:48.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:48.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:48.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:48.446 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:07:48.924 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:07:49.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:49.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:49.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:49.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:49.402 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:07:49.645 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:07:49.645 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-05 03:07:49.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:49.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:07:49.880 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:07:50.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:50.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:50.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:50.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:50.358 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:07:50.836 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:07:51.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:51.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:51.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:51.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:51.315 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:07:51.793 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:07:52.271 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:07:52.749 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:07:53.227 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:07:53.705 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:07:54.183 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:07:54.648 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:07:54.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:07:54.648 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:07:54.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:07:54.661 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:07:54.663 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:54.663 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:54.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:54.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:54.666 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:54.666 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:54.666 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:54.666 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:54.666 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:07:54.666 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:07:54.666 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:07:59.666 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:07:59.666 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:07:59.670 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:59.670 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:59.670 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:59.670 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:59.679 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:07:59.680 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:07:59.681 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:59.681 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:07:59.682 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:07:59.686 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:07:59.686 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:07:59.686 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:07:59.686 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:59.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:07:59.687 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:07:59.687 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:07:59.687 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:07:59.687 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:07:59.690 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:07:59.690 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:07:59.690 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:07:59.690 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:59.691 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:07:59.691 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:07:59.691 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:07:59.691 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:07:59.691 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:07:59.692 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:07:59.693 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:07:59.693 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:07:59.693 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:07:59.693 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:07:59.693 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:07:59.693 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:07:59.693 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:07:59.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:07:59.696 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:07:59.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:07:59.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:07:59.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:07:59.696 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:07:59.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:07:59.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:07:59.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:07:59.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:59.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:07:59.697 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:07:59.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:59.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:59.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:59.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:07:59.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:59.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:59.697 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:07:59.698 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:07:59.698 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:07:59.698 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:59.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:07:59.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:59.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:59.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:59.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:59.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:59.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:59.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:59.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:07:59.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:07:59.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:07:59.703 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:08:00.187 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:08:00.228 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:08:00.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:08:00.231 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:08:00.234 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:08:00.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:00.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:00.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:08:00.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:08:00.244 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:08:00.244 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:08:00.244 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:08:00.244 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:08:00.278 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:08:00.278 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-05 03:08:00.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:08:00.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:08:00.665 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:08:00.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:00.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:00.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:00.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:01.144 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:08:01.622 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:08:01.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:01.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:01.704 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:01.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:02.100 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:08:02.578 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:08:02.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:02.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:02.704 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:02.708 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:03.056 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:08:03.534 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:08:03.703 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:03.703 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:03.705 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:03.709 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:04.012 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:08:04.490 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:08:04.705 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:04.705 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:04.705 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:04.710 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:04.967 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:08:05.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:05.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:05.280 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:08:05.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:05.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:05.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:05.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:05.291 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:05.292 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:05.292 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:05.292 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:05.292 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:08:05.292 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:08:05.292 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:08:05.292 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1194 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:05.292 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1194 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:05.292 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1194 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:05.292 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1194 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:05.292 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1194 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:05.292 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1194 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:05.292 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1194 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:10.294 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:08:10.294 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:08:10.297 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:10.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:10.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:10.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:10.305 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:10.307 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:08:10.307 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:10.307 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:08:10.307 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:08:10.310 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:08:10.311 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:08:10.311 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:08:10.311 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:10.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:10.312 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:08:10.313 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:08:10.313 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:08:10.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:10.313 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:08:10.314 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:08:10.314 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:08:10.314 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:10.314 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:10.315 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:08:10.315 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:08:10.315 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:08:10.315 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:10.316 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:08:10.316 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:08:10.316 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:08:10.317 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:10.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:10.317 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:08:10.317 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:08:10.317 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:08:10.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:10.319 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:08:10.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:10.320 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:08:10.320 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:08:10.320 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:08:10.320 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:10.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:10.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:10.325 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:08:10.810 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:08:10.856 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:08:10.859 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:08:10.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:08:10.861 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:08:10.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:10.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:10.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:08:10.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:08:10.867 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:08:10.867 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:08:10.868 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:08:10.868 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:08:11.287 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:08:11.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:11.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:11.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:11.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:11.765 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:08:12.242 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:08:12.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:12.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:12.328 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:12.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:12.720 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:08:13.198 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:08:13.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:13.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:13.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:13.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:13.675 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:08:13.917 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:08:13.917 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-05 03:08:13.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:08:13.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:08:14.152 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:08:14.328 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:14.328 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:14.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:14.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:14.630 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:08:15.108 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:08:15.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:15.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:15.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:15.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:15.586 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:08:15.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:15.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:15.920 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:08:15.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:08:15.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:15.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:15.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:15.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:15.932 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:15.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:15.932 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:15.932 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:15.932 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:08:15.932 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:08:15.932 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:08:15.932 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1198 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:15.932 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1198 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:15.932 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1198 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:15.932 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1198 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:15.932 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1198 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:15.932 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1198 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:15.932 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1198 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:20.934 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:08:20.934 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:08:20.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:20.937 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:20.937 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:20.937 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:20.945 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:20.945 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:08:20.945 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:20.946 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:08:20.946 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:08:20.948 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:08:20.948 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:08:20.949 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:08:20.949 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:20.949 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:20.950 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:08:20.950 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:08:20.950 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:08:20.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:20.951 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:08:20.951 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:08:20.951 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:08:20.951 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:20.951 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:20.952 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:08:20.952 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:08:20.952 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:08:20.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:20.954 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:08:20.954 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:08:20.954 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:08:20.954 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:20.954 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:20.954 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:08:20.954 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:08:20.954 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:08:20.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:20.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:08:20.958 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:08:20.958 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:08:20.958 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:20.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:20.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:20.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:20.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:20.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:20.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:20.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:20.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:20.962 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:08:21.446 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:08:21.486 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:08:21.488 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:08:21.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:08:21.491 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:08:21.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:21.498 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:21.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:08:21.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:08:21.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:08:21.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:08:21.500 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:08:21.500 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:08:21.924 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:08:21.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:21.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:21.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:21.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:22.401 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:08:22.879 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:08:22.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:22.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:22.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:22.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:23.356 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:08:23.833 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:08:23.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:23.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:23.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:23.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:24.310 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:08:24.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:24.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:24.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:08:24.613 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:24.614 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:24.614 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:24.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:24.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:24.615 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:24.615 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:24.615 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:24.615 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:08:24.615 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:08:24.615 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:08:24.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=781 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:24.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=781 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:24.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=781 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:24.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=781 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:24.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=781 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:24.615 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=781 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:29.617 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:08:29.617 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:08:29.618 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:29.620 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:29.620 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:29.620 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:29.630 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:29.632 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:08:29.632 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:29.632 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:08:29.633 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:08:29.637 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:08:29.637 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:08:29.637 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:08:29.637 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:29.637 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:29.637 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:08:29.638 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:08:29.638 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:08:29.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:29.640 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:08:29.640 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:08:29.640 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:08:29.640 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:29.640 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:29.640 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:08:29.641 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:08:29.641 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:08:29.641 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:29.643 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:08:29.643 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:08:29.643 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:08:29.643 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:29.643 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:29.643 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:08:29.643 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:08:29.643 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:08:29.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:29.646 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:08:29.646 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:08:29.646 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:08:29.647 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:29.647 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:29.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:29.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:29.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:29.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:29.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:29.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:29.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:29.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:29.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:29.651 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:08:30.135 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:08:30.171 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:08:30.172 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:08:30.173 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:08:30.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:08:30.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:30.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:30.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:08:30.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:08:30.177 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:08:30.177 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:08:30.177 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:08:30.177 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:08:30.613 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:08:30.650 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:30.650 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:30.651 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:30.655 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:31.090 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:08:31.568 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:08:31.650 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:31.651 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:31.652 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:31.655 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:32.046 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:08:32.524 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:08:32.651 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:32.652 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:32.653 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:32.656 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:33.002 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:08:33.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:33.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:33.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:08:33.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:33.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:33.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:33.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:33.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:33.327 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:33.327 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:33.328 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:08:33.328 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:08:33.328 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:08:33.328 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:33.328 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=786 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:33.328 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:33.328 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:33.329 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:33.329 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:33.329 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:33.329 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:38.326 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:08:38.327 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:08:38.328 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:38.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:38.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:38.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:38.334 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:38.334 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:08:38.334 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:38.334 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:08:38.334 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:08:38.335 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:08:38.335 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:08:38.335 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:08:38.335 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:38.335 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:38.335 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:08:38.335 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:08:38.335 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:08:38.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:38.336 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:08:38.336 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:08:38.336 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:08:38.336 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:38.336 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:38.336 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:08:38.336 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:08:38.336 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:08:38.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:38.337 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:08:38.337 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:08:38.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:08:38.337 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:38.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:38.337 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:08:38.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:08:38.337 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:08:38.337 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:08:38.339 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:08:38.339 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:08:38.339 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:08:38.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:38.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:38.344 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:08:38.827 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:08:38.866 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:08:38.867 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:08:38.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:08:38.869 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:08:38.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:38.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:38.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:08:38.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:08:38.875 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:08:38.875 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:08:38.875 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:08:38.875 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:08:39.143 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:39.143 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:39.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:39.149 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:39.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:39.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:39.152 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:39.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:39.152 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:39.152 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:39.152 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:08:39.152 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:08:39.152 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:08:39.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=173 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=173 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=173 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=173 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=173 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=173 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=173 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=174 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=174 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.153 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.153 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:39.153 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:44.153 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:08:44.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:08:44.154 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:44.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:44.157 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:44.157 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:44.165 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:44.167 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:08:44.167 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:44.167 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:08:44.167 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:08:44.170 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:08:44.171 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:08:44.171 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:08:44.171 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:44.171 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:44.171 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:08:44.171 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:08:44.171 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:08:44.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:44.174 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:08:44.174 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:08:44.174 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:08:44.174 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:44.174 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:44.174 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:08:44.174 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:08:44.175 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:08:44.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:44.176 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:08:44.177 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:08:44.177 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:08:44.177 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:44.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:44.177 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:08:44.177 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:08:44.177 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:08:44.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:44.180 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:08:44.180 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:08:44.180 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:08:44.181 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:44.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:44.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:44.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:44.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:44.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:44.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:44.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:44.185 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:08:44.669 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:08:44.701 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:08:44.702 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:08:44.703 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:08:44.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:08:44.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:44.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:44.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:08:44.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:08:44.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:08:44.709 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:08:44.709 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:08:44.709 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:08:44.750 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:44.750 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:44.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:44.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:44.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:44.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:44.759 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:44.759 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:44.760 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:44.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:44.760 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:08:44.760 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:08:44.760 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:08:44.760 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:44.760 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:44.761 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:44.761 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:44.761 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:44.761 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:49.758 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:08:49.758 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:08:49.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:49.761 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:49.762 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:49.762 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:49.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:49.772 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:08:49.772 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:49.773 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:08:49.773 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:08:49.776 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:08:49.776 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:08:49.777 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:08:49.777 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:49.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:49.777 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:08:49.778 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:08:49.778 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:08:49.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:49.779 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:08:49.779 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:08:49.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:08:49.779 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:49.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:49.779 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:08:49.780 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:08:49.780 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:08:49.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:49.781 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:08:49.781 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:08:49.781 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:08:49.781 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:08:49.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:49.781 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:08:49.782 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:08:49.782 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:08:49.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:49.784 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:08:49.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:49.785 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:08:49.785 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:08:49.785 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:08:49.786 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:08:49.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:49.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:49.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:49.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:08:49.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:49.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:49.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:49.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:49.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:49.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:49.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:49.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:49.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:49.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:49.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:49.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:49.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:49.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:49.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:49.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:49.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:08:49.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:08:49.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:08:49.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:49.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:49.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:49.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:08:49.790 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:08:50.274 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:08:50.318 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:08:50.319 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:08:50.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:08:50.321 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:08:50.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:50.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:50.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:08:50.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:08:50.327 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:08:50.327 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:08:50.327 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:08:50.327 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:08:50.752 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:08:50.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:50.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:50.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:50.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:51.229 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:08:51.707 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:08:51.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:51.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:51.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:51.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:52.184 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:08:52.662 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:08:52.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:52.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:52.795 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:52.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:53.140 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:08:53.618 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:08:53.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:53.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:53.796 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:53.797 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:54.096 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:08:54.574 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:08:54.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:54.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:54.797 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:54.797 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:55.052 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:08:55.529 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:08:56.007 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:08:56.484 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:08:56.962 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:08:57.440 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:08:57.918 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:08:58.390 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:08:58.867 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:08:59.221 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:08:59.221 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:08:59.226 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:08:59.226 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:08:59.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:08:59.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:08:59.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:08:59.227 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:08:59.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:08:59.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:08:59.227 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:08:59.227 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:08:59.227 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:08:59.227 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:59.227 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:59.227 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:59.227 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:59.227 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:08:59.227 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2018 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:04.230 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:09:04.230 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:09:04.235 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:04.235 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:04.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:04.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:04.250 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:04.250 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:09:04.251 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:04.251 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:09:04.251 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:09:04.253 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:09:04.254 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:09:04.254 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:09:04.254 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:04.254 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:04.255 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:09:04.255 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:09:04.255 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:09:04.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:04.256 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:09:04.256 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:09:04.257 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:09:04.257 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:04.257 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:04.257 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:09:04.257 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:09:04.257 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:09:04.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:04.259 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:09:04.259 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:09:04.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:09:04.259 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:04.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:04.259 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:09:04.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:09:04.259 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:09:04.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:04.261 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:09:04.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:09:04.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:09:04.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:09:04.261 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:09:04.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:09:04.262 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:09:04.262 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:09:04.262 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:04.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:04.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:04.267 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:09:04.750 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:09:04.797 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:09:04.799 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:09:04.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:09:04.801 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:09:04.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:09:04.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:09:04.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:09:04.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:09:04.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:09:04.811 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:09:04.811 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:09:04.811 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:09:05.228 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:09:05.265 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:05.266 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:05.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:05.271 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:05.706 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:09:06.184 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:09:06.267 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:06.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:06.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:06.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:06.662 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:09:07.140 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:09:07.267 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:07.268 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:07.268 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:07.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:07.618 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:09:08.095 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:09:08.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:08.269 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:08.269 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:08.274 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:08.572 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:09:09.050 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:09:09.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:09.270 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:09.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:09.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:09.528 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:09:10.006 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:09:10.484 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:09:10.962 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:09:11.439 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:09:11.917 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:09:12.395 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:09:12.872 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:09:13.350 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:09:13.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:09:13.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:09:13.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:13.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:13.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:13.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:13.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:13.697 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:13.697 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:13.697 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:13.697 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:09:13.697 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:09:13.697 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:09:13.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2015 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:13.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2015 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:13.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2015 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:13.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2015 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:13.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2015 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:13.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2015 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:13.698 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2015 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:18.699 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:09:18.699 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:09:18.700 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:18.703 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:18.703 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:18.703 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:18.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:18.711 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:09:18.711 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:18.711 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:09:18.711 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:09:18.714 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:09:18.714 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:09:18.714 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:09:18.714 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:18.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:18.714 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:09:18.714 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:09:18.714 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:09:18.714 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:18.716 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:09:18.717 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:09:18.717 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:09:18.717 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:18.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:18.717 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:09:18.717 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:09:18.717 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:09:18.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:18.719 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:09:18.719 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:09:18.720 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:09:18.720 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:18.720 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:18.720 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:09:18.720 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:09:18.720 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:09:18.720 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:18.722 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:09:18.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:09:18.723 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:09:18.723 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:09:18.723 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:09:18.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:18.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:18.728 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:09:19.213 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:09:19.258 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:09:19.260 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:09:19.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:09:19.263 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:09:19.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:09:19.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:09:19.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:09:19.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:09:19.272 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:09:19.272 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:09:19.272 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:09:19.272 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:09:19.690 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:09:19.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:19.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:19.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:19.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:20.168 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:09:20.645 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:09:20.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:20.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:20.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:20.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:21.122 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:09:21.600 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:09:21.729 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:21.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:21.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:21.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:22.078 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:09:22.320 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:09:22.320 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-05 03:09:22.321 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:09:22.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:09:22.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:09:22.555 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:09:22.730 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:22.730 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:22.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:22.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:23.033 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:09:23.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:09:23.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:09:23.354 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:09:23.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:09:23.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:23.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:23.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:23.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:23.358 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:23.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:23.359 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:23.359 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:23.359 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:09:23.359 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:09:23.359 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:09:23.359 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=990 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:23.359 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=990 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:23.359 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=990 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:23.359 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=990 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:23.359 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=990 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:23.359 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=990 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:28.359 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:09:28.359 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:09:28.361 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:28.362 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:28.363 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:28.363 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:28.371 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:28.372 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:09:28.373 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:28.373 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:09:28.373 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:09:28.376 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:09:28.377 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:09:28.377 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:09:28.377 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:28.377 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:28.378 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:09:28.378 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:09:28.378 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:09:28.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:28.379 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:09:28.379 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:09:28.379 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:09:28.379 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:28.380 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:28.380 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:09:28.380 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:09:28.380 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:09:28.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:28.382 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:09:28.382 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:09:28.382 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:09:28.382 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:28.382 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:28.382 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:09:28.382 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:09:28.382 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:09:28.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:28.384 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:09:28.385 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:09:28.385 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:09:28.385 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:09:28.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:28.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:28.390 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:09:28.875 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:09:28.916 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:09:28.917 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:09:28.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:09:28.919 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:09:29.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:29.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:29.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:29.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:29.114 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:29.114 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:29.114 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:29.114 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:09:29.114 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:09:29.114 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:09:29.115 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:34.115 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:09:34.115 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:09:34.117 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:34.117 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:34.118 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:34.119 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:34.122 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:34.122 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:09:34.122 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:34.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:09:34.123 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:09:34.125 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:09:34.125 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:09:34.125 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:09:34.125 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:34.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:34.126 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:09:34.126 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:09:34.126 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:09:34.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:34.127 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:09:34.128 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:09:34.128 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:09:34.128 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:34.128 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:34.128 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:09:34.128 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:09:34.128 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:09:34.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:34.129 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:09:34.129 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:09:34.129 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:09:34.129 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:34.129 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:34.130 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:09:34.130 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:09:34.130 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:09:34.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:34.131 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:09:34.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:09:34.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:09:34.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:09:34.131 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:09:34.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:09:34.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:09:34.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:09:34.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:09:34.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:34.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:09:34.132 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:09:34.132 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:09:34.132 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:34.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:34.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:34.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:34.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:34.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:34.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:34.137 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:09:34.620 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:09:34.659 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:09:34.661 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:09:34.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:09:34.662 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:09:35.098 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:09:35.134 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:35.134 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:35.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:35.137 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:35.577 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:09:36.058 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:09:36.136 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:36.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:36.136 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:36.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:36.535 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:09:37.017 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:09:37.137 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:37.137 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:37.137 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:37.140 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:37.498 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:09:37.979 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:09:38.138 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:38.138 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:38.139 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:38.141 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:38.455 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:09:38.924 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:09:39.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:39.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:39.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:39.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:39.393 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:09:39.869 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:09:40.347 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:09:40.826 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:09:41.305 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:09:41.783 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:09:42.285 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:09:42.763 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:09:43.242 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:09:43.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:09:43.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:43.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:43.688 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:43.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:43.688 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:43.688 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:43.688 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:43.688 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:09:43.688 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:09:43.688 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:09:43.688 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:48.690 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:09:48.690 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:09:48.692 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:48.693 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:48.693 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:48.693 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:48.701 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:48.702 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:09:48.702 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:48.703 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:09:48.703 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:09:48.705 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:09:48.705 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:09:48.706 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:09:48.706 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:48.706 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:48.707 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:09:48.707 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:09:48.707 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:09:48.707 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:48.708 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:09:48.708 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:09:48.708 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:09:48.708 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:48.709 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:48.709 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:09:48.709 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:09:48.709 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:09:48.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:48.710 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:09:48.711 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:09:48.711 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:09:48.711 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:09:48.711 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:48.711 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:09:48.711 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:09:48.711 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:09:48.711 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:48.714 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:09:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:09:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:09:48.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:09:48.714 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:48.715 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:09:48.715 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:09:48.715 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:09:48.715 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:48.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:48.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:48.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:48.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:48.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:09:48.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:48.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:09:48.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:09:48.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:48.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:48.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:48.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:09:48.720 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:09:49.196 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:09:49.243 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:09:49.244 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:09:49.245 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:09:49.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:09:49.665 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:09:49.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:49.720 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:49.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:49.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:50.134 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:09:50.603 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:09:50.720 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:50.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:50.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:50.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:51.072 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:09:51.549 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:09:51.720 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:51.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:51.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:51.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:52.024 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:09:52.492 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:09:52.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:52.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:52.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:52.730 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:52.962 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:09:53.438 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:09:53.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:53.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:53.726 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:53.731 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:53.906 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:09:54.380 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:09:54.855 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:09:55.326 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:09:55.793 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:09:56.261 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:09:56.730 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:09:57.198 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:09:57.666 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:09:58.134 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:09:58.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:09:58.284 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:09:58.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:09:58.284 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:09:58.284 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:09:58.285 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:09:58.285 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:09:58.285 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:09:58.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:09:58.285 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:09:58.285 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:09:58.285 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:09:58.285 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2075 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:58.285 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2075 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:58.285 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2075 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:58.285 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2075 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:58.285 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2075 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:58.285 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2075 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:09:58.285 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2075 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:03.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:03.288 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:03.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:03.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:03.292 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:03.293 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:03.316 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:03.316 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:03.316 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:03.316 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:03.316 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:10:03.317 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:10:03.317 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:10:03.317 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:03.317 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:03.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:03.317 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:10:03.317 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:03.317 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:10:03.317 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:03.318 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:10:03.318 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:10:03.318 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:03.318 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:03.318 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:10:03.318 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:03.318 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:10:03.318 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:03.318 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:03.320 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:10:03.320 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:10:03.320 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:03.320 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:03.320 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:03.320 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:10:03.320 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:03.320 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:10:03.320 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:10:03.323 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:10:03.323 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:10:03.323 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:03.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:03.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:03.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:03.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:03.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:03.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:03.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:03.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:03.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:03.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:03.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:03.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:03.328 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:10:03.805 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:10:03.836 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:10:03.836 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:10:03.837 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:10:03.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:10:04.274 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:10:04.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:04.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:04.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:04.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:04.743 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:10:05.212 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:10:05.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:05.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:05.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:05.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:05.689 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:10:06.165 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:10:06.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:06.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:06.328 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:06.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:06.633 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:10:06.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:10:06.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:06.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:06.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:06.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:06.876 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:06.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:06.877 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:06.877 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:06.877 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:06.877 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:06.877 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=768 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=769 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=769 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=769 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=769 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=769 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=769 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=769 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:06.877 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=769 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:11.876 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:11.876 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:11.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:11.878 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:11.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:11.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:11.886 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:11.886 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:11.886 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:11.886 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:11.886 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:10:11.888 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:10:11.888 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:10:11.888 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:11.889 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:11.889 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:11.889 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:10:11.889 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:11.889 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:10:11.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:11.890 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:10:11.890 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:10:11.890 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:11.890 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:11.891 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:11.891 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:10:11.891 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:11.891 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:10:11.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:11.892 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:10:11.892 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:10:11.892 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:11.892 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:11.892 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:11.892 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:10:11.893 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:11.893 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:10:11.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:10:11.895 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:10:11.895 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:10:11.895 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:10:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:11.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:11.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:11.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:11.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:11.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:11.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:11.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:11.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:11.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:11.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:11.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:11.900 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:10:12.377 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:10:12.430 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:10:12.432 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:10:12.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:10:12.434 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:10:12.453 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:10:12.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:10:12.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:10:12.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:10:12.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:10:12.466 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:10:12.466 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:10:12.466 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:10:12.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:10:12.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:10:12.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:10:12.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:10:12.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:10:12.851 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:10:12.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:10:12.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:10:12.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:10:12.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:10:12.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:12.868 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:12.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:12.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:12.870 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:12.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:12.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:12.870 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:12.870 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:12.870 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:12.870 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:10:17.870 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:17.870 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:17.874 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:17.874 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:17.874 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:17.874 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:17.883 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:17.884 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:17.885 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:17.885 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:17.885 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:10:17.889 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:10:17.889 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:10:17.890 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:17.890 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:17.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:17.891 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:10:17.891 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:17.891 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:10:17.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:17.892 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:10:17.893 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:10:17.893 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:17.893 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:17.894 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:17.894 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:10:17.894 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:17.894 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:10:17.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:17.895 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:10:17.896 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:10:17.896 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:17.896 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:17.896 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:17.896 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:10:17.896 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:17.896 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:10:17.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:17.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:17.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:17.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:17.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:17.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:17.900 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:10:17.900 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:10:17.900 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:10:17.900 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:10:17.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:17.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:17.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:17.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:10:17.900 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:17.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:17.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:17.900 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:17.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:17.905 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:10:18.388 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:10:18.425 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:10:18.427 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:10:18.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:10:18.428 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:10:18.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:18.439 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:18.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:18.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:18.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:18.442 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:18.442 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:18.442 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:18.442 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:18.442 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:10:18.443 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:18.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:18.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:18.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:18.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:18.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:18.443 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:18.444 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:18.444 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:23.441 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:23.442 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:23.443 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:23.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:23.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:23.445 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:23.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:23.452 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:23.452 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:23.452 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:23.453 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:10:23.455 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:10:23.455 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:10:23.455 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:23.455 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:23.455 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:23.455 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:10:23.455 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:23.455 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:10:23.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:23.458 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:10:23.458 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:10:23.458 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:23.458 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:23.459 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:23.459 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:10:23.459 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:23.459 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:10:23.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:23.461 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:10:23.461 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:10:23.462 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:23.462 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:23.462 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:23.462 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:10:23.462 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:23.462 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:10:23.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:23.465 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:10:23.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:10:23.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:10:23.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:10:23.465 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:10:23.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:10:23.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:10:23.466 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:10:23.466 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:10:23.466 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:10:23.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:23.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:23.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:23.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:23.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:23.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:23.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:23.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:23.471 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:10:23.955 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:10:23.999 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:10:24.003 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:10:24.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:10:24.005 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:10:24.433 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:10:24.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:24.471 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:24.473 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:24.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:24.911 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:10:25.392 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:10:25.471 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:25.472 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:25.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:25.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:25.874 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:10:26.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:26.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:26.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:26.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:26.023 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:26.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:26.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:26.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:26.023 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:26.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:26.023 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:10:26.023 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=543 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:26.023 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:26.023 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:26.023 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:26.023 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:26.023 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:26.023 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:26.023 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:26.023 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:31.025 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:31.025 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:31.026 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:31.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:31.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:31.028 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:31.034 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:31.034 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:31.034 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:31.034 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:31.034 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:10:31.035 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:10:31.035 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:10:31.035 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:31.035 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:31.035 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:31.035 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:10:31.035 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:31.035 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:10:31.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:31.035 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:10:31.035 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:10:31.036 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:31.036 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:31.036 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:31.036 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:10:31.036 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:31.036 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:10:31.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:31.036 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:10:31.036 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:10:31.036 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:31.036 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:31.036 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:31.036 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:10:31.036 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:31.036 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:10:31.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:10:31.038 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:10:31.038 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:10:31.038 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:31.038 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:31.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:31.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:31.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:31.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:31.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:31.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:31.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:31.043 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:10:31.526 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:10:31.566 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:10:31.568 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:10:31.571 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:10:31.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:10:31.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:10:31.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:10:31.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:10:31.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:10:31.571 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:10:31.571 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:10:31.571 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:10:31.571 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:10:32.004 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:10:32.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:32.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:32.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:32.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:32.481 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:10:32.958 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:10:33.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:33.042 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:33.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:33.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:33.436 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:10:33.914 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:10:34.042 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:34.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:34.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:34.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:34.391 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:10:34.410 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:10:34.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:10:34.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:34.415 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:34.416 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:34.416 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:34.416 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:34.417 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:34.417 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:34.417 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:34.417 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:34.417 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:34.417 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:10:34.417 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:34.417 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:34.417 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:34.417 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:34.417 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:34.417 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:39.419 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:39.419 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:39.421 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:39.423 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:39.423 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:39.423 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:39.433 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:39.435 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:39.435 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:39.435 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:39.435 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:10:39.439 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:10:39.439 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:10:39.440 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:39.440 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:39.440 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:39.441 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:10:39.441 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:39.441 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:10:39.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:39.442 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:10:39.442 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:10:39.443 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:39.443 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:39.443 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:39.443 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:10:39.443 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:39.443 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:10:39.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:39.445 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:10:39.445 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:10:39.445 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:39.445 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:39.445 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:39.445 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:10:39.445 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:39.445 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:10:39.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:39.448 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:10:39.448 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:10:39.448 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:10:39.449 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:39.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:39.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:39.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:39.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:39.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:39.453 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:10:39.937 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:10:39.982 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:10:39.985 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:10:39.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:10:39.988 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:10:39.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:10:39.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:10:39.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:10:39.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:10:39.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:10:39.992 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:10:39.992 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:10:39.992 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:10:40.414 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:10:40.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:40.452 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:40.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:40.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:40.892 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:10:41.369 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:10:41.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:41.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:41.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:41.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:41.847 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:10:42.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:10:42.102 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:10:42.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:42.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:42.106 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:42.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:42.108 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:42.108 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:42.108 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:42.108 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:42.108 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:10:42.108 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:42.108 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:42.108 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:42.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:42.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:42.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:42.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:42.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:42.109 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=568 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:47.109 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:47.109 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:47.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:47.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:47.113 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:47.113 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:47.120 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:47.120 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:47.120 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:47.120 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:47.120 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:10:47.121 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:10:47.121 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:10:47.121 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:47.121 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:47.121 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:47.121 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:10:47.121 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:47.121 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:10:47.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:47.121 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:10:47.121 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:10:47.121 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:47.121 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:47.121 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:47.121 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:10:47.122 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:47.122 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:10:47.122 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:47.122 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:10:47.122 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:10:47.122 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:47.122 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:47.122 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:47.122 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:10:47.122 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:47.122 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:10:47.122 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:47.123 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:10:47.123 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:10:47.123 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:10:47.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:10:47.124 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:10:47.124 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:10:47.124 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:47.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:47.129 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:10:47.612 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:10:47.647 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:10:47.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:10:47.650 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:10:47.652 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:10:47.657 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:10:47.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:10:47.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:10:47.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:10:47.660 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:10:47.660 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:10:47.661 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:10:47.661 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:10:48.090 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:10:48.126 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:48.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:48.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:48.131 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:48.568 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:10:49.045 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:10:49.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:49.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:49.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:49.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:49.523 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:10:50.000 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:10:50.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:50.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:50.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:50.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:50.478 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:10:50.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:10:50.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:10:50.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:50.501 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:50.501 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:50.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:50.502 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:50.502 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:50.502 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:50.502 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:50.502 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:50.502 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:10:50.502 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:50.502 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:50.502 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:50.502 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:50.502 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:50.502 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:50.502 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:50.502 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:50.502 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:55.504 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:55.505 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:55.506 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:55.507 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:55.507 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:55.507 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:55.517 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:55.518 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:55.518 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:55.519 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:10:55.519 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:10:55.523 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:10:55.524 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:10:55.524 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:55.525 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:55.525 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:55.525 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:10:55.526 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:10:55.526 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:10:55.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:55.527 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:10:55.527 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:10:55.528 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:55.528 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:55.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:55.529 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:10:55.529 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:10:55.529 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:10:55.529 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:55.530 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:10:55.530 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:10:55.530 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:55.530 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:10:55.530 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:55.530 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:10:55.530 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:10:55.530 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:10:55.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:55.533 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:10:55.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:10:55.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:10:55.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:10:55.533 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:10:55.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:10:55.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:10:55.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:10:55.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:10:55.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:10:55.534 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:10:55.534 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:10:55.534 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:55.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:55.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:10:55.539 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:10:56.022 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:10:56.066 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:10:56.068 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:10:56.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:10:56.070 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:10:56.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:10:56.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:10:56.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:10:56.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:10:56.075 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:10:56.075 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:10:56.075 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:10:56.075 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:10:56.499 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:10:56.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:56.537 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:56.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:56.543 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:56.977 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:10:57.454 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:10:57.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:57.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:57.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:57.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:57.932 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:10:58.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:10:58.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:10:58.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:10:58.194 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:10:58.194 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:10:58.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:10:58.197 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:10:58.197 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:10:58.197 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:10:58.197 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:10:58.198 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:10:58.198 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:10:58.198 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:10:58.198 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:58.198 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:58.198 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:58.198 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:58.198 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:10:58.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=569 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:03.195 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:03.195 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:03.196 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:03.198 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:03.199 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:03.199 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:03.207 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:03.207 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:03.207 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:03.207 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:03.207 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:11:03.209 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:11:03.209 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:11:03.210 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:03.210 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:03.210 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:03.211 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:11:03.211 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:03.211 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:11:03.211 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:03.212 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:11:03.212 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:11:03.212 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:03.212 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:03.212 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:03.212 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:11:03.212 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:03.212 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:11:03.212 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:03.214 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:11:03.214 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:11:03.214 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:03.214 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:03.214 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:03.214 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:11:03.214 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:03.214 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:11:03.214 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:03.217 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:11:03.217 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:11:03.217 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:11:03.217 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:03.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:03.222 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:11:03.705 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:11:03.740 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:11:03.741 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:11:03.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:03.742 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:11:03.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:11:03.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:11:03.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:11:03.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:11:03.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:11:03.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:11:03.747 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:11:03.747 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:11:04.183 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:11:04.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:04.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:04.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:04.225 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:04.660 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:11:05.137 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:11:05.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:05.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:05.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:05.225 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:05.616 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:11:06.093 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:11:06.221 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:06.222 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:06.222 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:06.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:06.571 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:11:07.048 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:11:07.223 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:07.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:07.223 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:07.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:07.526 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:11:07.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:11:07.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:11:07.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:07.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:07.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:07.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:07.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:07.551 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:07.551 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:07.551 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:07.551 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:07.551 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:07.551 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:11:12.554 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:12.554 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:12.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:12.557 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:12.558 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:12.558 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:12.566 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:12.568 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:12.568 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:12.568 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:12.568 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:11:12.572 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:11:12.572 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:11:12.572 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:12.573 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:12.573 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:12.573 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:11:12.574 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:12.574 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:11:12.574 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:12.575 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:11:12.575 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:11:12.575 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:12.575 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:12.575 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:12.576 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:11:12.576 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:12.576 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:11:12.576 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:12.577 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:11:12.577 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:11:12.577 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:12.577 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:12.577 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:12.577 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:11:12.578 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:12.578 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:11:12.578 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:12.580 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:11:12.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:11:12.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:11:12.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:11:12.580 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:11:12.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:11:12.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:11:12.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:11:12.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:11:12.581 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:11:12.581 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:11:12.581 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:12.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:12.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:12.586 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:11:13.069 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:11:13.110 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:11:13.113 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:11:13.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:13.115 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:11:13.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:11:13.123 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:11:13.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:11:13.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:11:13.124 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:11:13.125 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:11:13.125 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:11:13.125 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:11:13.546 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:11:13.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:13.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:13.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:13.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:14.024 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:11:14.502 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:11:14.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:14.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:14.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:14.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:14.979 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:11:15.457 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:11:15.585 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:15.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:15.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:15.590 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:15.934 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:11:16.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:11:16.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:11:16.195 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:16.195 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:16.195 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:16.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:16.198 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:16.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:16.198 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:16.198 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:16.198 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:16.199 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:11:16.199 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:16.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:16.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:16.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:16.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:16.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:16.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:16.199 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=773 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:21.198 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:21.198 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:21.199 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:21.201 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:21.201 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:21.201 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:21.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:21.214 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:21.214 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:21.215 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:21.215 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:11:21.218 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:11:21.218 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:11:21.219 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:21.219 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:21.219 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:21.220 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:11:21.220 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:21.220 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:11:21.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:21.221 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:11:21.221 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:11:21.221 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:21.221 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:21.221 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:21.221 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:11:21.221 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:21.221 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:11:21.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:21.223 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:11:21.223 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:11:21.223 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:21.223 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:21.223 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:21.224 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:11:21.224 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:21.224 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:11:21.224 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:21.226 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:11:21.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:11:21.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:11:21.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:11:21.226 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:11:21.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:11:21.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:11:21.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:11:21.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:11:21.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:21.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:11:21.227 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:11:21.227 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:11:21.227 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:21.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:21.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:21.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:21.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:21.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:21.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:21.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:21.232 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:11:21.717 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:11:21.754 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:11:21.756 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:11:21.757 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:11:21.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:22.194 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:11:22.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:22.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:22.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:22.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:22.672 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:11:23.150 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:11:23.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:23.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:23.231 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:23.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:23.623 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:11:23.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:23.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:23.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:23.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:23.772 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:23.772 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:23.772 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:23.772 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:23.773 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:23.773 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:23.773 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:11:23.773 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:23.773 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:23.773 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:23.773 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:23.773 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:23.773 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:23.773 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=544 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:28.774 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:28.774 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:28.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:28.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:28.777 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:28.777 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:28.784 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:28.785 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:28.785 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:28.785 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:28.785 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:11:28.788 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:11:28.788 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:11:28.788 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:28.789 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:28.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:28.789 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:11:28.790 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:28.790 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:11:28.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:28.791 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:11:28.791 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:11:28.791 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:28.791 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:28.792 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:28.792 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:11:28.792 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:28.792 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:11:28.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:28.793 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:11:28.793 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:11:28.793 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:28.793 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:28.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:28.794 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:11:28.794 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:28.794 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:11:28.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:28.796 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:11:28.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:11:28.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:11:28.797 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:11:28.797 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:11:28.797 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:11:28.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:28.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:28.802 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:11:29.287 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:11:29.321 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:11:29.321 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:11:29.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:29.323 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:11:29.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:11:29.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:11:29.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:11:29.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:29.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:29.766 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:11:29.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:29.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:29.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:29.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:30.244 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:11:30.722 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:11:30.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:30.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:30.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:30.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:31.199 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:11:31.668 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:11:31.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:31.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:31.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:31.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:32.138 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:11:32.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:32.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:32.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:32.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:32.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:32.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:32.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:32.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:32.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:32.403 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:32.403 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:32.403 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:11:37.406 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:37.406 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:37.407 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:37.408 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:37.408 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:37.409 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:37.412 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:37.412 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:37.412 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:37.412 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:37.412 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:11:37.413 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:11:37.413 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:11:37.413 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:37.413 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:37.413 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:37.413 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:11:37.413 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:37.413 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:11:37.413 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:37.414 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:11:37.414 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:11:37.414 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:37.414 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:37.414 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:37.414 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:11:37.414 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:37.414 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:11:37.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:37.415 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:11:37.415 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:11:37.416 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:37.416 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:37.416 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:37.416 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:11:37.416 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:37.416 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:11:37.416 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:37.417 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:11:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:11:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:11:37.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:11:37.418 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:11:37.418 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:11:37.418 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:37.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:37.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:37.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:37.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:37.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:37.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:37.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:37.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:37.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:37.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:37.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:37.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:37.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:37.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:37.423 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:11:37.907 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:11:37.940 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:11:37.942 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:11:37.943 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:11:37.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:37.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:11:37.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:11:37.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:11:37.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:37.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:37.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:37.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:37.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:37.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:37.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:37.984 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:37.984 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:37.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:37.984 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:37.984 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:37.984 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:11:37.984 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:37.984 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:37.984 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:37.984 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:37.984 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:37.984 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:37.984 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:37.984 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:37.985 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:42.984 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:42.984 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:42.985 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:42.987 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:42.988 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:42.988 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:42.997 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:42.998 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:42.998 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:42.999 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:42.999 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:11:43.002 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:11:43.002 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:11:43.003 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:43.003 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:43.003 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:43.004 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:11:43.004 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:43.004 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:11:43.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:43.005 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:11:43.005 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:11:43.006 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:43.006 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:43.006 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:43.006 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:11:43.006 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:43.006 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:11:43.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:43.008 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:11:43.008 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:11:43.008 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:43.008 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:43.008 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:43.008 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:11:43.009 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:43.009 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:11:43.009 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:11:43.013 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:11:43.013 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:11:43.013 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:11:43.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:43.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:43.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:43.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:43.018 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:11:43.502 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:11:43.546 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:11:43.548 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:11:43.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:43.551 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:11:43.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:11:43.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:11:43.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:11:43.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:43.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:43.983 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:11:44.016 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:44.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:44.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:44.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:44.461 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:11:44.939 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:11:45.017 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:45.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:45.021 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:45.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:45.417 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:11:45.895 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:11:46.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:46.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:46.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:46.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:46.376 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:11:46.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:46.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:46.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:46.608 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:46.608 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:46.608 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:46.609 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:46.609 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:46.609 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:46.609 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:46.609 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:46.609 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:11:46.609 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:46.609 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=766 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:46.609 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=766 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:46.609 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=766 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:46.609 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=766 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:46.609 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=766 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:51.610 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:51.610 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:51.612 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:51.613 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:51.615 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:51.617 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:51.625 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:51.627 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:51.627 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:51.627 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:51.627 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:11:51.629 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:11:51.630 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:11:51.630 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:51.630 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:51.631 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:51.631 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:11:51.631 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:51.631 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:11:51.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:51.632 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:11:51.632 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:11:51.632 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:51.632 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:51.632 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:51.632 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:11:51.632 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:51.632 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:11:51.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:51.634 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:11:51.634 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:11:51.634 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:51.634 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:51.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:51.634 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:11:51.634 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:51.634 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:11:51.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:51.636 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:11:51.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:11:51.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:11:51.637 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:11:51.637 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:11:51.637 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:11:51.637 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:51.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:51.642 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:11:52.126 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:11:52.165 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:11:52.167 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:11:52.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:52.169 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:11:52.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:11:52.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:11:52.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:11:52.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:52.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:52.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:52.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:52.221 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:52.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:52.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:52.221 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:52.223 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:52.223 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:52.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:52.223 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:52.223 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:52.223 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:52.224 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:11:52.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:52.224 [WARNING] transceiver.py:257 (TRX3@172.18.201.20:5700/3) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:52.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:52.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:52.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:52.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:52.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:52.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:57.225 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:57.225 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:57.226 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:57.228 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:57.229 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:57.229 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:57.236 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:57.237 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:57.237 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:57.237 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:11:57.237 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:11:57.240 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:11:57.240 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:11:57.240 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:57.240 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:57.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:57.240 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:11:57.241 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:11:57.241 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:11:57.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:57.243 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:11:57.243 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:11:57.243 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:57.243 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:57.243 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:57.243 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:11:57.243 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:11:57.243 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:11:57.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:57.245 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:11:57.245 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:11:57.245 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:57.246 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:11:57.246 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:57.246 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:11:57.246 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:11:57.246 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:11:57.246 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:57.248 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:11:57.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:11:57.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:11:57.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:11:57.248 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:11:57.249 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:11:57.249 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:11:57.249 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:57.249 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:57.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:11:57.254 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:11:57.738 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:11:57.777 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:11:57.779 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:11:57.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:11:57.782 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:11:57.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:11:57.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:11:57.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:11:57.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:11:57.797 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:11:57.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:11:57.797 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:11:57.797 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:11:57.797 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:11:57.797 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:11:57.797 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:11:57.797 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:57.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:57.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:57.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:57.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:57.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:11:57.798 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:02.797 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:02.797 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:02.799 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:02.800 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:02.801 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:02.801 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:02.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:02.811 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:02.811 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:02.812 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:02.812 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:12:02.815 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:12:02.816 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:12:02.816 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:02.816 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:02.817 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:02.817 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:12:02.817 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:02.817 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:12:02.818 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:02.818 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:12:02.818 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:12:02.819 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:02.819 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:02.819 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:02.819 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:12:02.819 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:02.819 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:12:02.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:02.821 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:12:02.821 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:12:02.821 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:02.821 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:02.821 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:02.821 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:12:02.821 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:02.821 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:12:02.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:02.824 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:12:02.824 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:12:02.824 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:12:02.824 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:02.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:02.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:02.829 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:12:03.312 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:12:03.352 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:12:03.354 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:12:03.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:03.356 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:12:03.368 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:03.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:03.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:03.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:03.370 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:03.370 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:03.370 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:03.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:03.370 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:03.371 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:03.371 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:12:03.371 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:03.371 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:03.371 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:03.371 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:03.371 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:03.371 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:08.370 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:08.370 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:08.373 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:08.373 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:08.373 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:08.373 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:08.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:08.380 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:08.380 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:08.380 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:08.380 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:12:08.381 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:12:08.381 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:12:08.381 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:08.381 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:08.381 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:08.381 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:12:08.381 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:08.381 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:12:08.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:08.383 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:12:08.383 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:12:08.383 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:08.383 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:08.383 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:08.383 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:12:08.383 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:08.383 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:12:08.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:08.384 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:12:08.384 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:12:08.384 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:08.384 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:08.384 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:08.384 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:12:08.384 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:08.384 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:12:08.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:12:08.386 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:12:08.386 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:12:08.386 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:08.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:08.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:08.391 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:12:08.875 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:12:08.910 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:12:08.913 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:12:08.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:08.915 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:12:08.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:08.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:08.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:08.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:08.930 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:08.930 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:08.930 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:08.930 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:08.930 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:08.930 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:12:08.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:08.930 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:08.930 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:08.930 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:08.930 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:08.930 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:08.930 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:08.930 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:08.930 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:13.932 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:13.932 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:13.934 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:13.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:13.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:13.939 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:13.954 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:13.956 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:13.956 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:13.956 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:13.957 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:12:13.960 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:12:13.961 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:12:13.961 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:13.961 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:13.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:13.962 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:12:13.962 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:13.963 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:12:13.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:13.963 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:12:13.963 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:12:13.963 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:13.964 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:13.964 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:13.964 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:12:13.964 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:13.964 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:12:13.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:13.966 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:12:13.966 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:12:13.966 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:13.966 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:13.966 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:13.966 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:12:13.966 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:13.966 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:12:13.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:13.969 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:12:13.969 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:12:13.969 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:12:13.970 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:13.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:13.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:13.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:13.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:13.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:13.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:13.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:13.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:13.974 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:12:14.460 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:12:14.497 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:12:14.500 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:12:14.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:14.502 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:12:14.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:14.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:14.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:14.515 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:14.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:14.519 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:14.519 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:14.519 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:14.519 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:14.520 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:14.520 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:12:14.520 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:14.520 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:14.520 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:14.520 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:14.520 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:14.521 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:19.521 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:19.521 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:19.521 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:19.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:19.521 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:19.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:19.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:19.528 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:19.528 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:19.528 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:19.528 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:12:19.531 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:12:19.531 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:12:19.531 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:19.531 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:19.532 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:19.532 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:12:19.532 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:19.532 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:12:19.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:19.535 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:12:19.535 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:12:19.535 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:19.535 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:19.535 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:19.535 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:12:19.535 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:19.535 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:12:19.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:19.538 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:12:19.538 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:12:19.538 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:19.538 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:19.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:19.538 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:12:19.539 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:19.539 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:12:19.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:19.542 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:12:19.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:12:19.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:12:19.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:12:19.542 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:12:19.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:12:19.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:12:19.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:12:19.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:12:19.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:19.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:19.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:19.543 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:12:19.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:19.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:19.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:19.543 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:19.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:19.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:19.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:19.543 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:12:19.543 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:12:19.543 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:12:19.543 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:12:19.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:19.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:19.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:19.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:19.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:19.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:19.548 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:12:20.031 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:12:20.076 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:12:20.078 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:12:20.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:20.080 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:12:20.509 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:12:20.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:20.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:20.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:20.551 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:20.988 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:12:21.468 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:12:21.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:21.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:21.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:21.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:21.947 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:12:22.428 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:12:22.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:22.549 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:22.549 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:22.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:22.908 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:12:23.110 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:12:23.111 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:12:23.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:12:23.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:12:23.112 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:12:23.113 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:12:23.113 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:12:23.113 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:12:23.387 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:12:23.549 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:23.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:23.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:23.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:23.864 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:12:24.342 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:12:24.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:24.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:24.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:24.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:24.820 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:12:25.297 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:12:25.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:12:25.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:12:25.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:25.427 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:25.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:25.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:25.427 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:25.430 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:25.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:25.430 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:25.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:25.430 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:25.430 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:25.430 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:12:25.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:25.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:25.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:25.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:25.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:25.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:25.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1254 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:30.431 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:30.431 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:30.432 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:30.434 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:30.434 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:30.435 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:30.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:30.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:30.444 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:30.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:30.444 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:12:30.448 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:12:30.448 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:12:30.448 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:30.448 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:30.449 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:30.449 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:12:30.449 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:30.449 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:12:30.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:30.452 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:12:30.452 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:12:30.452 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:30.452 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:30.453 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:30.453 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:12:30.453 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:30.453 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:12:30.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:30.455 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:12:30.455 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:12:30.456 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:30.456 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:30.456 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:30.456 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:12:30.456 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:30.456 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:12:30.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:30.460 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:12:30.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:12:30.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:12:30.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:12:30.460 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:12:30.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:12:30.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:12:30.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:12:30.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:12:30.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:30.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:30.461 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:12:30.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:30.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:30.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:30.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:30.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:30.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:30.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:30.461 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:12:30.461 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:12:30.461 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:12:30.461 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:12:30.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:30.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:30.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:30.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:30.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:30.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:30.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:30.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:30.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:30.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:30.466 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:12:30.949 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:12:30.988 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:12:30.990 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:12:30.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:30.990 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:12:31.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:12:31.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:12:31.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:12:31.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:31.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:31.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:31.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:31.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:31.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:31.030 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:31.030 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:31.030 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:31.030 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:12:31.031 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:31.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:31.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:31.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:31.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:31.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:31.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:31.031 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:36.031 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:36.031 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:36.032 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:36.033 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:36.033 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:36.034 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:36.041 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:36.042 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:36.042 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:36.043 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:36.043 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:12:36.045 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:12:36.045 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:12:36.046 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:36.046 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:36.046 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:36.047 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:12:36.047 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:36.047 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:12:36.048 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:36.049 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:12:36.049 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:12:36.049 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:36.049 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:36.049 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:36.050 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:12:36.050 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:36.050 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:12:36.050 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:36.052 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:12:36.052 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:12:36.052 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:36.052 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:36.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:36.052 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:12:36.052 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:36.052 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:12:36.053 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:36.056 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:12:36.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:12:36.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:12:36.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:12:36.056 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:12:36.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:12:36.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:12:36.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:12:36.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:12:36.057 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:12:36.057 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:12:36.057 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:36.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:36.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:36.062 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:12:36.546 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:12:36.590 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:12:36.592 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:12:36.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:36.595 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:12:36.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:12:36.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:12:36.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:12:36.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:36.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:36.628 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:36.628 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:36.628 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:36.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:36.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:36.631 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:36.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:36.631 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:36.631 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:36.631 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:12:36.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:36.631 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:36.631 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:36.631 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:36.631 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:36.632 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:36.632 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:36.632 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:36.632 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:41.632 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:41.632 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:41.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:41.635 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:41.636 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:41.637 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:41.645 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:41.646 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:41.647 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:41.647 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:41.647 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:12:41.652 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:12:41.652 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:12:41.652 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:41.652 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:41.653 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:41.653 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:12:41.654 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:41.654 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:12:41.654 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:41.655 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:12:41.655 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:12:41.655 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:41.655 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:41.655 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:41.655 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:12:41.656 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:41.656 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:12:41.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:41.657 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:12:41.657 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:12:41.658 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:41.658 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:41.658 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:41.658 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:12:41.658 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:41.658 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:12:41.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:41.661 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:12:41.661 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:12:41.661 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:12:41.662 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:41.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:41.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:41.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:41.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:41.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:41.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:41.666 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:12:42.149 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:12:42.179 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:12:42.180 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:12:42.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:42.181 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:12:42.200 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:12:42.200 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:12:42.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:12:42.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:42.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:42.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:42.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:42.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:42.220 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:42.220 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:42.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:42.224 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:42.224 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:42.224 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:42.224 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:12:42.224 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:42.224 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:42.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:42.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:42.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:42.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:42.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:42.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:42.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:47.224 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:47.224 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:47.225 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:47.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:47.228 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:47.228 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:47.237 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:47.239 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:47.239 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:47.240 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:47.240 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:12:47.246 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:12:47.247 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:12:47.247 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:47.248 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:47.248 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:47.248 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:12:47.249 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:47.249 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:12:47.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:47.252 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:12:47.253 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:12:47.253 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:47.253 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:47.253 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:47.253 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:12:47.253 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:47.253 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:12:47.253 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:47.257 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:12:47.257 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:12:47.257 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:47.257 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:47.257 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:12:47.257 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:47.257 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:47.257 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:12:47.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:47.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:12:47.262 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:12:47.262 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:12:47.262 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:47.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:47.266 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:12:47.750 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:12:47.790 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:12:47.792 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:12:47.794 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:12:47.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:47.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:12:47.819 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:12:47.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:12:47.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:47.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:47.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:47.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:47.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:47.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:47.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:47.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:47.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:47.856 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:47.856 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:47.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:47.856 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:47.859 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:47.859 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:47.859 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:47.859 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:47.860 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:47.860 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:47.860 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:12:47.860 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:47.860 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:47.860 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:47.861 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:47.861 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:47.861 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:47.861 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:12:52.859 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:52.859 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:52.860 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:52.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:52.863 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:52.863 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:52.868 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:52.869 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:52.869 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:52.870 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:12:52.870 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:12:52.873 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:12:52.873 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:12:52.874 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:52.874 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:52.874 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:52.875 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:12:52.875 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:12:52.875 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:12:52.876 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:52.876 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:12:52.877 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:12:52.877 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:52.877 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:52.877 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:52.877 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:12:52.877 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:12:52.877 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:12:52.877 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:52.879 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:12:52.879 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:12:52.879 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:52.880 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:12:52.880 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:52.880 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:12:52.880 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:12:52.880 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:12:52.880 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:52.883 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:12:52.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:12:52.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:12:52.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:12:52.883 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:12:52.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:12:52.884 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:12:52.884 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:12:52.884 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:52.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:12:52.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:52.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:52.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:52.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:52.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:52.889 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:12:53.373 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:12:53.411 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:12:53.412 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:12:53.413 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:12:53.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:53.414 [DEBUG] fake_trx.py:382 (BTS@172.18.201.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-05 03:12:53.414 [INFO] fake_trx.py:385 (BTS@172.18.201.20:5700) Artificial TRXC delay set to 200
2026-03-05 03:12:53.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-05 03:12:53.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:12:53.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:53.850 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:12:54.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:54.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:54.040 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:54.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:54.240 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:54.331 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:12:54.810 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:12:54.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:55.046 [DEBUG] fake_trx.py:382 (BTS@172.18.201.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-05 03:12:55.046 [INFO] fake_trx.py:385 (BTS@172.18.201.20:5700) Artificial TRXC delay set to 0
2026-03-05 03:12:55.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-05 03:12:55.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:55.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:55.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:55.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:12:55.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:12:55.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:12:55.052 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:12:55.052 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:12:55.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:12:55.053 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:12:55.053 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:12:55.053 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:12:55.053 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:12:55.053 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:12:55.053 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:13:00.055 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:13:00.055 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:13:00.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:13:00.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:13:00.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:13:00.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:13:00.066 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:13:00.068 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:13:00.068 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:00.069 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:13:00.069 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:13:00.072 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:13:00.072 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:13:00.073 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:13:00.073 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:00.073 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:13:00.074 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:13:00.074 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:13:00.074 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:13:00.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:00.075 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:13:00.075 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:13:00.075 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:13:00.075 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:00.076 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:13:00.076 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:13:00.076 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:13:00.076 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:13:00.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:00.078 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:13:00.078 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:13:00.078 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:13:00.078 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:00.078 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:13:00.078 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:13:00.078 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:13:00.078 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:13:00.078 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:13:00.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:13:00.082 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:13:00.082 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:13:00.082 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:00.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:00.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:00.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:00.087 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:13:00.568 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:13:00.612 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:13:00.614 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:13:00.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:00.616 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:13:00.618 [DEBUG] fake_trx.py:382 (BTS@172.18.201.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-05 03:13:00.619 [INFO] fake_trx.py:385 (BTS@172.18.201.20:5700) Artificial TRXC delay set to 200
2026-03-05 03:13:00.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-05 03:13:00.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:01.048 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:13:01.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:01.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:01.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:01.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:01.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:01.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:01.529 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:13:01.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:01.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:02.010 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:13:02.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:02.253 [DEBUG] fake_trx.py:382 (BTS@172.18.201.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-05 03:13:02.253 [INFO] fake_trx.py:385 (BTS@172.18.201.20:5700) Artificial TRXC delay set to 0
2026-03-05 03:13:02.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-05 03:13:02.254 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:02.254 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:02.254 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:02.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:02.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:02.254 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:13:02.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:02.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:02.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:02.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:02.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:02.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:02.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:02.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:02.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:13:02.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:02.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:02.260 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:02.260 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:13:02.260 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:13:02.260 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:13:02.260 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:13:02.260 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:13:02.260 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:13:02.260 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:13:07.267 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:13:07.267 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:13:07.267 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:13:07.267 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:13:07.267 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:13:07.267 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:13:07.275 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:13:07.277 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:13:07.277 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:07.278 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:13:07.278 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:13:07.282 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:13:07.282 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:13:07.283 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:13:07.283 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:07.283 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:13:07.284 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:13:07.284 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:13:07.284 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:13:07.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:07.285 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:13:07.285 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:13:07.285 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:13:07.285 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:07.286 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:13:07.286 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:13:07.286 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:13:07.286 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:13:07.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:07.288 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:13:07.288 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:13:07.288 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:13:07.288 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:07.289 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:13:07.289 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:13:07.289 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:13:07.289 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:13:07.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:07.292 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:07.293 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:13:07.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:07.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:07.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:07.293 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:13:07.293 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:13:07.293 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:13:07.293 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:13:07.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:07.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:07.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:07.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:13:07.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:07.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:07.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:07.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:07.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:07.298 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:13:07.782 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:13:07.823 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:13:07.825 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:13:07.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:07.827 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:13:07.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:07.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:07.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:07.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:07.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:07.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:13:07.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:07.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:07.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:07.867 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:13:07.868 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:13:07.868 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:13:07.868 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:13:07.868 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:13:07.868 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:13:07.868 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:13:07.868 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:07.868 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:07.868 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:07.868 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:07.868 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:07.868 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:07.868 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:12.870 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:13:12.870 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:13:12.873 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:13:12.873 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:13:12.873 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:13:12.873 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:13:12.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:13:12.881 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:13:12.881 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:12.881 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:13:12.881 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:13:12.882 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:13:12.882 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:13:12.882 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:13:12.882 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:12.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:13:12.882 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:13:12.882 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:13:12.882 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:13:12.882 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:12.884 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:13:12.884 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:13:12.884 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:13:12.884 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:12.884 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:13:12.884 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:13:12.884 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:13:12.884 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:13:12.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:12.886 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:13:12.886 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:13:12.886 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:13:12.886 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:12.886 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:13:12.886 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:13:12.886 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:13:12.886 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:13:12.886 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:12.888 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:13:12.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:13:12.889 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:13:12.889 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:13:12.889 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:12.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:12.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:12.894 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:13:13.378 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:13:13.417 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:13:13.420 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:13:13.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:13.422 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:13:13.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:13.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:13.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:13.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:13.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:13.456 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:13:13.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:13.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:13.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:13.457 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:13:13.458 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:13:13.458 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:13:13.458 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:13:13.458 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:13:13.458 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:13:13.458 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:13:13.458 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:13.458 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:13.458 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:13.458 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:13.458 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:13.458 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:13.458 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:13.459 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:13:18.460 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:13:18.461 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:13:18.462 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:13:18.463 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:13:18.463 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:13:18.463 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:13:18.472 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:13:18.474 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:13:18.474 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:18.475 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:13:18.475 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:13:18.480 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:13:18.480 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:13:18.481 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:13:18.481 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:18.481 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:13:18.482 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:13:18.482 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:13:18.482 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:13:18.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:18.483 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:13:18.483 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:13:18.483 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:13:18.483 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:18.484 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:13:18.484 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:13:18.484 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:13:18.484 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:13:18.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:18.486 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:13:18.486 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:13:18.486 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:13:18.486 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:13:18.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:13:18.486 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:13:18.486 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:13:18.486 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:13:18.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:18.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:13:18.490 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:13:18.490 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:13:18.490 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:18.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:18.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:18.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:18.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:18.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:13:18.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:13:18.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:13:18.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:18.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:18.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:18.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:18.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:13:18.495 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:13:18.979 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:13:19.015 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:13:19.018 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:13:19.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:19.019 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:13:19.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:19.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:19.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:19.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:19.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:19.037 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:19.037 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:19.037 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:19.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:19.084 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:19.084 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:19.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:19.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:19.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:19.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:19.143 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:19.143 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:19.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:19.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:19.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:19.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:19.162 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:19.162 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:19.162 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:19.162 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:19.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:19.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:19.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:19.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:19.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:19.456 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:13:19.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:13:19.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:19.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:19.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:19.934 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:13:20.412 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:13:20.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:13:20.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:20.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:20.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:20.890 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:13:21.368 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:13:21.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:13:21.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:21.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:21.498 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:21.846 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:13:22.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:22.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:22.228 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:22.228 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:22.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:22.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:22.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:22.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:22.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:22.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:22.250 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:22.250 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:22.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:22.270 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:22.270 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:22.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:22.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:22.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:22.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:22.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:22.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:22.323 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:13:22.339 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:22.339 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:22.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:22.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:22.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:22.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:22.340 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:22.340 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:22.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:22.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:22.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:22.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:22.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:22.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:13:22.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:22.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:22.499 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:22.797 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:13:23.275 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:13:23.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:13:23.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:13:23.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:13:23.500 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:13:23.753 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:13:24.230 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:13:24.708 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:13:25.186 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:13:25.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:25.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:25.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:25.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:25.396 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:25.396 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:25.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:25.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:25.397 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:25.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:25.397 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:25.397 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:25.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:25.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:25.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:25.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:25.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:25.663 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:13:26.141 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:13:26.619 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:13:27.097 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:13:27.575 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:13:28.054 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:13:28.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:28.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:28.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:28.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:28.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:28.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:28.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:28.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:28.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:28.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:28.460 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:28.460 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:28.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:28.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:28.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:28.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:28.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:28.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:28.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:28.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:28.529 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:28.531 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:13:28.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:28.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:28.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:28.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:28.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:28.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:28.550 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:28.550 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:28.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:28.586 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:28.586 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:28.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:28.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:29.008 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:13:29.486 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:13:29.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:29.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:29.696 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:29.696 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:29.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:29.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:29.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:29.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:29.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:29.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:29.719 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:29.719 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:29.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:29.773 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:13:29.773 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:13:29.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:29.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:29.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:29.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:29.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:29.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:29.871 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:13:29.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:29.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:29.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:29.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:29.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:29.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:29.889 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:29.889 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:29.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:29.906 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:13:29.907 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:13:29.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:29.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:29.962 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:13:30.440 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:13:30.919 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:13:31.398 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:13:31.876 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:13:32.354 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:13:32.833 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:13:32.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:32.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:32.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:32.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:32.915 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:13:32.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:32.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:32.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:32.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:32.936 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:32.936 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:32.936 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:32.936 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:32.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:32.981 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:13:32.981 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:13:32.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:32.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:33.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:33.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:33.041 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:33.041 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:33.041 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:13:33.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:33.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:33.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:33.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:33.062 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:33.062 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:33.062 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:33.062 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:33.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:33.067 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:13:33.067 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:13:33.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:33.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:33.306 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:13:33.776 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:13:34.246 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:13:34.717 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:13:35.188 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:13:35.666 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:13:36.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:36.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:36.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:36.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:36.075 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:13:36.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:36.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:36.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:36.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:36.094 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:36.094 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:36.094 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:36.094 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:36.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:36.140 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:13:36.140 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:13:36.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:36.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:36.142 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:13:36.620 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:13:37.099 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:13:37.578 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:13:38.056 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:13:38.534 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:13:39.012 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:13:39.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:39.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:39.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:39.148 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:39.148 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:13:39.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:39.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:39.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:39.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:39.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:39.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:39.170 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:39.170 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:39.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:39.206 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:13:39.206 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:13:39.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:39.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:39.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:39.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:39.304 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:39.304 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:39.304 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:13:39.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:39.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:39.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:39.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:39.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:39.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:39.326 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:39.326 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:39.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:39.343 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:13:39.343 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:13:39.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:39.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:39.487 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:13:39.956 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:13:40.425 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:13:40.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:40.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:40.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:40.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:40.609 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:13:40.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:40.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:40.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:40.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:40.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:40.629 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:40.629 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:40.629 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:40.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:40.671 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:40.671 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:40.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:40.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:40.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:40.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:40.892 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:40.892 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:40.898 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:13:40.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:40.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:40.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:40.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:40.910 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:40.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:40.910 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:40.910 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:40.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:40.952 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:40.952 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:40.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:40.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:41.376 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:13:41.854 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:13:42.331 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:13:42.809 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:13:43.287 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:13:43.765 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:13:43.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:43.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:43.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:43.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:43.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:43.978 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:43.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:43.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:43.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:43.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:43.980 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:43.980 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:43.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:44.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:44.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:44.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:44.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:44.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:44.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:44.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:44.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:44.241 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:13:44.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:44.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:44.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:44.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:44.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:44.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:44.250 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:44.250 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:44.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:44.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:44.298 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:44.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:44.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:44.718 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:13:45.195 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 03:13:45.673 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 03:13:46.152 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 03:13:46.629 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 03:13:47.107 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 03:13:47.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:47.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:47.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:47.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:47.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:47.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:47.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:47.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:47.323 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:47.323 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:47.323 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:47.323 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:47.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:47.344 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:47.344 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:47.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:47.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:47.584 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 03:13:48.062 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 03:13:48.540 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 03:13:49.018 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 03:13:49.495 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 03:13:49.973 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 03:13:50.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:50.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:50.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:50.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:50.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:50.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:50.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:50.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:50.371 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:50.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:50.371 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:50.371 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:50.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:50.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:50.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:50.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:50.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:50.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:50.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:50.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:50.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:50.450 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 03:13:50.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:50.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:50.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:50.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:50.453 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:50.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:50.453 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:50.453 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:50.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:50.507 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:50.508 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:50.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:50.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:50.927 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 03:13:51.406 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 03:13:51.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:51.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:51.449 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:51.449 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:51.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:51.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:51.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:51.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:51.467 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:51.467 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:51.467 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:51.467 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:51.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:51.506 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:13:51.506 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:13:51.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:51.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:51.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:51.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:51.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:51.564 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:51.565 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:13:51.582 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:51.582 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:51.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:51.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:51.583 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:51.583 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:51.584 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:51.584 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:51.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:51.589 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:13:51.589 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:13:51.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:51.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:51.882 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 03:13:52.356 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 03:13:52.834 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 03:13:53.312 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 03:13:53.789 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 03:13:54.268 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 03:13:54.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:54.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:54.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:54.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:54.596 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:13:54.616 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:54.616 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:54.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:54.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:54.617 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:54.617 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:54.617 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:54.617 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:54.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:54.651 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:13:54.651 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:13:54.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:54.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:54.745 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 03:13:55.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:55.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:55.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:55.137 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:55.138 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:13:55.157 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:55.157 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:55.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:55.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:55.159 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:55.159 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:55.159 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:55.159 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:55.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:55.163 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:13:55.163 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:13:55.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:55.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:55.222 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 03:13:55.700 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 03:13:56.178 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 03:13:56.656 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 03:13:57.134 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 03:13:57.612 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 03:13:58.090 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 03:13:58.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:58.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:58.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:58.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:58.170 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:13:58.180 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:13:58.180 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:13:58.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:13:58.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:58.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:13:58.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:13:58.181 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:13:58.181 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:13:58.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:13:58.237 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:13:58.237 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:13:58.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:58.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:13:58.566 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 03:13:59.044 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 03:13:59.522 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 03:14:00.000 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 03:14:00.478 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 03:14:00.956 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 03:14:01.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:01.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:01.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:01.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:01.245 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:14:01.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:01.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:01.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:01.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:01.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:01.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:01.264 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:01.265 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:01.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:01.290 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:14:01.290 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:14:01.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:01.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:01.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:01.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:01.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:01.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:01.350 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:14:01.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:01.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:01.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:01.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:01.372 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:01.372 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:01.372 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:01.372 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:01.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:01.430 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 03:14:01.436 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:14:01.436 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:14:01.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:01.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:01.899 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 03:14:02.369 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 03:14:02.842 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 03:14:03.316 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 03:14:03.790 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 03:14:04.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:04.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:04.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:04.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:04.245 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:14:04.253 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:04.253 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:04.253 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:04.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:04.257 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:04.257 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:04.257 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:04.257 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:04.257 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:14:04.257 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:14:04.257 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:14:04.257 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=9793 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:04.257 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=9793 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:04.257 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=9793 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:04.257 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=9793 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:04.257 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=9793 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:04.257 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=9793 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:04.257 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=9793 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:09.254 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:14:09.254 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:14:09.255 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:09.255 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:09.255 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:09.256 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:09.259 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:09.259 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:14:09.259 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:09.259 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:14:09.259 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:14:09.260 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:14:09.260 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:14:09.260 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:14:09.260 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:09.260 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:09.260 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:14:09.260 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:14:09.260 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:14:09.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:09.261 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:14:09.261 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:14:09.261 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:14:09.261 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:09.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:09.261 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:14:09.261 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:14:09.261 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:14:09.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:09.262 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:14:09.262 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:14:09.262 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:14:09.262 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:09.262 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:09.262 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:14:09.262 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:14:09.262 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:14:09.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:09.263 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:14:09.263 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:14:09.263 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:14:09.263 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:09.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:09.268 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:14:09.737 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:14:09.776 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:14:09.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:09.776 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:14:09.777 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:14:09.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:09.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:09.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:09.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:09.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:09.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:09.785 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:09.785 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:09.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:09.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:09.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:09.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:09.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:09.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:09.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:09.891 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:09.891 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:09.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:09.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:09.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:09.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:09.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:09.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:09.899 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:09.899 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:09.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:09.921 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:14:09.921 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:14:09.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:09.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:10.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:10.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:10.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:10.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:10.011 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:14:10.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:10.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:10.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:10.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:10.020 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:10.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:10.020 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:10.020 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:10.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:10.064 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:10.064 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:10.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:10.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:10.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:10.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:10.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:10.127 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:10.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:10.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:10.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:10.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:10.135 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:10.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:10.135 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:10.135 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:10.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:10.155 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:14:10.155 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:14:10.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:10.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:10.205 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:14:10.265 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:10.265 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:10.266 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:10.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:10.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:10.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:10.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:10.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:10.283 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:14:10.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:10.286 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:10.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:10.286 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:10.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:10.287 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:10.287 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:14:10.287 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:14:10.287 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:14:10.287 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:10.287 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:10.287 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=224 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:10.287 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=224 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:10.287 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=224 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:10.287 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=224 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:10.287 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=224 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:10.287 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=224 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:10.287 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=224 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:15.287 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:14:15.287 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:14:15.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:15.288 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:15.288 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:15.289 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:15.291 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:15.291 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:14:15.292 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:15.292 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:14:15.292 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:14:15.292 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:14:15.292 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:14:15.292 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:14:15.292 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:15.293 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:15.293 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:14:15.293 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:14:15.293 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:14:15.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:15.293 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:14:15.293 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:14:15.293 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:14:15.293 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:15.293 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:15.293 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:14:15.293 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:14:15.293 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:14:15.293 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:15.294 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:14:15.294 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:14:15.294 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:14:15.294 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:15.294 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:15.294 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:14:15.294 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:14:15.294 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:14:15.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:15.295 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:14:15.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:14:15.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:14:15.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:14:15.295 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:14:15.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:14:15.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:14:15.296 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:14:15.296 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:14:15.296 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:15.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:15.301 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:14:15.769 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:14:15.812 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:14:15.813 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:14:15.814 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:14:15.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:15.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:15.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:15.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:15.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:15.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:15.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:15.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:15.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:15.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:15.865 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:15.865 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:15.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:15.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:16.241 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:14:16.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:16.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:16.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:16.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:16.258 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:16.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:16.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:16.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:16.260 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:16.260 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:16.260 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:16.260 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:16.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:16.287 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:14:16.287 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:14:16.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:16.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:16.298 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:16.298 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:16.298 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:16.300 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:16.711 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:14:16.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:16.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:16.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:16.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:16.967 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:14:16.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:16.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:16.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:16.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:16.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:16.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:16.976 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:16.976 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:16.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:16.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:16.992 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:16.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:16.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:17.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:17.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:17.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:17.148 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:17.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:17.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:17.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:17.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:17.156 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:17.156 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:17.156 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:17.156 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:17.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:17.180 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:14:17.182 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:14:17.182 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:14:17.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:17.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:17.299 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:17.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:17.299 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:17.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:17.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:17.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:17.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:17.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:17.567 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:14:17.569 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:17.569 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:17.569 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:17.569 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:17.570 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:17.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:17.570 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:17.570 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:17.570 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:14:17.570 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:14:17.570 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:14:17.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=495 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:17.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=495 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:17.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=495 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:17.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=495 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:17.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=495 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:17.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=495 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:17.570 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=495 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:22.573 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:14:22.573 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:14:22.578 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:22.579 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:22.579 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:22.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:22.591 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:22.592 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:14:22.592 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:22.592 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:14:22.592 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:14:22.594 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:14:22.594 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:14:22.594 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:14:22.594 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:22.595 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:22.595 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:14:22.595 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:14:22.595 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:14:22.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:22.596 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:14:22.596 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:14:22.596 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:14:22.596 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:22.596 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:22.596 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:14:22.597 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:14:22.597 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:14:22.597 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:22.598 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:14:22.598 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:14:22.598 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:14:22.598 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:22.598 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:22.599 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:14:22.599 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:14:22.599 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:14:22.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:22.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:14:22.602 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:14:22.602 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:14:22.602 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:22.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:22.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:22.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:22.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:22.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:22.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:22.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:22.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:22.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:22.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:22.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:22.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:22.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:22.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:22.607 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:14:23.088 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:14:23.134 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:14:23.137 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:14:23.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:23.140 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:14:23.167 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:23.167 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:23.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:23.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:23.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:23.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:23.171 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:23.171 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:23.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:23.184 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:23.185 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:23.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:23.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:23.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:23.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:23.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:23.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:23.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:23.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:23.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:23.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:23.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:23.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:23.359 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:23.359 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:23.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:23.368 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:14:23.368 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:14:23.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:23.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:23.561 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:14:23.605 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:23.605 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:23.607 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:23.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:23.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:23.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:23.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:23.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:23.627 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:14:23.645 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:23.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:23.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:23.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:23.646 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:23.646 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:23.646 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:23.646 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:23.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:23.701 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:23.701 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:23.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:23.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:24.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:24.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:24.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:24.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:24.034 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:14:24.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:24.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:24.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:24.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:24.044 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:24.044 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:24.044 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:24.044 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:24.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:24.093 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:14:24.093 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:14:24.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:24.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:24.512 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:14:24.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:24.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:24.609 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:24.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:24.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:24.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:24.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:24.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:24.905 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:14:24.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:24.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:24.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:24.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:24.917 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:24.918 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:24.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:24.918 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:24.918 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:14:24.918 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:14:24.918 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:14:24.919 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:24.919 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:24.919 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:24.919 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:24.919 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:24.919 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:29.914 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:14:29.914 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:14:29.915 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:29.915 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:29.915 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:29.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:29.918 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:29.919 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:14:29.919 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:29.919 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:14:29.919 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:14:29.919 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:14:29.919 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:14:29.919 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:14:29.919 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:29.919 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:29.919 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:14:29.920 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:14:29.920 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:14:29.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:29.920 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:14:29.920 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:14:29.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:14:29.920 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:29.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:29.920 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:14:29.920 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:14:29.920 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:14:29.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:29.921 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:14:29.921 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:14:29.921 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:14:29.921 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:29.921 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:29.921 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:14:29.921 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:14:29.921 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:14:29.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:29.922 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:14:29.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:14:29.923 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:14:29.923 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:14:29.923 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:29.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:29.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:29.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:29.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:29.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:29.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:29.928 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:14:30.402 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:14:30.444 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:14:30.445 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:14:30.446 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:14:30.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:30.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:30.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:30.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:30.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:30.466 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:30.466 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:30.466 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:30.466 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:30.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:30.506 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:30.507 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:30.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:30.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:30.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:30.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:30.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:30.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:30.673 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:30.673 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:30.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:30.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:30.674 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:30.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:30.674 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:30.674 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:30.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:30.682 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:14:30.682 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:14:30.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:30.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:30.875 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:14:30.925 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:30.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:30.926 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:30.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:30.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:30.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:30.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:30.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:30.942 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:14:30.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:30.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:30.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:30.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:30.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:30.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:30.961 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:30.961 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:31.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:31.022 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:31.022 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:31.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:31.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:31.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:31.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:31.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:31.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:31.344 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:14:31.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:31.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:31.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:31.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:31.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:31.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:31.362 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:31.362 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:31.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:31.399 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:14:31.400 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:14:31.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:31.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:31.819 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:14:31.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:31.927 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:31.927 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:31.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:32.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:32.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:32.209 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:32.209 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:32.210 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:14:32.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:32.218 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:32.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:32.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:32.221 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:32.222 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:32.222 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:32.222 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:14:32.222 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:14:32.222 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:14:32.222 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:32.223 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.223 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.223 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.223 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.223 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.223 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.223 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.223 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.223 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.223 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.223 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:32.224 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:14:37.220 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:14:37.220 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:14:37.220 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:37.220 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:37.220 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:37.221 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:37.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:14:37.224 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:14:37.224 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:37.225 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:14:37.225 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:14:37.225 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:14:37.225 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:14:37.225 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:14:37.225 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:37.225 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:14:37.225 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:14:37.225 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:14:37.225 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:14:37.225 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:37.226 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:14:37.226 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:14:37.226 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:14:37.226 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:37.226 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:14:37.226 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:14:37.226 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:14:37.226 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:14:37.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:37.227 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:14:37.227 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:14:37.227 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:14:37.227 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:14:37.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:14:37.227 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:14:37.227 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:14:37.227 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:14:37.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:37.228 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:14:37.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:14:37.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:14:37.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:14:37.228 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:14:37.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:14:37.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:14:37.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:14:37.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:14:37.229 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:14:37.229 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:14:37.229 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:37.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:14:37.233 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:14:37.708 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:14:37.740 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:14:37.741 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:14:37.741 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:14:37.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:37.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:37.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:37.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:37.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:37.748 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:37.748 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:37.748 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:37.748 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:37.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:37.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:37.753 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:37.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:37.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:38.179 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:14:38.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:38.231 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:38.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:38.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:38.654 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:14:39.127 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:14:39.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:39.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:39.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:39.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:39.600 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:14:39.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:39.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:39.639 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:39.639 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:39.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:39.646 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:39.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:39.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:39.647 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:39.647 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:39.647 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:39.647 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:39.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:39.687 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:14:39.687 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:14:39.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:39.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:40.069 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:14:40.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:40.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:40.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:40.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:40.538 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:14:41.007 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:14:41.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:41.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:41.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:41.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:41.476 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:14:41.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:41.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:41.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:41.806 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:41.806 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:14:41.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:41.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:41.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:41.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:41.826 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:41.826 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:41.826 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:41.826 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:41.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:41.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:41.854 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:41.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:41.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:41.944 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:14:42.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:14:42.235 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:14:42.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:14:42.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:14:42.417 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:14:42.891 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:14:43.363 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:14:43.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:43.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:43.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:43.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:43.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:14:43.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:14:43.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:14:43.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:43.420 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:14:43.420 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:14:43.420 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:14:43.420 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:14:43.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:14:43.451 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:14:43.451 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:14:43.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:43.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:14:43.835 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:14:44.305 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:14:44.777 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:14:45.247 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:14:45.717 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:14:46.188 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:14:46.658 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:14:47.134 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:14:47.610 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:14:48.085 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:14:48.553 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:14:49.028 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:14:49.503 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:14:49.975 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:14:50.451 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:14:50.925 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:14:51.396 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:14:51.867 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:14:52.340 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:14:52.815 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:14:53.289 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:14:53.758 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:14:54.231 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:14:54.705 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:14:55.182 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:14:55.658 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:14:56.132 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:14:56.601 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:14:57.072 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:14:57.550 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:14:58.029 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:14:58.503 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:14:58.980 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:14:59.459 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:14:59.937 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:15:00.416 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:15:00.894 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:15:01.372 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:15:01.851 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:15:02.329 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:15:02.808 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:15:03.286 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:15:03.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:03.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:03.421 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:15:03.423 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:03.424 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:03.424 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:03.424 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:03.426 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:15:03.426 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:15:03.426 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:15:03.426 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:15:03.426 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:15:03.426 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:15:03.426 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:15:03.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5641 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:15:03.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5641 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:15:03.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5641 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:15:03.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5641 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:15:03.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5642 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:15:03.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5642 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:15:03.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5642 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:15:03.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5642 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:15:03.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5642 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:15:03.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5642 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:15:03.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5642 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:15:03.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5642 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:15:08.428 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:15:08.428 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:15:08.429 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:15:08.431 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:15:08.432 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:15:08.435 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:15:08.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:15:08.442 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:15:08.442 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:15:08.442 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:15:08.442 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:15:08.443 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:15:08.444 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:15:08.444 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:15:08.444 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:15:08.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:15:08.444 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:15:08.444 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:15:08.444 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:15:08.444 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:08.445 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:15:08.445 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:15:08.445 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:15:08.445 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:15:08.445 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:15:08.445 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:15:08.445 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:15:08.445 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:15:08.445 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:08.446 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:15:08.446 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:15:08.446 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:15:08.446 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:15:08.446 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:15:08.446 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:15:08.447 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:15:08.447 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:15:08.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:08.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:15:08.449 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:15:08.449 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:15:08.449 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:08.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:08.453 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:15:08.938 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:15:08.963 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:15:08.964 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:15:08.964 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:15:08.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:08.971 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:08.971 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:08.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:08.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:08.973 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:08.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:08.973 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:08.973 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:08.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:08.990 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:08.990 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:08.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:08.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:09.416 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:15:09.451 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:09.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:09.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:09.453 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:09.894 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:15:10.371 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:15:10.452 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:10.452 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:10.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:10.454 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:10.849 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:15:10.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:10.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:10.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:10.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:10.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:10.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:10.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:10.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:10.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:10.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:10.918 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:10.918 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:10.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:10.945 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:15:10.945 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:15:10.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:10.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:11.326 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:15:11.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:11.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:11.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:11.455 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:11.805 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:15:12.283 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:15:12.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:12.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:12.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:12.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:12.761 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:15:13.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:13.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:13.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:13.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:13.093 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:15:13.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:13.114 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:13.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:13.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:13.116 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:13.116 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:13.116 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:13.116 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:13.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:13.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:13.141 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:13.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:13.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:13.239 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:15:13.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:13.455 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:13.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:13.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:13.717 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:15:14.194 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:15:14.672 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:15:14.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:14.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:14.713 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:14.714 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:14.730 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:14.730 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:14.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:14.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:14.731 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:14.731 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:14.732 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:14.732 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:14.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:14.768 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:15:14.768 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:15:14.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:14.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:15.149 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:15:15.628 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:15:16.106 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:15:16.584 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:15:17.062 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:15:17.540 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:15:18.019 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:15:18.497 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:15:18.976 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:15:19.454 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:15:19.933 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:15:20.410 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:15:20.889 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:15:21.367 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:15:21.846 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:15:22.324 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:15:22.803 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:15:23.281 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:15:23.757 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:15:24.235 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:15:24.713 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:15:25.191 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:15:25.670 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:15:26.148 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:15:26.626 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:15:27.105 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:15:27.583 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:15:28.062 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:15:28.540 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:15:29.019 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:15:29.498 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:15:29.977 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:15:30.454 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:15:30.933 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:15:31.411 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:15:31.890 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:15:32.369 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:15:32.847 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:15:33.326 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:15:33.804 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:15:34.282 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:15:34.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:34.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:34.734 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:15:34.737 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:34.737 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:34.737 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:34.737 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:34.738 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:15:34.738 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:15:34.738 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:15:34.738 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:15:34.738 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:15:34.738 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:15:34.738 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:15:39.743 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:15:39.743 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:15:39.743 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:15:39.743 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:15:39.743 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:15:39.743 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:15:39.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:15:39.754 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:15:39.754 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:15:39.755 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:15:39.755 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:15:39.759 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:15:39.759 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:15:39.760 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:15:39.760 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:15:39.761 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:15:39.761 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:15:39.761 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:15:39.762 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:15:39.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:39.763 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:15:39.763 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:15:39.764 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:15:39.764 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:15:39.764 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:15:39.764 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:15:39.765 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:15:39.765 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:15:39.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:39.766 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:15:39.766 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:15:39.766 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:15:39.766 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:15:39.766 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:15:39.766 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:15:39.767 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:15:39.767 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:15:39.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:39.770 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:15:39.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:15:39.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:15:39.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:15:39.770 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:15:39.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:15:39.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:15:39.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:15:39.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:15:39.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:39.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:39.770 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:15:39.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:15:39.771 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:15:39.771 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:15:39.771 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:39.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:39.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:15:39.776 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:15:40.259 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:15:40.293 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:15:40.293 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:15:40.294 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:15:40.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:40.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:40.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:40.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:40.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:40.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:40.304 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:40.304 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:40.304 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:40.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:40.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:40.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:40.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:40.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:40.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:40.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:40.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:40.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:40.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:40.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:40.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:40.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:40.558 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:40.558 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:40.558 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:40.558 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:40.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:40.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:40.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:40.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:40.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:40.736 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:15:40.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:40.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:40.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:40.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:41.214 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:15:41.692 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:15:41.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:41.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:41.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:41.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:42.169 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:15:42.647 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:15:42.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:42.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:42.696 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:42.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:42.715 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:42.715 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:42.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:42.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:42.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:42.717 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:42.717 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:42.717 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:42.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:42.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:42.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:42.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:42.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:42.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:42.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:42.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:42.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:42.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:42.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:42.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:42.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:42.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:42.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:42.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:42.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:42.934 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:42.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:42.934 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:42.934 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:42.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:42.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:42.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:42.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:42.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:43.124 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:15:43.602 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:15:43.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:43.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:43.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:43.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:44.081 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:15:44.557 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:15:44.779 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:15:44.779 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:15:44.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:15:44.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:15:45.035 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:15:45.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:45.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:45.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:45.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:45.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:45.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:45.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:45.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:45.152 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:45.152 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:45.152 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:45.152 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:45.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:45.182 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:15:45.182 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:15:45.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:45.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:45.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:45.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:45.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:45.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:45.450 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:15:45.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:45.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:45.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:45.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:45.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:45.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:45.460 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:45.460 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:45.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:45.509 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:15:45.509 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:15:45.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:45.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:45.512 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:15:45.991 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:15:46.469 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:15:46.941 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:15:47.420 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:15:47.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:47.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:47.803 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:47.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:47.804 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:15:47.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:47.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:47.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:47.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:47.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:47.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:47.823 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:47.823 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:47.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:47.842 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:15:47.842 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:15:47.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:47.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:47.898 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:15:48.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:48.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:48.128 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:48.128 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:48.128 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:15:48.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:48.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:48.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:48.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:48.149 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:48.149 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:48.149 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:48.149 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:48.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:48.189 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:15:48.189 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:15:48.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:48.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:48.376 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:15:48.854 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:15:49.332 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:15:49.810 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:15:50.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:50.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:50.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:50.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:50.238 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:15:50.255 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:50.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:50.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:50.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:50.257 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:50.257 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:50.257 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:50.257 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:50.281 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:15:50.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:50.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:50.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:50.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:50.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:50.759 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:15:50.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:50.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:50.918 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:50.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:50.939 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:50.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:50.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:50.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:50.940 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:50.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:50.940 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:50.940 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:50.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:51.000 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:51.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:51.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:51.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:51.236 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:15:51.714 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:15:52.192 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:15:52.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:52.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:52.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:52.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:52.645 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:52.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:52.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:52.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:52.646 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:52.646 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:52.646 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:52.646 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:52.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:52.664 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:52.664 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:52.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:52.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:52.670 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:15:53.147 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:15:53.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:53.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:53.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:53.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:53.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:53.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:53.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:53.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:53.319 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:53.319 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:53.319 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:53.319 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:53.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:53.331 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:53.331 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:53.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:53.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:53.622 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:15:54.100 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:15:54.578 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:15:55.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:55.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:55.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:55.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:55.038 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:55.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:55.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:55.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:55.039 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:55.039 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:55.040 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:55.040 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:55.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:55.047 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:15:55.047 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:15:55.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:55.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:55.054 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:15:55.527 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:15:56.005 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:15:56.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:56.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:56.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:56.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:56.327 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:15:56.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:15:56.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:15:56.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:15:56.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:56.348 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:15:56.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:15:56.348 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:15:56.348 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:15:56.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:15:56.390 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:15:56.390 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:15:56.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:56.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:15:56.483 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:15:56.961 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:15:57.439 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:15:57.917 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:15:58.395 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:15:58.874 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:15:59.352 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:15:59.830 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:16:00.309 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:16:00.787 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:16:01.266 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:16:01.745 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:16:02.223 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:16:02.702 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:16:03.180 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:16:03.657 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:16:04.135 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:16:04.614 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:16:05.092 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:16:05.570 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:16:06.049 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:16:06.527 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 03:16:07.006 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 03:16:07.485 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 03:16:07.963 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 03:16:08.441 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 03:16:08.920 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 03:16:09.398 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 03:16:09.877 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 03:16:10.355 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 03:16:10.834 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 03:16:11.313 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 03:16:11.791 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 03:16:12.270 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 03:16:12.748 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 03:16:13.227 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 03:16:13.705 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 03:16:14.184 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 03:16:14.662 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 03:16:15.141 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 03:16:15.619 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 03:16:16.097 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 03:16:16.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:16.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:16.350 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:16.353 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:16.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:16.353 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:16.353 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:16.354 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:16:16.354 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:16:16.354 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:16:16.354 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:16:16.354 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:16:16.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:16:16.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:16:16.354 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7809 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:16.354 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7809 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:16.354 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7809 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:16.354 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7809 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:16.354 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7809 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:16.354 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7809 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:16.355 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=7809 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:21.357 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:16:21.357 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:16:21.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:16:21.360 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:16:21.361 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:16:21.361 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:16:21.370 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:16:21.371 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:16:21.371 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:21.371 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:16:21.372 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:16:21.375 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:16:21.375 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:16:21.375 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:16:21.376 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:21.376 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:16:21.376 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:16:21.377 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:16:21.377 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:16:21.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:21.378 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:16:21.378 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:16:21.378 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:16:21.378 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:21.378 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:16:21.378 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:16:21.378 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:16:21.378 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:16:21.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:21.380 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:16:21.380 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:16:21.380 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:16:21.380 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:21.380 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:16:21.380 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:16:21.380 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:16:21.380 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:16:21.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:21.383 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:16:21.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:16:21.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:16:21.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:16:21.383 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:16:21.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:16:21.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:16:21.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:16:21.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:16:21.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:21.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:16:21.384 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:16:21.384 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:16:21.384 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:21.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:21.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:21.389 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:16:21.873 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:16:21.916 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:16:21.918 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:16:21.920 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:16:21.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:21.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:21.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:21.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:21.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:21.947 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:21.947 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:21.947 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:21.947 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:21.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:21.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:21.979 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:21.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:21.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:22.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:22.052 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:22.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:22.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:22.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:22.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:22.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:22.071 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:22.071 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:22.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:22.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:22.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:22.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:22.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:22.195 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:22.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:22.212 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:22.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:22.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.214 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:22.214 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:22.214 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:22.214 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:22.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:22.257 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:22.257 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:16:22.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.347 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:16:22.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:22.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:22.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:22.354 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:22.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:22.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:22.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:22.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:22.378 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:22.378 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:22.378 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:22.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:22.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:22.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:22.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:22.390 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:22.390 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:16:22.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:22.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:22.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.473 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:22.473 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:22.473 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:22.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:22.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:22.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:22.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:22.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:22.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:22.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:22.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:22.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:22.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:22.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:22.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:22.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:22.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:22.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:22.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:22.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:22.758 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:22.758 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:22.758 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:22.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:22.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:22.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:22.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.819 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:16:22.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:22.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.976 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:22.976 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:22.992 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:22.992 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:22.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:22.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:22.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:22.993 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:22.993 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:22.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:22.998 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:22.998 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:16:22.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:22.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:23.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:23.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:23.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:23.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:23.138 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:23.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:23.152 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:23.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:23.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:23.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:23.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:23.153 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:23.153 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:23.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:23.197 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:23.197 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:16:23.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:23.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:23.294 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:16:23.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:23.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:23.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:23.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:23.378 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:23.383 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:23.383 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:23.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:23.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:23.386 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:16:23.387 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:16:23.387 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:16:23.387 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:16:23.387 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:16:23.387 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:16:23.387 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:16:23.388 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=430 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:23.388 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=430 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:23.388 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=430 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:23.388 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=430 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:23.388 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=430 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:23.388 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=430 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:28.389 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:16:28.389 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:16:28.389 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:16:28.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:16:28.389 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:16:28.389 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:16:28.397 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:16:28.397 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:16:28.397 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:28.397 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:16:28.398 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:16:28.400 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:16:28.400 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:16:28.401 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:16:28.401 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:28.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:16:28.402 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:16:28.402 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:16:28.402 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:16:28.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:28.403 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:16:28.403 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:16:28.404 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:16:28.404 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:28.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:16:28.404 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:16:28.404 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:16:28.404 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:16:28.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:28.406 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:16:28.406 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:16:28.406 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:16:28.406 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:28.406 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:16:28.406 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:16:28.406 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:16:28.407 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:16:28.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:28.409 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:16:28.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:16:28.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:16:28.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:16:28.409 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:16:28.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:16:28.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:16:28.410 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:16:28.410 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:16:28.410 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:28.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:28.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:28.415 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:16:28.895 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:16:28.948 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:16:28.951 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:16:28.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:28.953 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:16:28.970 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:28.970 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:28.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:28.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:28.973 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:28.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:28.973 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:28.973 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:28.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:28.994 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:28.994 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:28.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:28.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:29.372 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:16:29.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:29.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:29.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:29.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:29.399 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:29.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:29.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:29.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:29.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:29.401 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:29.401 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:29.401 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:29.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:29.415 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:29.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:29.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:29.419 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:29.419 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:29.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:29.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:29.422 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:29.849 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:16:29.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:29.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:29.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:29.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:29.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:29.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:29.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:29.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:29.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:29.892 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:29.892 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:29.892 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:29.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:29.952 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:29.952 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:16:29.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:29.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:30.327 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:16:30.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:30.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:30.418 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:30.422 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:30.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:30.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:30.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:30.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:30.599 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:30.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:30.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:30.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:30.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:30.618 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:30.618 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:30.618 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:30.618 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:30.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:30.666 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:30.666 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:16:30.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:30.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:30.805 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:16:31.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:31.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:31.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:31.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:31.086 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:31.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:31.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:31.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:31.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:31.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:31.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:31.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:31.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:31.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:31.141 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:31.141 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:31.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:31.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:31.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:31.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:31.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:31.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:31.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:31.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:31.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:31.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:31.267 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:31.267 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:31.267 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:31.267 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:31.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:31.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:31.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:31.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:31.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:31.282 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:16:31.416 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:31.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:31.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:31.423 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:31.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:31.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:31.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:31.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:31.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:31.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:31.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:31.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:31.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:31.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:31.745 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:31.745 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:31.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:31.752 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:31.752 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:16:31.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:31.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:31.759 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:16:32.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:32.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:32.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:32.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:32.155 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:32.172 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:32.172 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:32.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:32.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:32.173 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:32.173 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:32.173 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:32.173 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:32.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:32.177 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:32.177 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:16:32.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:32.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:32.228 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:16:32.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:32.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:32.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:32.424 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:32.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:32.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:32.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:32.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:32.621 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:32.628 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:32.628 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:32.628 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:32.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:32.629 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:16:32.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:16:32.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:16:32.629 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:16:32.629 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:16:32.629 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:16:32.629 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:16:32.629 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=905 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:32.629 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=905 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:32.629 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=905 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:32.629 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=905 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:32.629 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=905 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:32.629 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=905 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:32.629 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=905 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:37.632 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:16:37.632 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:16:37.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:16:37.635 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:16:37.636 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:16:37.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:16:37.644 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:16:37.646 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:16:37.646 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:37.647 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:16:37.647 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:16:37.651 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:16:37.652 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:16:37.652 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:16:37.652 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:37.653 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:16:37.653 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:16:37.654 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:16:37.654 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:16:37.654 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:37.655 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:16:37.655 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:16:37.655 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:16:37.655 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:37.655 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:16:37.655 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:16:37.655 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:16:37.656 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:16:37.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:37.657 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:16:37.657 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:16:37.657 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:16:37.657 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:37.658 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:16:37.658 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:16:37.658 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:16:37.658 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:16:37.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:37.660 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:16:37.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:16:37.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:16:37.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:16:37.660 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:16:37.661 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:16:37.661 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:16:37.661 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:37.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:37.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:37.666 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:16:38.150 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:16:38.192 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:16:38.194 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:16:38.197 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:16:38.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:38.221 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:38.221 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:38.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:38.224 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.224 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:38.224 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:38.224 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:38.224 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:38.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:38.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:38.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:38.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:38.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:38.312 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:38.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:38.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:38.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:38.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:38.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:38.332 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:38.332 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:38.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:38.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:38.390 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:38.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:38.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:38.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:38.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:38.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:38.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:38.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:38.465 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:38.465 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:38.465 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:38.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:38.478 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:38.478 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:16:38.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:38.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:38.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:38.570 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:38.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:38.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:38.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:38.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.590 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:38.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:38.590 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:38.590 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:38.622 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:16:38.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:38.630 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:38.630 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:16:38.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.664 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:38.665 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:38.665 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:38.668 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:38.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:38.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:38.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:38.692 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:38.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:38.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:38.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:38.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:38.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:38.712 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:38.712 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:38.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:38.769 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:38.769 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:38.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:38.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:38.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:38.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:38.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:38.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:38.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:38.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:38.872 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:38.872 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:38.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:38.913 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:38.913 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:38.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:38.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:39.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:39.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:39.089 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:39.089 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:39.099 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:16:39.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:39.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:39.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:39.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:39.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:39.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:39.111 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:39.111 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:39.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:39.156 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:39.156 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:16:39.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:39.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:39.575 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:16:39.665 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:39.666 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:39.666 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:39.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:39.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:39.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:39.732 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:39.732 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:39.732 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:39.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:39.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:39.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:39.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:39.752 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:39.752 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:39.752 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:39.752 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:39.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:39.758 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:39.758 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:16:39.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:39.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:39.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:39.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:39.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:39.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:39.968 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:39.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:39.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:39.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:39.977 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:39.980 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:16:39.981 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:16:39.981 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:16:39.981 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:16:39.981 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:16:39.981 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:16:39.981 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:16:39.982 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.982 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.982 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.982 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.982 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.982 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.982 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.982 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.982 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.983 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.983 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.983 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.983 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.983 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:39.983 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:44.980 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:16:44.980 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:16:44.981 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:16:44.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:16:44.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:16:44.987 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:16:44.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:16:44.995 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:16:44.995 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:44.995 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:16:44.996 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:16:44.997 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:16:44.998 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:16:44.998 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:16:44.998 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:44.998 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:16:44.998 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:16:44.999 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:16:44.999 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:16:44.999 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:44.999 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:16:44.999 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:16:45.000 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:16:45.000 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:45.000 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:16:45.000 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:16:45.000 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:16:45.000 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:16:45.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:45.001 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:16:45.001 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:16:45.001 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:16:45.001 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:16:45.001 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:16:45.001 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:16:45.001 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:16:45.001 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:16:45.001 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:45.003 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:16:45.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:16:45.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:16:45.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:16:45.003 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:16:45.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:16:45.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:16:45.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:16:45.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:16:45.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:16:45.004 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:16:45.004 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:16:45.004 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:45.004 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:16:45.005 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:16:45.005 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:16:45.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:45.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:45.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:45.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:45.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:16:45.009 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:16:45.493 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:16:45.521 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:16:45.522 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:16:45.523 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:16:45.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:45.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:45.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:45.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:45.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:45.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:45.543 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:45.543 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:45.543 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:45.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:45.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:45.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:45.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:45.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:45.966 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:16:46.006 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:46.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:46.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:46.010 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:46.444 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:16:46.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:46.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:46.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:46.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:46.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:46.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:46.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:46.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:46.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:46.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:46.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:46.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:46.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:46.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:46.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:46.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:46.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:46.921 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:16:47.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:47.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:47.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:47.010 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:47.399 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:16:47.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:47.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:47.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:47.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:47.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:47.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:47.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:47.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:47.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:47.465 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:47.465 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:47.465 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:47.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:47.502 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:47.502 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:16:47.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:47.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:47.878 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:16:48.008 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:48.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:48.009 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:48.011 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:48.356 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:16:48.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:48.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:48.657 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:48.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:48.658 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:48.679 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:48.679 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:48.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:48.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:48.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:48.681 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:48.681 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:48.681 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:48.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:48.742 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:48.742 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:16:48.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:48.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:48.834 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:16:49.010 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:49.010 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:49.010 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:49.012 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:49.312 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:16:49.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:49.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:49.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:49.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:49.633 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:49.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:49.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:49.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:49.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:49.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:49.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:49.654 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:49.654 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:49.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:49.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:49.695 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:49.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:49.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:49.790 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:16:50.011 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:50.011 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:50.011 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:50.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:50.268 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:16:50.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:50.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:50.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:50.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:50.328 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:50.329 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:50.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:50.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:50.330 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:50.330 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:50.330 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:50.331 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:50.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:50.372 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:50.372 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:50.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:50.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:50.746 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:16:51.224 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:16:51.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:51.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:51.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:51.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:51.267 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=1337 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:51.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:51.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:51.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:51.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:51.287 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:51.287 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:51.287 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:51.287 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:51.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:51.321 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:51.321 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:16:51.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:51.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:51.701 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:16:52.179 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:16:52.657 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:16:53.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:53.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:53.116 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:53.116 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:53.116 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:53.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:53.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:53.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:16:53.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:53.135 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:16:53.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:16:53.135 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:16:53.135 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:16:53.135 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:16:53.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:53.191 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:16:53.191 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:16:53.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:53.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:53.612 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:16:54.090 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:16:54.568 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:16:55.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:16:55.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:16:55.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:16:55.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:16:55.028 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:16:55.039 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:16:55.040 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:16:55.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:16:55.040 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:16:55.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:16:55.043 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:16:55.043 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:16:55.044 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:16:55.044 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:16:55.044 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:16:55.044 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:16:55.044 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2144 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:55.044 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2144 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:55.044 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2144 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:55.045 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2144 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:55.045 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2144 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:55.045 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2144 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:55.045 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2144 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:55.045 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2144 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:16:55.045 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2145 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:00.043 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:00.043 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:00.045 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:00.045 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:00.046 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:00.046 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:00.049 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:00.049 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:00.049 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:00.050 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:00.050 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:17:00.051 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:17:00.052 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:17:00.052 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:00.052 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:00.053 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:00.053 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:17:00.053 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:00.053 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:17:00.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:00.054 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:17:00.054 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:17:00.054 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:00.054 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:00.054 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:00.055 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:17:00.055 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:00.055 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:17:00.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:00.056 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:17:00.056 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:17:00.056 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:00.056 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:00.057 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:00.057 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:17:00.057 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:00.057 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:17:00.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:17:00.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:17:00.060 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:17:00.060 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:17:00.060 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:00.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:00.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:00.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:00.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:00.065 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:17:00.548 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:17:00.589 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:17:00.591 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:17:00.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:00.594 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:17:00.616 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:00.616 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:00.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:00.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:00.621 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:00.621 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:00.621 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:00.621 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:00.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:00.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:00.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:00.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:00.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:00.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:00.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:00.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:00.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:00.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:00.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:00.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:00.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:00.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:00.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:00.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:00.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:00.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:00.841 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:00.841 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:17:00.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:00.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:01.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:01.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:01.012 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:01.012 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:01.012 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:01.025 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:17:01.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:01.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:01.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:01.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:01.033 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:01.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:01.033 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:01.033 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:01.063 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:01.063 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:01.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:01.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:01.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:01.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:01.083 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:01.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:01.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:01.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:01.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:01.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:01.256 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:01.272 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:01.272 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:01.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:01.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:01.273 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:01.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:01.273 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:01.273 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:01.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:01.317 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:01.317 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:17:01.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:01.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:01.501 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:17:01.979 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:17:02.064 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:02.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:02.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:02.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:02.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:02.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:02.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:02.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:02.138 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:02.146 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:02.146 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:02.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:02.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:02.150 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:02.150 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:02.150 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:02.150 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:02.150 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:02.150 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:17:02.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:02.151 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.151 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.151 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.151 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.151 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.151 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.151 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.151 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.151 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:02.152 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:07.150 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:07.150 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:07.154 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:07.154 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:07.154 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:07.154 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:07.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:07.161 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:07.161 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:07.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:07.162 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:17:07.164 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:17:07.165 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:17:07.165 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:07.165 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:07.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:07.166 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:17:07.166 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:07.167 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:17:07.167 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:07.167 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:17:07.168 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:17:07.168 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:07.168 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:07.168 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:07.168 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:17:07.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:07.169 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:17:07.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:07.170 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:17:07.170 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:17:07.170 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:07.170 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:07.170 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:07.171 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:17:07.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:07.171 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:17:07.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:07.174 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:17:07.174 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:17:07.174 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:17:07.175 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:07.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:07.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:07.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:07.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:07.179 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:17:07.660 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:17:07.704 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:17:07.707 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:17:07.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:07.709 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:17:07.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:07.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:07.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:07.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:07.726 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:07.726 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:07.726 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:07.726 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:07.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:07.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:07.764 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:07.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:07.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:07.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:07.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:07.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:07.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:07.883 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:07.883 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:07.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:07.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:07.884 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:07.885 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:07.885 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:07.885 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:07.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:07.894 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:07.894 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:17:07.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:07.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:08.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:08.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:08.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:08.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:08.044 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:08.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:08.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:08.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:08.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:08.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:08.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:08.067 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:08.067 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:08.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:08.082 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:08.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:08.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:08.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:08.137 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:17:08.177 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:08.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:08.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:08.182 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:08.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:08.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:08.367 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:08.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:08.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:08.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:08.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:08.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:08.375 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:08.375 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:08.375 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:08.375 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:08.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:08.425 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:08.425 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:17:08.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:08.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:08.612 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:17:09.090 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:17:09.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:09.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:09.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:09.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:09.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:09.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:09.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:09.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:09.249 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:09.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:09.257 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:09.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:09.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:09.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:09.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:09.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:09.261 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:09.261 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:09.261 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:17:09.262 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:09.262 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:09.262 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:09.262 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:09.262 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:09.262 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:09.262 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:14.263 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:14.264 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:14.264 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:14.264 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:14.264 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:14.264 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:14.271 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:14.273 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:14.273 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:14.274 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:14.274 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:17:14.277 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:17:14.278 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:17:14.278 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:14.278 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:14.279 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:14.279 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:17:14.280 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:14.280 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:17:14.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:14.281 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:17:14.281 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:17:14.281 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:14.281 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:14.282 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:14.282 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:17:14.282 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:14.282 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:17:14.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:14.284 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:17:14.284 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:17:14.285 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:14.285 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:14.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:14.285 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:17:14.285 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:14.285 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:17:14.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:14.288 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:17:14.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:17:14.288 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:17:14.288 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:17:14.288 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:17:14.288 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:14.289 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:17:14.289 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:17:14.289 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:17:14.289 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:17:14.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:14.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:14.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:14.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:17:14.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:14.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:14.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:14.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:14.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:14.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:14.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:14.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:14.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:14.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:14.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:14.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:14.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:14.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:14.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:14.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:14.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:14.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:14.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:14.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:14.294 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:17:14.778 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:17:14.822 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:17:14.824 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:17:14.826 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:17:14.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:14.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:14.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:14.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:14.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:14.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:14.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:14.857 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:14.857 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:14.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:14.877 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:14.878 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:14.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:14.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:14.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:14.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:14.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:14.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:15.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:15.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:15.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:15.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:15.001 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:15.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:15.001 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:15.001 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:15.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:15.013 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:15.013 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:17:15.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:15.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:15.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:15.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:15.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:15.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:15.163 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:15.182 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:15.182 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:15.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:15.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:15.183 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:15.183 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:15.184 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:15.184 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:15.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:15.203 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:15.203 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:15.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:15.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:15.254 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:17:15.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:15.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:15.294 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:15.297 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:15.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:15.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:15.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:15.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:15.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:15.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:15.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:15.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:15.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:15.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:15.505 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:15.505 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:15.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:15.547 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:15.547 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:17:15.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:15.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:15.733 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:17:16.211 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:17:16.293 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:16.294 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:16.295 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:16.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:16.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:16.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:16.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:16.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:16.370 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:16.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:16.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:16.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:16.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:16.381 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:16.381 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:16.381 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:16.382 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:16.382 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:16.382 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:16.382 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:17:16.382 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.382 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.382 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.382 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.383 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.383 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.383 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.383 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.383 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.383 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.383 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.383 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.383 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.383 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:16.383 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:21.382 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:21.382 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:21.383 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:21.384 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:21.385 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:21.385 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:21.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:21.393 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:21.394 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:21.394 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:21.394 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:17:21.396 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:17:21.397 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:17:21.397 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:21.397 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:21.398 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:21.398 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:17:21.398 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:21.398 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:17:21.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:21.399 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:17:21.399 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:17:21.399 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:21.399 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:21.400 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:21.400 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:17:21.400 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:21.400 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:17:21.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:21.402 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:17:21.403 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:17:21.403 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:21.403 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:21.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:21.403 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:17:21.403 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:21.403 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:17:21.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:21.405 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:17:21.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:17:21.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:17:21.406 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:17:21.406 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:17:21.406 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:21.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:21.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:21.411 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:17:21.894 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:17:21.933 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:17:21.934 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:17:21.936 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:17:21.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:21.962 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:21.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:21.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:21.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:21.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:21.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:21.966 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:21.967 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:21.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:21.997 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:21.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:21.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:21.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:22.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:22.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:22.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:22.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:22.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:22.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:22.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:22.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:22.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:22.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:22.140 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:22.141 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:22.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:22.187 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:22.187 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:17:22.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:22.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:22.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:22.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:22.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:22.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:22.359 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:22.371 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:17:22.373 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:22.373 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:22.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:22.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:22.375 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:22.375 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:22.375 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:22.375 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:22.409 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:22.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:22.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:22.413 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:22.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:22.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:22.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:22.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:22.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:22.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:22.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:22.602 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:22.602 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:22.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:22.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:22.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:22.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:22.623 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:22.623 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:22.623 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:22.623 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:22.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:22.663 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:22.664 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:17:22.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:22.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:22.846 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:17:23.324 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:17:23.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:23.410 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:23.412 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:23.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:23.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:23.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:23.482 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:23.482 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:23.482 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:23.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:23.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:23.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:23.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:23.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:23.495 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:23.495 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:23.495 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:23.495 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:23.495 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:23.495 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:17:23.495 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:23.495 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:23.495 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:23.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:23.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:23.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=446 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:23.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:23.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:23.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:23.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:23.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:23.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:23.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:23.496 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=447 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:28.494 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:28.494 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:28.496 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:28.497 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:28.499 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:28.501 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:28.509 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:28.509 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:28.510 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:28.510 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:28.510 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:17:28.512 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:17:28.512 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:17:28.512 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:28.512 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:28.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:28.513 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:17:28.513 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:28.513 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:17:28.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:28.514 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:17:28.514 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:17:28.514 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:28.514 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:28.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:28.514 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:17:28.514 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:28.514 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:17:28.514 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:28.516 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:17:28.516 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:17:28.516 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:28.516 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:28.516 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:28.516 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:17:28.516 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:28.516 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:17:28.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:28.518 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:17:28.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:17:28.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:17:28.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:17:28.518 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:17:28.519 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:17:28.519 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:17:28.519 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:28.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:28.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:28.524 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:17:29.008 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:17:29.049 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:17:29.051 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:17:29.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:29.053 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:17:29.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:29.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:29.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:29.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:29.083 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:29.083 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:29.083 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:29.084 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:29.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:29.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:29.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:29.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:29.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:29.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:29.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:29.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:29.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:29.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:29.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:29.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:29.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:29.447 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:29.447 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:29.447 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:29.447 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:29.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:29.485 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:17:29.489 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:29.489 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:17:29.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:29.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:29.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:29.522 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:29.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:29.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:29.963 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:17:29.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:29.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:29.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:29.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:29.981 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:30.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:30.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:30.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:30.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:30.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:30.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:30.002 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:30.002 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:30.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:30.007 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:30.007 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:30.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:30.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:30.440 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:17:30.523 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:30.523 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:30.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:30.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:30.917 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:17:31.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:31.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:31.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:31.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:31.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:31.092 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:31.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:31.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:31.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:31.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:31.093 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:31.093 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:31.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:31.100 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:31.100 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:17:31.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:31.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:31.395 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:17:31.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:31.524 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:31.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:31.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:31.873 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:17:32.351 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:17:32.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:32.526 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:32.526 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:32.528 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:32.829 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:17:33.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:33.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:33.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:33.151 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:33.151 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:33.159 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:33.159 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:33.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:33.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:33.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:33.161 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:33.161 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:33.161 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:33.161 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:33.161 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:33.161 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:17:33.161 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:33.161 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:33.161 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:33.161 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:33.161 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:33.161 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:33.161 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:38.162 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:38.162 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:38.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:38.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:38.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:38.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:38.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:38.173 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:38.173 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:38.174 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:38.174 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:17:38.176 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:17:38.177 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:17:38.177 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:38.177 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:38.178 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:38.178 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:17:38.178 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:38.178 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:17:38.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:38.179 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:17:38.180 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:17:38.180 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:38.180 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:38.180 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:38.180 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:17:38.180 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:38.180 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:17:38.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:38.182 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:17:38.182 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:17:38.182 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:38.182 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:38.182 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:38.182 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:17:38.183 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:38.183 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:17:38.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:38.185 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:17:38.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:17:38.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:17:38.186 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:17:38.186 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:17:38.186 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:17:38.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:38.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:38.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:38.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:38.191 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:17:38.673 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:17:38.718 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:17:38.720 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:17:38.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:38.722 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:17:38.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:38.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:38.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:38.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:38.754 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:38.754 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:38.755 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:38.755 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:38.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:38.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:38.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:38.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:38.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:39.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:39.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:39.092 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:39.092 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:39.110 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:39.110 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:39.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:39.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:39.114 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:39.114 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:39.114 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:39.114 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:39.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:39.150 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:17:39.156 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:39.156 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:17:39.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:39.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:39.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:39.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:39.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:39.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:39.629 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:17:39.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:39.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:39.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:39.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:39.647 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:39.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:39.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:39.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:39.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:39.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:39.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:39.663 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:39.663 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:39.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:39.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:39.681 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:39.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:39.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:40.106 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:17:40.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:40.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:40.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:40.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:40.584 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:17:40.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:40.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:40.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:40.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:40.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:40.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:40.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:40.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:40.768 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:40.768 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:40.768 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:40.768 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:40.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:40.831 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:40.831 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:17:40.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:40.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:41.062 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:17:41.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:41.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:41.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:41.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:41.539 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:17:42.008 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:17:42.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:42.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:42.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:42.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:42.481 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:17:42.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:42.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:42.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:42.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:42.798 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:42.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:42.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:42.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:42.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:42.811 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:42.811 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:42.811 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:42.811 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:42.811 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:42.811 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:42.811 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:17:42.812 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=991 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:42.812 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=991 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:42.812 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:42.812 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:42.812 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:42.812 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:42.812 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:42.813 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:42.813 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:42.813 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:42.813 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:42.813 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:42.813 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:42.813 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:47.810 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:47.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:47.811 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:47.813 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:47.814 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:47.814 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:47.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:47.822 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:47.822 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:47.822 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:47.822 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:17:47.824 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:17:47.824 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:17:47.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:47.824 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:47.824 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:47.824 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:17:47.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:47.824 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:17:47.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:47.826 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:17:47.827 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:17:47.827 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:47.827 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:47.827 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:47.827 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:17:47.827 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:47.827 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:17:47.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:47.829 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:17:47.829 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:17:47.829 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:47.829 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:47.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:47.829 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:17:47.829 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:47.829 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:17:47.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:47.832 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:17:47.832 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:17:47.832 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:17:47.833 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:47.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:47.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:47.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:47.837 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:17:48.321 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:17:48.362 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:17:48.365 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:17:48.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:48.367 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:17:48.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:48.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:48.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:48.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:48.397 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:48.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:48.398 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:48.398 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:48.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:48.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:48.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:48.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:48.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:48.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:48.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:48.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:48.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:48.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:48.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:48.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:48.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:48.759 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:48.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:48.760 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:48.760 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:48.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:48.798 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:17:48.802 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:48.802 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:17:48.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:48.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:48.835 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:48.835 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:48.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:48.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:49.277 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:17:49.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:49.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:49.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:49.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:49.294 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:49.303 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:49.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:49.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:49.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:49.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:49.304 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:49.305 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:49.305 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:49.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:49.327 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:49.327 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:49.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:49.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:49.754 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:17:49.836 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:49.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:49.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:49.840 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:50.232 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:17:50.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:50.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:50.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:50.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:50.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:50.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:50.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:50.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:50.406 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:50.407 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:50.407 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:50.407 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:50.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:50.418 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:50.418 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:17:50.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:50.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:50.709 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:17:50.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:50.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:50.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:50.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:51.188 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:17:51.666 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:17:51.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:51.840 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:51.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:51.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:52.144 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:17:52.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:52.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:52.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:52.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:52.466 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:52.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:52.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:52.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:52.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:52.479 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:52.479 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:52.479 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:52.479 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:52.480 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:52.480 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:17:52.480 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:52.480 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:52.480 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:52.480 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:52.481 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:52.481 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:52.481 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:52.481 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:17:57.478 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:17:57.478 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:17:57.480 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:57.481 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:57.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:57.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:57.497 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:17:57.498 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:57.498 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:57.498 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:17:57.498 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:17:57.500 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:17:57.500 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:17:57.500 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:57.500 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:57.500 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:17:57.500 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:17:57.501 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:17:57.501 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:17:57.501 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:57.503 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:17:57.503 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:17:57.503 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:57.503 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:57.504 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:17:57.504 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:17:57.504 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:17:57.504 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:17:57.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:57.506 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:17:57.506 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:17:57.506 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:57.506 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:17:57.506 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:17:57.506 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:17:57.506 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:17:57.506 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:17:57.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:57.509 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:17:57.510 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:17:57.510 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:17:57.510 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:17:57.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:17:57.514 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:17:57.996 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:17:58.037 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:17:58.039 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:17:58.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:58.041 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:17:58.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:58.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:58.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:58.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:58.072 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:58.072 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:58.073 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:58.073 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:58.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:58.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:58.097 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:58.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:58.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:58.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:58.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:58.438 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:58.438 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:58.456 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:58.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:58.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:58.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:58.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:58.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:58.459 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:58.459 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:58.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:58.466 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:17:58.466 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:17:58.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:58.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:58.473 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:17:58.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:58.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:58.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:58.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:58.951 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:17:58.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:58.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:58.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:58.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:58.969 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:17:58.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:17:58.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:17:58.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:17:58.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:58.984 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:58.984 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:58.984 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:17:58.984 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:17:58.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:17:58.998 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:17:58.998 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:17:58.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:58.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:17:59.428 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:17:59.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:17:59.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:17:59.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:17:59.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:17:59.906 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:18:00.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:00.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:00.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:00.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:00.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:00.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:00.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:00.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:00.090 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:00.090 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:00.090 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:00.090 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:00.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:00.146 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:18:00.146 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:18:00.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:00.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:00.384 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:18:00.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:00.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:00.514 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:00.514 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:00.862 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:18:01.340 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:18:01.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:01.515 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:01.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:01.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:01.819 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:18:02.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:02.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:02.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:02.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:02.140 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:18:02.148 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:02.148 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:02.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:02.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:02.151 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:02.151 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:02.151 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:02.151 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:02.151 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:02.151 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:02.151 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:18:02.151 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:02.151 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=992 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.151 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:07.151 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:07.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:07.154 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:07.155 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:07.155 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:07.162 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:07.162 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:07.162 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:07.163 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:07.163 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:18:07.166 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:18:07.166 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:18:07.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:07.167 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:07.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:07.168 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:18:07.168 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:07.168 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:18:07.169 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:07.170 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:18:07.170 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:18:07.170 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:07.170 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:07.170 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:07.170 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:18:07.171 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:07.171 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:18:07.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:07.173 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:18:07.173 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:18:07.173 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:07.173 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:07.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:07.173 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:18:07.173 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:07.173 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:18:07.174 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:07.177 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:18:07.177 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:18:07.177 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:18:07.178 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:18:07.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:07.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:07.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:07.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:18:07.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:07.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:07.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:07.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:07.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:07.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:07.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:07.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:07.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:07.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:07.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:07.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:07.179 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:07.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:07.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:07.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:07.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:07.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:07.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:07.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:07.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:07.182 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:18:07.662 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:18:07.709 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:18:07.711 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:18:07.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:07.713 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:18:07.731 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:07.731 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:07.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:07.752 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:07.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:07.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:07.752 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:07.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:07.755 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:07.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:07.755 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:07.755 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:07.755 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:07.755 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:18:07.755 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.755 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.755 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.755 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.755 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.755 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.755 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.755 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.755 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.755 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.755 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.755 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.756 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:07.756 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:12.756 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:12.756 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:12.757 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:12.760 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:12.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:12.760 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:12.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:12.769 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:12.769 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:12.769 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:12.769 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:18:12.771 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:18:12.772 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:18:12.772 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:12.772 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:12.772 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:12.773 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:18:12.773 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:12.773 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:18:12.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:12.774 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:18:12.774 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:18:12.774 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:12.774 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:12.774 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:12.775 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:18:12.775 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:12.775 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:18:12.775 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:12.776 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:18:12.776 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:18:12.776 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:12.776 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:12.777 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:12.777 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:18:12.777 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:12.777 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:18:12.777 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:12.779 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:18:12.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:18:12.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:18:12.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:18:12.779 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:18:12.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:18:12.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:18:12.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:18:12.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:18:12.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:18:12.780 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:18:12.780 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:18:12.780 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:12.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:12.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:12.785 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:18:13.267 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:18:13.308 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:18:13.311 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:18:13.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:13.313 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:18:13.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:13.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:13.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:13.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:13.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:13.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:13.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:13.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:13.375 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:13.375 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:13.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:13.376 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:13.376 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:13.376 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:13.376 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:13.376 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:13.376 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:18:13.376 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:18.379 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:18.379 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:18.381 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:18.383 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:18.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:18.383 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:18.391 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:18.391 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:18.391 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:18.392 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:18.392 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:18:18.394 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:18:18.394 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:18:18.395 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:18.395 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:18.395 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:18.396 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:18:18.396 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:18.396 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:18:18.396 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:18.397 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:18:18.397 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:18:18.397 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:18.397 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:18.397 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:18.397 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:18:18.397 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:18.397 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:18:18.397 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:18.399 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:18:18.399 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:18:18.399 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:18.399 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:18.399 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:18.399 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:18:18.399 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:18.399 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:18:18.400 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:18.402 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:18:18.402 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:18:18.402 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:18:18.402 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:18.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:18.407 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:18:18.890 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:18:18.932 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:18:18.934 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:18:18.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:18.936 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:18:18.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:18.956 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:18.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:18.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:18.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:18.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:18.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:18.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:18.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:18.971 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:18.971 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:18.971 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:18.971 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:18:18.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:18.971 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:18.971 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:18.971 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:18.971 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:18.971 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:18.971 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:18.971 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:23.970 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:23.970 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:23.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:23.973 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:23.973 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:23.973 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:23.978 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:23.978 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:23.978 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:23.978 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:23.978 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:18:23.981 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:18:23.981 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:18:23.981 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:23.981 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:23.981 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:23.981 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:18:23.981 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:23.981 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:18:23.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:23.984 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:18:23.984 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:18:23.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:23.985 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:23.985 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:23.985 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:18:23.985 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:23.985 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:18:23.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:23.988 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:18:23.988 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:18:23.988 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:23.988 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:23.988 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:23.988 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:18:23.988 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:23.988 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:18:23.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:23.992 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:18:23.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:18:23.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:18:23.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:18:23.992 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:18:23.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:18:23.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:18:23.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:18:23.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:18:23.993 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:18:23.993 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:18:23.993 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:23.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:23.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:18:23.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:23.995 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:23.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:23.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:23.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:23.996 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:23.996 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:23.996 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:23.996 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:23.996 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:23.996 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:18:28.998 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:28.998 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:29.000 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:29.001 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:29.002 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:29.002 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:29.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:29.012 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:29.012 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:29.013 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:29.013 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:18:29.016 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:18:29.016 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:18:29.017 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:29.017 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:29.017 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:29.017 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:18:29.018 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:29.018 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:18:29.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:29.019 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:18:29.019 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:18:29.019 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:29.019 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:29.019 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:29.019 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:18:29.019 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:29.020 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:18:29.020 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:29.021 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:18:29.021 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:18:29.021 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:29.021 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:29.021 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:29.021 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:18:29.022 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:29.022 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:18:29.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:29.024 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:18:29.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:18:29.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:18:29.024 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:18:29.024 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:18:29.024 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:18:29.024 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:18:29.025 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:18:29.025 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:18:29.025 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:29.025 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:29.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:29.030 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:18:29.513 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:18:29.555 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:18:29.557 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:18:29.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:29.561 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:18:29.582 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:29.582 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:29.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:29.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:29.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:29.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:29.585 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:29.585 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:29.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:29.618 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:29.619 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:29.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:29.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:29.990 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:18:30.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:30.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:30.029 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:30.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:30.468 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:18:30.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:30.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:30.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:30.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:30.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:30.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:30.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:30.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:30.600 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:30.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:30.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:30.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:30.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:30.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:30.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:30.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:30.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:30.944 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:18:31.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:31.029 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:31.030 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:31.033 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:31.422 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:18:31.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:31.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:31.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:31.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:31.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:31.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:31.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:31.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:31.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:31.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:31.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:31.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:31.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:31.617 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:31.617 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:31.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:31.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:31.897 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:18:32.029 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:32.029 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:32.031 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:32.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:32.375 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:18:32.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:32.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:32.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:32.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:32.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:32.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:32.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:32.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:32.545 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:32.545 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:32.545 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:32.545 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:32.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:32.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:32.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:32.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:32.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:32.850 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:18:33.031 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:33.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:33.032 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:33.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:33.328 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:18:33.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:33.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:33.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:33.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:33.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:33.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:33.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:33.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:33.515 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:33.515 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:33.515 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:33.515 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:33.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:33.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:33.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:33.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:33.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:33.806 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:18:34.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:34.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:34.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:34.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:34.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:34.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:34.125 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:34.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:34.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:34.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:34.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:34.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:34.147 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:34.147 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:34.147 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:34.147 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:34.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:34.189 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:18:34.189 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 03:18:34.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:34.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:34.284 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:18:34.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:34.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:34.733 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:34.733 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:34.734 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:18:34.753 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:34.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:34.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:34.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:34.755 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:34.755 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:34.755 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:34.755 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:34.762 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:18:34.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:34.814 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:18:34.814 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-05 03:18:34.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:34.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:35.240 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:18:35.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:35.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:35.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:35.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:35.371 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:18:35.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:35.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:35.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:35.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:35.393 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:35.393 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:35.393 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:35.393 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:35.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:35.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:35.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:35.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:35.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:35.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:35.717 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:18:36.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:36.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:36.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:36.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:36.054 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:36.054 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:36.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:36.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:36.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:36.056 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:36.056 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:36.056 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:36.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:36.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:36.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:36.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:36.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:36.195 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:18:36.673 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:18:36.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:36.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:36.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:36.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:36.733 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:36.733 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:36.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:36.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:36.734 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:36.734 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:36.734 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:36.734 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:36.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:36.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:36.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:36.776 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:36.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:36.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:37.150 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:18:37.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:37.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:37.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:37.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:37.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:37.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:37.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:37.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:37.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:37.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:37.352 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:37.352 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:37.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:37.394 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:18:37.394 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:18:37.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:37.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:37.628 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:18:37.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:37.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:37.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:37.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:37.983 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:18:37.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:37.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:37.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:37.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:37.994 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:37.994 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:37.994 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:37.994 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:37.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:38.001 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:18:38.001 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:18:38.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:38.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:38.105 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:18:38.583 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:18:38.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:38.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:38.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:38.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:38.599 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:18:38.619 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:38.619 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:38.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:38.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:38.620 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:38.620 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:38.620 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:38.620 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:38.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:38.628 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:18:38.628 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:18:38.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:38.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:39.061 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:18:39.539 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:18:39.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:39.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:39.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:39.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:39.543 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:18:39.563 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:39.563 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:39.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:39.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:39.564 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:39.564 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:39.564 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:39.565 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:39.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:39.592 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:18:39.592 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:18:39.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:39.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:40.017 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:18:40.495 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:18:40.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:40.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:40.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:40.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:40.525 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:18:40.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:40.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:40.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:40.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:40.546 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:40.546 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:40.546 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:40.546 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:40.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:40.597 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:18:40.597 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:18:40.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:40.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:40.973 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:18:41.451 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:18:41.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:41.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:41.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:41.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:41.501 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:18:41.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:41.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:41.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:41.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:41.522 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:41.522 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:41.522 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:41.522 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:41.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:41.547 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:18:41.547 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:18:41.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:41.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:41.926 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:18:42.404 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:18:42.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:42.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:42.482 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:42.482 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:42.483 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:18:42.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:42.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:42.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:42.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:42.503 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:42.503 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:42.503 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:42.503 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:42.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:42.550 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:18:42.550 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:18:42.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:42.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:42.882 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:18:43.361 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:18:43.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:43.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:43.447 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:43.447 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:43.447 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:18:43.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:43.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:43.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:43.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:43.470 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:43.470 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:43.470 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:43.470 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:43.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:43.512 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:18:43.512 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:18:43.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:43.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:43.839 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:18:44.317 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:18:44.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:44.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:44.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:44.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:44.422 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:18:44.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:44.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:44.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:44.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:44.444 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:44.444 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:44.444 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:44.444 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:44.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:44.455 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:18:44.455 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:18:44.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:44.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:44.790 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:18:45.269 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:18:45.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:45.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:45.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:45.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:45.392 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:18:45.410 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:45.410 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:45.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:45.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:45.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:45.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:45.412 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:45.412 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:45.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:45.459 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:18:45.459 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:18:45.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:45.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:45.746 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:18:46.224 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:18:46.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:46.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:46.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:46.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:46.366 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:18:46.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:46.373 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:46.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:46.373 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:46.376 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:46.376 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:46.376 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:46.376 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:46.376 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:46.376 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:46.376 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:18:51.375 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:51.375 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:51.376 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:51.378 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:51.378 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:51.379 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:51.386 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:51.388 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:51.388 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:51.389 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:51.389 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:18:51.392 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:18:51.392 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:18:51.393 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:51.393 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:51.393 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:51.394 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:18:51.394 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:51.394 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:18:51.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:51.395 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:18:51.395 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:18:51.395 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:51.395 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:51.395 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:51.395 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:18:51.395 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:51.395 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:18:51.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:51.398 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:18:51.398 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:18:51.398 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:51.398 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:51.398 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:51.398 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:18:51.399 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:51.399 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:18:51.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:51.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:18:51.403 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:18:51.403 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:18:51.403 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:51.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:51.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:51.408 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:18:51.890 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:18:51.948 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:18:51.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:51.951 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:18:51.953 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:18:51.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:51.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:51.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:51.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:51.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:51.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:51.980 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:51.980 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:52.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:52.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:52.041 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:52.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:52.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:52.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:52.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:52.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:52.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:52.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.248 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:52.248 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:52.249 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:52.249 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:52.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:52.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:52.269 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:52.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.366 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:18:52.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:52.407 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:52.409 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:52.415 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:52.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:52.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:52.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:52.516 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:52.516 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:52.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:52.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:52.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:52.518 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:52.518 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:52.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:52.555 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:52.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:52.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:52.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:52.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:52.778 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:52.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:52.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:18:52.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.779 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:52.779 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:52.779 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:18:52.779 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:18:52.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:52.784 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:18:52.784 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:18:52.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:52.843 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:18:53.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:18:53.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:18:53.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:18:53.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:18:53.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:53.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:53.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:53.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:53.031 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:53.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:53.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:53.032 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:53.032 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:53.032 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:18:53.032 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:53.032 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=348 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:53.032 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=348 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:53.032 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=348 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:53.033 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=348 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:53.033 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=348 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:53.033 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=349 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:18:58.030 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:18:58.030 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:18:58.034 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:58.034 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:58.034 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:58.034 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:58.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:18:58.045 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:58.045 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:58.046 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:18:58.046 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:18:58.049 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:18:58.050 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:18:58.050 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:58.050 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:58.051 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:18:58.051 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:18:58.052 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:18:58.052 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:18:58.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:18:58.053 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:18:58.053 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:18:58.053 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:58.053 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:58.053 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:18:58.054 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:18:58.054 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:18:58.054 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:18:58.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:18:58.056 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:18:58.056 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:18:58.056 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:58.056 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:18:58.056 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:18:58.056 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:18:58.056 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:18:58.056 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:18:58.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:18:58.059 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:18:58.059 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:18:58.059 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:58.060 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:18:58.060 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:18:58.060 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:18:58.060 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:58.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:18:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:18:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:58.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:58.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:18:58.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:58.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:58.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:58.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:18:58.065 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:18:58.549 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:18:59.030 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:18:59.512 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:18:59.990 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:19:00.469 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:19:00.949 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:19:01.427 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:19:01.905 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:19:02.373 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:19:02.842 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:19:03.320 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:19:03.798 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:19:04.279 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:19:04.760 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:19:05.241 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:19:05.722 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:19:06.203 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:19:06.685 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:19:07.166 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:19:07.648 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:19:08.129 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:19:08.607 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:19:09.085 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:19:09.563 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:19:10.041 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:19:10.517 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:19:10.985 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:19:11.455 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:19:11.923 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:19:12.397 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:19:12.878 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:19:13.360 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:19:13.841 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:19:14.323 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:19:14.804 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:19:15.285 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:19:15.767 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:19:16.247 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:19:16.720 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:19:17.189 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:19:17.668 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:19:18.147 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:19:18.626 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:19:19.104 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:19:19.582 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:19:20.060 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:19:20.541 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:19:21.022 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:19:21.504 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:19:21.983 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:19:22.090 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:19:22.090 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:19:22.090 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:19:22.090 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:19:22.090 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:19:22.090 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:19:22.090 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:19:22.090 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:19:22.090 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:19:22.090 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:19:22.091 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:19:22.091 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:19:22.091 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:19:27.094 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:19:27.094 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:19:27.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:19:27.097 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:19:27.098 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:19:27.101 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:19:27.109 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:19:27.110 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:19:27.110 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:19:27.110 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:19:27.110 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:19:27.115 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:19:27.115 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:19:27.115 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:19:27.115 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:19:27.116 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:19:27.116 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:19:27.116 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:19:27.116 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:19:27.116 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:19:27.119 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:19:27.119 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:19:27.119 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:19:27.119 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:19:27.119 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:19:27.119 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:19:27.119 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:19:27.120 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:19:27.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:19:27.122 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:19:27.122 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:19:27.122 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:19:27.122 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:19:27.122 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:19:27.122 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:19:27.122 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:19:27.122 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:19:27.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:19:27.126 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:19:27.126 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:19:27.126 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:19:27.127 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:19:27.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:19:27.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:19:27.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:19:27.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:19:27.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:19:27.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:19:27.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:19:27.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:19:27.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:19:27.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:19:27.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:19:27.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:19:27.131 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:19:27.613 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:19:28.094 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:19:28.575 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:19:29.056 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:19:29.537 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:19:30.018 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:19:30.499 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:19:30.980 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:19:31.462 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:19:31.941 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:19:32.419 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:19:32.898 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:19:33.378 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:19:33.856 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:19:34.334 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:19:34.812 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:19:35.289 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:19:35.767 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:19:36.245 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:19:36.723 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:19:37.201 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:19:37.679 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:19:38.157 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:19:38.634 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:19:39.112 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:19:39.590 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:19:40.069 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:19:40.549 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:19:41.030 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:19:41.508 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:19:41.980 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:19:42.460 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:19:42.941 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:19:43.420 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:19:43.898 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:19:44.378 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:19:44.855 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:19:45.336 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:19:45.817 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:19:46.298 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:19:46.778 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:19:47.258 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:19:47.736 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:19:48.215 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:19:48.695 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:19:49.176 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:19:49.658 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:19:50.139 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:19:50.619 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:19:51.100 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:19:51.582 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:19:52.063 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:19:52.541 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:19:53.019 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:19:53.496 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:19:53.964 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 03:19:54.435 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 03:19:54.918 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 03:19:55.400 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 03:19:55.882 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 03:19:56.364 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 03:19:56.845 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 03:19:57.326 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 03:19:57.807 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 03:19:58.288 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 03:19:58.769 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 03:19:59.251 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 03:19:59.732 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 03:20:00.213 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 03:20:00.695 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 03:20:01.177 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 03:20:01.659 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 03:20:02.140 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 03:20:02.622 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 03:20:03.100 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 03:20:03.579 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 03:20:04.057 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 03:20:04.159 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:04.535 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 03:20:05.012 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 03:20:05.161 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:05.493 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 03:20:05.974 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 03:20:06.162 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:06.456 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 03:20:06.936 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 03:20:07.164 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:07.417 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 03:20:07.897 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 03:20:08.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:08.378 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 03:20:08.855 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 03:20:09.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:09.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:20:09.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:20:09.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:20:09.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:20:09.167 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:20:09.167 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:20:09.167 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:20:09.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=8943 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:09.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=8943 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:09.167 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=8943 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:14.167 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:20:14.167 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:20:14.168 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:20:14.169 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:20:14.169 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:20:14.170 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:20:14.175 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:20:14.175 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:20:14.175 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:20:14.175 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:20:14.175 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:20:14.176 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:20:14.176 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:20:14.176 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:20:14.176 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:20:14.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:20:14.176 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:20:14.176 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:20:14.176 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:20:14.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:20:14.177 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:20:14.177 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:20:14.177 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:20:14.177 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:20:14.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:20:14.177 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:20:14.177 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:20:14.177 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:20:14.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:20:14.178 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:20:14.178 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:20:14.178 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:20:14.178 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:20:14.178 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:20:14.178 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:20:14.178 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:20:14.178 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:20:14.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:20:14.180 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:20:14.180 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:20:14.180 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:14.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:14.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:14.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:14.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:14.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:14.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:14.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:14.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:14.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:14.185 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:20:14.669 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:20:14.705 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:20:14.708 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:14.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:14.708 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:20:14.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:14.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:14.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:20:14.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:14.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:20:14.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:20:14.724 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:20:14.724 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:20:14.760 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:14.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:14.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:20:14.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:20:14.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:14.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:15.143 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:20:15.182 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:20:15.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:15.183 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:20:15.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:20:15.621 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:20:15.637 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 03:20:16.099 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:20:16.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:20:16.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:16.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:20:16.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:20:16.577 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:20:17.055 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:20:17.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:20:17.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:17.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:20:17.186 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:20:17.533 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:20:18.010 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:20:18.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:18.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:20:18.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:20:18.186 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:20:18.488 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:20:18.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:18.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:18.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:18.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:18.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:18.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:18.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:20:18.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:18.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:20:18.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:20:18.585 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:20:18.585 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:20:18.629 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:18.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:18.641 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:20:18.641 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:20:18.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:18.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:18.966 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:20:19.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:20:19.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:20:19.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:19.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:20:19.444 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:20:19.923 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:20:20.401 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:20:20.880 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:20:21.358 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:20:21.837 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:20:22.315 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:20:22.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:22.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:22.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:22.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:22.706 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:20:22.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:22.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:22.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:20:22.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:22.726 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:20:22.726 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:20:22.726 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:20:22.726 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:20:22.732 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:22.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:22.736 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:20:22.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:20:22.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:22.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:22.792 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:20:23.229 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 03:20:23.269 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:20:23.746 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:20:24.224 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:20:24.701 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:20:25.179 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:20:25.657 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:20:26.135 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:20:26.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:26.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:26.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:26.577 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:26.600 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:26.600 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:26.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:20:26.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:26.603 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:20:26.603 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:20:26.603 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:20:26.603 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:20:26.611 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:20:26.659 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:26.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:26.677 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:20:26.677 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:20:26.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:26.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:27.088 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:20:27.567 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:20:28.045 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:20:28.435 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 03:20:28.524 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:20:29.002 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:20:29.392 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 03:20:29.480 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:20:29.958 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:20:30.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:30.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:30.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:30.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:30.354 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:20:30.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:30.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:20:30.363 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:20:30.363 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:20:30.366 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:20:30.366 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:20:30.367 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:20:30.367 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:20:30.367 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:20:30.367 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:20:30.367 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3455 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3455 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3455 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3455 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3455 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3455 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3455 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3456 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3456 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3456 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3456 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3456 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3456 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3456 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:30.367 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3456 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:20:35.367 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:20:35.367 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:20:35.368 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:20:35.370 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:20:35.371 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:20:35.371 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:20:35.379 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:20:35.380 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:20:35.380 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:20:35.381 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:20:35.381 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:20:35.385 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:20:35.385 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:20:35.385 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:20:35.386 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:20:35.386 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:20:35.386 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:20:35.387 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:20:35.387 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:20:35.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:20:35.387 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:20:35.388 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:20:35.388 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:20:35.388 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:20:35.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:20:35.388 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:20:35.388 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:20:35.388 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:20:35.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:20:35.390 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:20:35.390 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:20:35.390 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:20:35.390 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:20:35.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:20:35.390 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:20:35.390 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:20:35.390 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:20:35.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:20:35.393 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:20:35.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:20:35.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:20:35.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:20:35.393 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:20:35.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:20:35.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:20:35.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:20:35.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:20:35.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:35.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:35.393 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:20:35.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:20:35.394 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:20:35.394 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:20:35.394 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:35.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:35.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:35.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:35.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:35.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:20:35.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:20:35.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:20:35.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:35.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:35.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:35.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:20:35.399 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:20:35.882 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:20:35.922 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:20:35.924 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:35.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:35.927 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:20:35.962 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:35.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:35.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:20:35.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:35.964 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:20:35.964 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:20:35.964 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:20:35.964 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:20:35.975 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:35.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:35.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:20:35.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:20:35.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:35.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:36.359 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:20:36.360 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:36.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:36.397 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:20:36.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:20:36.401 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:20:36.837 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:20:36.853 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:36.856 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 03:20:37.315 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:20:37.340 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:37.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:37.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:20:37.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:20:37.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:20:37.793 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:20:37.827 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:38.270 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:20:38.314 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:38.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:38.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:20:38.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:20:38.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:20:38.748 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:20:38.801 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:39.227 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:20:39.289 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:39.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:20:39.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:39.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:20:39.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:20:39.704 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:20:39.776 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:40.182 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:20:40.263 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:40.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:20:40.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:20:40.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:20:40.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:20:40.660 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:20:40.750 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:41.138 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:20:41.237 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:41.616 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:20:41.724 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:42.093 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:20:42.211 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:42.571 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:20:42.698 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:43.049 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:20:43.185 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:43.527 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:20:43.672 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:43.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:43.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:43.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:43.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:43.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:43.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:43.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:20:43.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:43.702 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:20:43.702 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:20:43.702 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:20:43.702 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:20:43.708 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:43.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:43.714 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:20:43.714 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:20:43.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:43.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:43.999 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:20:44.393 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:44.477 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:20:44.881 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:44.955 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:20:45.368 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:45.434 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:20:45.856 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:45.912 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:20:46.344 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:46.391 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:20:46.832 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:46.869 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:20:47.320 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:47.348 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:20:47.806 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:47.825 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:20:48.294 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:48.304 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:20:48.782 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:48.782 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:20:49.261 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:20:49.277 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:49.740 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:20:49.766 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:50.218 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:20:50.253 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:50.697 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:20:50.740 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:51.176 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:20:51.229 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:51.654 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:20:51.716 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:51.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:51.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:51.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:51.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:51.725 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:20:51.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:51.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:51.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:20:51.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:51.742 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:20:51.742 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:20:51.742 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:20:51.742 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:20:51.743 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:51.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:51.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:20:51.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:20:51.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:51.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:52.090 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:52.131 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:20:52.566 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:52.569 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 03:20:52.608 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:20:53.044 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:53.086 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:20:53.521 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:53.563 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:20:53.999 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:54.040 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:20:54.476 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:54.518 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:20:54.954 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:54.995 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:20:55.431 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:55.473 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:20:55.909 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:55.950 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:20:56.386 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:56.428 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:20:56.863 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:56.906 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:20:57.342 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:57.383 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:20:57.819 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:57.861 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:20:58.296 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:58.338 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:20:58.774 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:58.816 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:20:59.252 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:59.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:59.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:59.258 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:59.258 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:59.271 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:20:59.271 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:20:59.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:20:59.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:59.273 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:20:59.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:20:59.273 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:20:59.273 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:20:59.284 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:59.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:20:59.292 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:20:59.292 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:20:59.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:59.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:20:59.293 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:20:59.683 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:20:59.770 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:21:00.161 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:00.248 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:21:00.639 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:00.643 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 03:21:00.727 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:21:01.118 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:01.203 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:21:01.592 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:01.681 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:21:02.072 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:02.159 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 03:21:02.549 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:02.551 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 03:21:02.638 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 03:21:03.028 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:03.116 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 03:21:03.506 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:03.508 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 03:21:03.594 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 03:21:03.984 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:04.071 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 03:21:04.462 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:04.464 [DEBUG] fake_trx.py:269 (MS@172.18.201.22:6700) Recv SETTA cmd
2026-03-05 03:21:04.550 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 03:21:04.948 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:05.028 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 03:21:05.418 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:05.506 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 03:21:05.896 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:05.984 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 03:21:06.375 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:06.462 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 03:21:06.852 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:06.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:06.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:06.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:06.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:06.857 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:21:06.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:06.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:06.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:06.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:06.865 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:06.865 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:06.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:06.865 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:21:06.865 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:21:06.865 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:21:06.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:06.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6719 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:06.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6719 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:06.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6719 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:06.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6719 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:06.865 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6719 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:11.868 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:21:11.868 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:21:11.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:11.871 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:11.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:11.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:11.880 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:11.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:21:11.882 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:11.883 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:21:11.883 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:21:11.886 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:21:11.887 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:21:11.887 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:21:11.887 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:11.888 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:11.888 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:21:11.889 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:21:11.889 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:21:11.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:11.889 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:21:11.889 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:21:11.890 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:21:11.890 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:11.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:11.890 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:21:11.890 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:21:11.890 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:21:11.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:11.892 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:21:11.892 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:21:11.892 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:21:11.892 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:11.892 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:11.892 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:21:11.892 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:21:11.892 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:21:11.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:11.895 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:21:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:21:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:21:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:21:11.895 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:21:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:21:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:21:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:21:11.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:21:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:11.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:11.895 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:21:11.896 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:21:11.896 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:21:11.896 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:11.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:11.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:11.901 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:21:12.384 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:21:12.416 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:21:12.417 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:12.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:12.418 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:21:12.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:12.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:12.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:21:12.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:12.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:12.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:12.437 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:21:12.437 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:21:12.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:12.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:12.490 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:12.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:12.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:12.861 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:21:12.899 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:12.899 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:12.900 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:12.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:13.339 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:21:13.817 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:21:13.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:13.900 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:13.900 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:13.903 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:14.295 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:21:14.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:14.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:14.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:14.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:14.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:14.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:14.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:21:14.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:14.620 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:14.620 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:14.620 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:21:14.620 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:21:14.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:14.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:14.681 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:14.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:14.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:14.773 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:21:14.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:14.901 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:14.901 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:14.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:15.251 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:21:15.728 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:21:15.901 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:15.901 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:15.901 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:15.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:16.206 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:21:16.684 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:21:16.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:16.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:16.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:16.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:16.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:16.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:16.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:21:16.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:16.809 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:16.809 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:16.809 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:21:16.809 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:21:16.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:16.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:16.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:16.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:16.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:16.901 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:16.902 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:16.902 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:16.905 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:17.159 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:21:17.637 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:21:18.115 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:21:18.593 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:21:18.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:18.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:18.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:18.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:18.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:18.925 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:18.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:18.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:18.928 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:18.928 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:18.928 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:18.928 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:21:18.928 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:21:18.928 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:21:18.928 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:18.928 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1502 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:18.928 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1502 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:18.928 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1502 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:18.928 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1502 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:18.928 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1502 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:18.928 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1502 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:18.928 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1502 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:18.928 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1502 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:23.928 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:21:23.928 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:21:23.930 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:23.932 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:23.932 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:23.932 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:23.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:23.944 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:21:23.944 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:23.945 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:21:23.945 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:21:23.949 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:21:23.949 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:21:23.950 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:21:23.950 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:23.950 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:23.951 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:21:23.951 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:21:23.951 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:21:23.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:23.952 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:21:23.952 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:21:23.952 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:21:23.953 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:23.953 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:23.953 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:21:23.953 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:21:23.953 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:21:23.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:23.955 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:21:23.955 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:21:23.955 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:21:23.955 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:23.955 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:23.955 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:21:23.955 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:21:23.955 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:21:23.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:23.958 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:21:23.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:23.959 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:21:23.959 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:21:23.959 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:21:23.959 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:23.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:23.961 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:23.961 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:23.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:23.961 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:23.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:23.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:23.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:23.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:23.964 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:21:24.449 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:21:24.492 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:21:24.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:24.494 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:24.496 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:21:24.521 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:24.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:24.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:21:24.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:24.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:24.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:24.525 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:21:24.525 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:21:24.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:24.555 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:21:24.555 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:21:24.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:24.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:24.926 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:21:24.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:24.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:24.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:24.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:25.405 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:21:25.883 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:21:25.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:25.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:25.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:25.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:26.362 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:21:26.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:26.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:26.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:26.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:26.659 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:21:26.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:26.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:26.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:21:26.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:26.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:26.682 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:26.682 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:21:26.682 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:21:26.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:26.689 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:21:26.689 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:21:26.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:26.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:26.840 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:21:26.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:26.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:26.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:26.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:27.318 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:21:27.796 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:21:27.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:27.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:27.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:27.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:28.274 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:21:28.752 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:21:28.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:28.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:28.796 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:28.796 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:28.796 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:21:28.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:28.805 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:28.805 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:28.805 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:28.807 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:28.807 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:28.807 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:28.807 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:28.807 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:21:28.807 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:21:28.807 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:21:28.807 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:28.807 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:28.807 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:28.807 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:28.807 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:28.807 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:28.807 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1033 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:33.808 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:21:33.808 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:21:33.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:33.814 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:33.814 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:33.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:33.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:33.823 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:21:33.823 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:33.823 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:21:33.823 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:21:33.826 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:21:33.826 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:21:33.826 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:21:33.826 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:33.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:33.827 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:21:33.827 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:21:33.827 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:21:33.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:33.830 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:21:33.830 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:21:33.830 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:21:33.830 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:33.830 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:33.830 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:21:33.830 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:21:33.830 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:21:33.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:33.833 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:21:33.833 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:21:33.833 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:21:33.833 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:33.833 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:33.833 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:21:33.833 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:21:33.833 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:21:33.833 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:33.836 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:21:33.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:21:33.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:21:33.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:21:33.836 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:21:33.837 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:21:33.837 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:21:33.837 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:21:33.837 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:33.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:33.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:33.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:21:33.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:33.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:33.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:33.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:33.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:33.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:33.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:33.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:33.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:33.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:33.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:33.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:33.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:33.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:33.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:33.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:33.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:33.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:33.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:33.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:33.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:33.842 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:21:34.327 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:21:34.363 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:21:34.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:34.365 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:34.366 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:21:34.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:34.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:34.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:21:34.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:34.383 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:34.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:34.383 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:21:34.383 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:21:34.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:34.431 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:34.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:34.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:34.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:34.804 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:21:34.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:34.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:34.842 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:34.845 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:35.282 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:21:35.760 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:21:35.841 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:35.843 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:35.843 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:35.847 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:36.238 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:21:36.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:36.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:36.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:36.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:36.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:36.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:36.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:21:36.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:36.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:36.537 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:36.537 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:21:36.537 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:21:36.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:36.574 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:36.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:36.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:36.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:36.716 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:21:36.842 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:36.844 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:36.844 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:36.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:37.194 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:21:37.671 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:21:37.842 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:37.845 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:37.845 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:37.850 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:38.149 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:21:38.626 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:21:38.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:38.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:38.676 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:38.676 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:38.691 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:38.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:38.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:21:38.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:38.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:38.692 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:38.693 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:21:38.693 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:21:38.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:38.732 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:38.732 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:38.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:38.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:38.843 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:38.846 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:38.847 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:38.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:39.103 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:21:39.581 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:21:40.058 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:21:40.536 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:21:40.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:40.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:40.840 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:40.840 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:40.848 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:40.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:40.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:40.849 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:40.850 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:40.851 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:40.851 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:40.851 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:40.851 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:21:40.851 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:21:40.851 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1497 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1498 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1498 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:40.851 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:45.852 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:21:45.852 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:21:45.854 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:45.856 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:45.881 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:45.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:45.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:45.885 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:21:45.885 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:45.886 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:21:45.886 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:21:45.891 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:21:45.891 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:21:45.892 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:21:45.892 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:45.892 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:45.893 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:21:45.893 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:21:45.894 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:21:45.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:45.895 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:21:45.895 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:21:45.896 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:21:45.896 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:45.896 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:45.896 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:21:45.896 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:21:45.896 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:21:45.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:45.898 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:21:45.898 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:21:45.898 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:21:45.898 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:45.898 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:45.898 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:21:45.898 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:21:45.898 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:21:45.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:45.901 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:21:45.901 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:21:45.901 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:21:45.902 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:45.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:45.906 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:21:46.390 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:21:46.434 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:21:46.436 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:46.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:46.438 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:21:46.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:46.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:46.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:21:46.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:46.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:46.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:46.463 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:21:46.463 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:21:46.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:46.493 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:21:46.493 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:21:46.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:46.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:46.868 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:21:46.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:46.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:46.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:46.905 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:47.346 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:21:47.815 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:21:47.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:47.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:47.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:47.906 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:48.284 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:21:48.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:48.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:48.620 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:48.620 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:48.620 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:21:48.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:48.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:48.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:21:48.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:48.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:48.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:48.636 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:21:48.636 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:21:48.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:48.663 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:21:48.664 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:21:48.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:48.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:48.755 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:21:48.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:48.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:48.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:48.907 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:49.225 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:21:49.696 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:21:49.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:49.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:49.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:49.907 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:50.167 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:21:50.638 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:21:50.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:50.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:50.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:50.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:50.761 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:21:50.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:50.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:50.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:50.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:50.774 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:50.774 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:50.774 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:50.774 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:50.774 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:21:50.774 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:21:50.774 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:21:55.774 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:21:55.774 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:21:55.775 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:55.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:55.778 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:55.778 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:55.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:55.787 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:21:55.787 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:55.788 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:21:55.788 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:21:55.791 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:21:55.791 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:21:55.792 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:21:55.792 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:55.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:55.792 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:21:55.793 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:21:55.793 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:21:55.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:55.793 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:21:55.794 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:21:55.794 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:21:55.794 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:55.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:55.794 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:21:55.794 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:21:55.794 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:21:55.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:55.796 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:21:55.796 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:21:55.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:21:55.796 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:21:55.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:55.796 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:21:55.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:21:55.796 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:21:55.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:55.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:21:55.800 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:21:55.800 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:21:55.800 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:55.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:55.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:55.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:55.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:21:55.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:21:55.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:55.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:21:55.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:55.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:55.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:55.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:21:55.804 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:21:56.289 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:21:56.326 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:21:56.328 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:21:56.330 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:21:56.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:56.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:56.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:56.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:21:56.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:56.355 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:56.356 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:56.356 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:21:56.356 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:21:56.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:56.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:21:56.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:21:56.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:56.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:56.766 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:21:56.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:56.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:56.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:56.805 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:57.244 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:21:57.723 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:21:57.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:57.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:57.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:57.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:58.201 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:21:58.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:21:58.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:21:58.582 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:21:58.582 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:21:58.588 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:21:58.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:21:58.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:21:58.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:21:58.589 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:21:58.589 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:21:58.589 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:21:58.589 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:21:58.589 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:21:58.589 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:21:58.589 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:21:58.589 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=596 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:58.589 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=596 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:58.589 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=596 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:58.589 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=596 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:58.589 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=596 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:58.589 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=596 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:21:58.589 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=596 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:03.592 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:03.593 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:03.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:03.595 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:03.595 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:03.596 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:03.605 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:03.606 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:03.607 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:03.607 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:03.607 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:22:03.610 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:22:03.610 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:22:03.611 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:03.611 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:03.611 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:03.612 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:22:03.612 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:03.612 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:22:03.613 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:03.613 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:22:03.613 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:22:03.613 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:03.614 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:03.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:03.614 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:22:03.614 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:03.614 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:22:03.614 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:03.616 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:22:03.616 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:22:03.616 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:03.616 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:03.616 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:03.616 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:22:03.616 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:03.616 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:22:03.616 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:03.619 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:22:03.619 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:22:03.619 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:22:03.620 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:03.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:03.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:03.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:03.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:03.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:03.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:03.624 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:22:04.108 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:22:04.145 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:22:04.148 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:22:04.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:04.151 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:22:04.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:04.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:04.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:22:04.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:04.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:04.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:04.183 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:22:04.183 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:22:04.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:04.215 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:22:04.215 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:22:04.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:04.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:04.585 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:22:04.623 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:04.623 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:04.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:04.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:05.064 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:22:05.543 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:22:05.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:05.624 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:05.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:05.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:06.021 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:22:06.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:06.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:06.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:06.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:06.417 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:22:06.425 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:06.425 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:06.425 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:06.425 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:06.429 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:06.429 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:06.429 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:06.429 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:06.429 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:06.429 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:06.429 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:22:06.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=599 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=599 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=599 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=599 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=599 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=599 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=599 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.430 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.431 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.431 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.431 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.431 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.431 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.431 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:06.431 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=600 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:11.429 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:11.429 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:11.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:11.432 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:11.433 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:11.433 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:11.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:11.443 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:11.443 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:11.443 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:11.443 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:22:11.446 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:22:11.447 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:22:11.447 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:11.447 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:11.448 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:11.448 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:22:11.448 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:11.448 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:22:11.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:11.449 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:22:11.449 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:22:11.449 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:11.449 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:11.449 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:11.450 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:22:11.450 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:11.450 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:22:11.450 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:11.452 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:22:11.452 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:22:11.452 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:11.452 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:11.452 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:11.452 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:22:11.452 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:11.452 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:22:11.452 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:22:11.455 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:22:11.455 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:22:11.455 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:22:11.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:11.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:11.460 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:22:11.943 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:22:11.981 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:22:11.983 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:22:11.985 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:22:11.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:12.010 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:12.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:12.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:22:12.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:12.068 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:12.069 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:12.069 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:22:12.069 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:22:12.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:12.091 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:12.091 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:12.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:12.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:12.421 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:22:12.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:12.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:12.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:12.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:12.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:12.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:12.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:12.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:12.511 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:12.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:12.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:22:12.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:12.521 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:12.521 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:12.521 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:22:12.522 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:22:12.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:12.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:12.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:12.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:12.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:12.896 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:22:12.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:12.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:12.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:12.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:12.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:12.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:12.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:12.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:12.963 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:12.963 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:12.963 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:12.963 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:12.963 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:12.963 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:12.963 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:22:12.964 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:12.964 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:12.964 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:12.964 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:12.964 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:12.964 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:17.964 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:17.964 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:17.966 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:17.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:17.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:17.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:17.976 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:17.977 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:17.977 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:17.978 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:17.978 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:22:17.981 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:22:17.981 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:22:17.981 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:17.981 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:17.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:17.982 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:22:17.983 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:17.983 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:22:17.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:17.983 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:22:17.983 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:22:17.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:17.984 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:17.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:17.984 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:22:17.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:17.984 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:22:17.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:17.986 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:22:17.986 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:22:17.986 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:17.986 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:17.986 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:17.986 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:22:17.986 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:17.986 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:22:17.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:17.989 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:22:17.989 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:22:17.989 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:22:17.990 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:17.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:17.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:17.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:17.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:17.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:17.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:17.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:17.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:17.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:17.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:17.994 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:22:18.477 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:22:18.519 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:22:18.521 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:22:18.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:18.523 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:22:18.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:18.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:18.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:22:18.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:18.578 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:18.578 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:18.578 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:22:18.578 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:22:18.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:18.625 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:18.626 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:18.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:18.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:18.954 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:22:18.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:18.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:18.994 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:18.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:18.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:19.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:19.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:19.007 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:19.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:19.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:19.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:22:19.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:19.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:19.031 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:19.031 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:22:19.031 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:22:19.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:19.049 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:19.049 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:19.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:19.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:19.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:19.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:19.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:19.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:19.431 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:22:19.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:19.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:19.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:19.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:19.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:19.437 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:19.437 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:19.437 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:19.437 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:19.437 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:19.437 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:22:24.443 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:24.443 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:24.443 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:24.443 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:24.443 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:24.443 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:24.450 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:24.452 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:24.452 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:24.453 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:24.453 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:22:24.457 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:22:24.457 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:22:24.458 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:24.458 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:24.458 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:24.459 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:22:24.459 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:24.460 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:22:24.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:24.462 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:22:24.462 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:22:24.462 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:24.462 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:24.462 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:24.462 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:22:24.462 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:24.463 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:22:24.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:24.465 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:22:24.465 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:22:24.465 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:24.465 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:24.465 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:24.465 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:22:24.465 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:24.465 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:22:24.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:24.469 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:22:24.469 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:22:24.469 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:22:24.470 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:24.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:24.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:24.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:24.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:24.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:24.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:24.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:24.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:24.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:24.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:24.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:24.474 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:22:24.958 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:22:25.006 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:22:25.008 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:22:25.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:25.010 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:22:25.031 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:25.031 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:25.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:22:25.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:25.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:25.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:25.078 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:22:25.078 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:22:25.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:25.106 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:25.107 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:25.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:25.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:25.436 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:22:25.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:25.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:25.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:25.480 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:25.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:25.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:25.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:25.489 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:25.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:25.506 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:25.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:22:25.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:25.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:25.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:25.517 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:22:25.517 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:22:25.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:25.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:25.530 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:25.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:25.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:25.911 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:22:25.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:25.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:25.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:25.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:25.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:25.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:25.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:25.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:25.966 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:25.966 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:25.966 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:25.966 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:25.966 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:25.966 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:22:25.966 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:25.966 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:25.966 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:25.966 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:25.966 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:25.966 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:25.966 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:25.966 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:25.966 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=319 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:30.967 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:30.967 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:30.968 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:30.970 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:30.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:30.971 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:30.978 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:30.978 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:30.978 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:30.979 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:30.979 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:22:30.981 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:22:30.981 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:22:30.981 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:30.982 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:30.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:30.982 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:22:30.983 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:30.983 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:22:30.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:30.984 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:22:30.984 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:22:30.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:30.984 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:30.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:30.984 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:22:30.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:30.984 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:22:30.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:30.986 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:22:30.986 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:22:30.986 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:30.986 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:30.986 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:30.986 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:22:30.986 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:30.986 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:22:30.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:30.989 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:22:30.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:22:30.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:22:30.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:22:30.989 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:22:30.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:22:30.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:22:30.990 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:22:30.990 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:22:30.990 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:30.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:30.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:30.995 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:22:31.479 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:22:31.514 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:22:31.515 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:22:31.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:31.516 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:22:31.531 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:31.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:31.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:22:31.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:31.577 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:31.578 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:31.579 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:22:31.579 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:22:31.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:31.627 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:22:31.627 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:22:31.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:31.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:31.957 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:22:31.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:31.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:31.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:31.998 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:32.435 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:22:32.913 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:22:32.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:32.995 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:32.997 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:32.999 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:33.392 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:22:33.870 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:22:33.995 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:33.995 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:33.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:34.000 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:34.348 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:22:34.825 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:22:34.996 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:34.996 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:34.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:35.001 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:35.304 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:22:35.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:35.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:35.632 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:22:35.634 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:35.634 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:35.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:35.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:35.635 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:35.635 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:35.635 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:35.635 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:35.635 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:35.635 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:35.635 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:22:40.638 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:40.638 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:40.642 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:40.642 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:40.642 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:40.642 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:40.651 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:40.653 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:40.653 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:40.654 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:40.654 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:22:40.658 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:22:40.658 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:22:40.659 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:40.659 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:40.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:40.659 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:22:40.659 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:40.659 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:22:40.659 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:40.662 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:22:40.662 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:22:40.662 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:40.662 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:40.662 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:40.662 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:22:40.662 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:40.662 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:22:40.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:40.665 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:22:40.665 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:22:40.665 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:40.665 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:40.665 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:40.665 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:22:40.665 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:40.665 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:22:40.665 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:40.668 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:22:40.668 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:22:40.668 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:22:40.668 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:22:40.668 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:40.669 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:22:40.669 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:22:40.669 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:22:40.669 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:40.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:40.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:40.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:40.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:40.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:40.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:40.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:40.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:40.674 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:22:41.155 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:22:41.195 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:22:41.196 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:22:41.198 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:22:41.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:41.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:41.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:41.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:22:41.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:41.235 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:41.235 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:41.235 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:22:41.235 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:22:41.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:41.255 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:41.256 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:41.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:41.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:41.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:41.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:41.477 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:41.477 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:41.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:41.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:41.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:22:41.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:41.503 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:41.503 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:41.503 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:22:41.503 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:22:41.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:41.536 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:41.537 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:41.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:41.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:41.632 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:22:41.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:41.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:41.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:41.677 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:41.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:41.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:41.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:41.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:41.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:41.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:41.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:41.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:41.774 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:41.775 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:41.775 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:41.775 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:41.775 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:41.775 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:41.775 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=236 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:41.775 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=237 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:46.775 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:46.775 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:46.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:46.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:46.777 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:46.778 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:46.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:46.781 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:46.781 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:46.781 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:46.782 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:22:46.783 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:22:46.783 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:22:46.783 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:46.783 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:46.783 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:46.783 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:22:46.784 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:46.784 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:22:46.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:46.785 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:22:46.785 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:22:46.785 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:46.785 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:46.785 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:46.785 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:22:46.786 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:46.786 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:22:46.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:46.787 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:22:46.787 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:22:46.787 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:46.787 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:46.787 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:46.787 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:22:46.787 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:46.787 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:22:46.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:46.789 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:22:46.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:22:46.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:22:46.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:22:46.789 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:22:46.790 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:22:46.790 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:22:46.790 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:46.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:46.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:46.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:46.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:46.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:46.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:46.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:46.795 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:22:47.278 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:22:47.317 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:22:47.318 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:22:47.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:47.319 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:22:47.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:47.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:47.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:22:47.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:47.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:47.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:47.385 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:22:47.385 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:22:47.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:47.426 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:22:47.427 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:22:47.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:47.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:47.756 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:22:47.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:47.796 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:47.796 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:47.798 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:48.234 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:22:48.712 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:22:48.796 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:48.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:48.797 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:48.799 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:49.191 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:22:49.669 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:22:49.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:49.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:49.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:49.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:50.148 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:22:50.626 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:22:50.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:50.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:50.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:50.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:51.104 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:22:51.432 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:51.432 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:51.432 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:22:51.434 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:51.435 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:51.435 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:51.435 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:51.435 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:51.435 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:51.435 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:51.435 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:51.435 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:51.435 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:22:51.435 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:51.435 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=991 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:51.435 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=991 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:51.435 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=991 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:51.435 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=991 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:51.436 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=991 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:51.436 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=991 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:51.436 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=991 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:56.439 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:56.439 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:56.440 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:56.442 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:56.443 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:56.443 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:56.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:56.454 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:56.454 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:56.454 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:22:56.454 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:22:56.458 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:22:56.459 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:22:56.459 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:56.459 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:56.459 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:56.460 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:22:56.460 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:22:56.460 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:22:56.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:56.462 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:22:56.462 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:22:56.462 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:56.462 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:56.462 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:56.463 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:22:56.463 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:22:56.463 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:22:56.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:56.465 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:22:56.465 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:22:56.465 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:56.465 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:22:56.465 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:56.465 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:22:56.465 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:22:56.465 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:22:56.465 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:56.468 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:22:56.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:22:56.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:22:56.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:22:56.468 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:22:56.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:22:56.469 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:22:56.469 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:22:56.469 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:56.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:56.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:56.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:22:56.474 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:22:56.958 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:22:57.003 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:22:57.006 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:22:57.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:57.008 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:22:57.020 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:57.020 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:57.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:22:57.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:57.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:57.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:57.052 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:22:57.052 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:22:57.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:57.104 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:22:57.104 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:22:57.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:57.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:57.434 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:22:57.472 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:57.473 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:57.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:57.477 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:57.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:22:57.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:22:57.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:22:57.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:22:57.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:22:57.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:22:57.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:22:57.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:22:57.841 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:22:57.841 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:22:57.841 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:22:57.841 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:22:57.841 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:22:57.841 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:22:57.841 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:22:57.841 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:02.842 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:02.842 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:02.844 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:02.845 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:02.846 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:02.846 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:02.857 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:02.857 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:02.858 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:02.858 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:02.858 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:23:02.859 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:23:02.859 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:23:02.860 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:02.860 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:02.860 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:02.860 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:23:02.861 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:02.861 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:23:02.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:02.861 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:23:02.861 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:23:02.861 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:02.861 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:02.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:02.862 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:23:02.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:02.862 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:23:02.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:02.863 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:23:02.863 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:23:02.863 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:02.863 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:02.863 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:02.863 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:23:02.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:02.864 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:23:02.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:23:02.866 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:23:02.866 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:23:02.866 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:23:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:02.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:02.871 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:23:03.355 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:23:03.396 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:23:03.398 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:23:03.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:03.400 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:23:03.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:03.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:03.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:23:03.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:03.428 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:23:03.429 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:23:03.429 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:23:03.429 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:23:03.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:03.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:23:03.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:23:03.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:03.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:03.832 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:23:03.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:03.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:03.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:03.872 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:04.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:04.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:04.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:04.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:04.175 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:04.175 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:04.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:04.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:04.178 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:04.178 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:04.178 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:04.178 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:04.178 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:04.178 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:04.178 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:23:04.178 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=280 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=280 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=280 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=280 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=280 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=280 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=280 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:04.179 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=281 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:09.181 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:09.182 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:09.182 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:09.182 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:09.182 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:09.182 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:09.188 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:09.188 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:09.188 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:09.188 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:09.188 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:23:09.192 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:23:09.192 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:23:09.192 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:09.192 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:09.192 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:09.192 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:23:09.193 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:09.193 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:23:09.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:09.195 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:23:09.196 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:23:09.196 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:09.196 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:09.196 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:09.196 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:23:09.196 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:09.196 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:23:09.196 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:09.198 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:23:09.199 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:23:09.199 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:09.199 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:09.199 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:09.199 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:23:09.199 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:09.199 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:23:09.199 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:09.202 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:23:09.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:23:09.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:23:09.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:23:09.202 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:23:09.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:23:09.203 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:23:09.203 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:23:09.203 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:09.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:09.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:09.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:09.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:09.208 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:23:09.692 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:23:09.740 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:23:09.742 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:23:09.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:09.744 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:23:09.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:09.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:09.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:23:09.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:09.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:23:09.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:23:09.805 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:23:09.805 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:23:09.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:09.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:23:09.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:23:09.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:09.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:10.168 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:23:10.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:10.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:10.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:10.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:10.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:10.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:10.563 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:10.563 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:10.572 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:10.572 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:10.572 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:10.573 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:10.576 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:10.576 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:10.576 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:10.576 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:10.576 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:10.576 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:23:10.577 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:10.577 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:10.577 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:10.577 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:10.577 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:10.577 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:10.577 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:10.577 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:15.574 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:15.575 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:15.576 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:15.577 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:15.578 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:15.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:15.583 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:15.584 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:15.585 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:15.585 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:15.585 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:23:15.588 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:23:15.588 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:23:15.589 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:15.589 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:15.589 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:15.589 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:23:15.589 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:15.589 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:23:15.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:15.591 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:23:15.591 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:23:15.591 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:15.592 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:15.592 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:15.592 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:23:15.592 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:15.592 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:23:15.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:15.593 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:23:15.593 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:23:15.594 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:15.594 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:15.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:15.594 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:23:15.594 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:15.594 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:23:15.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:15.596 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:23:15.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:23:15.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:23:15.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:23:15.596 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:23:15.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:23:15.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:23:15.597 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:23:15.597 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:23:15.597 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:15.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:15.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:15.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:15.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:15.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:15.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:15.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:15.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:15.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:15.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:15.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:15.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:15.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:15.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:15.602 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:23:16.086 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:23:16.123 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:23:16.124 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:23:16.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:16.125 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:23:16.143 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:16.143 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:16.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:23:16.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:16.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:23:16.191 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:23:16.191 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:23:16.191 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:23:16.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:16.234 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:23:16.234 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:23:16.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:16.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:16.563 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:23:16.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:16.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:16.602 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:16.604 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:17.042 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:23:17.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:17.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:17.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:17.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:17.100 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:23:17.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:17.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:17.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:17.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:17.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:17.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:17.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:17.112 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:17.112 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:17.112 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:23:17.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:17.112 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:22.113 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:22.113 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:22.115 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:22.116 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:22.117 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:22.118 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:22.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:22.127 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:22.128 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:22.128 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:22.128 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:23:22.132 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:23:22.133 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:23:22.133 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:22.133 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:22.134 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:22.134 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:23:22.134 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:22.134 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:23:22.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:22.135 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:23:22.136 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:23:22.136 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:22.136 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:22.136 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:22.136 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:23:22.136 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:22.136 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:23:22.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:22.138 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:23:22.138 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:23:22.138 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:22.138 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:22.138 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:22.138 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:23:22.138 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:22.138 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:23:22.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:22.141 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:23:22.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:23:22.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:23:22.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:23:22.141 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:23:22.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:23:22.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:23:22.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:23:22.142 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:23:22.142 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:23:22.142 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:22.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:22.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:22.147 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:23:22.632 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:23:22.674 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:23:22.675 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:23:22.676 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:23:22.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:22.694 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:22.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:22.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:23:22.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:22.734 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:23:22.734 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:23:22.734 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:23:22.735 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:23:22.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:22.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:23:22.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:23:22.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:22.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:23.109 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:23:23.145 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:23.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:23.147 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:23.151 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:23.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:23.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:23.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:23.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:23.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:23.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:23.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:23.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:23.516 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:23.516 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:23.517 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:23.517 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:23.517 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:23.517 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:23:23.517 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:23.517 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.518 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.518 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.518 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.518 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.518 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.518 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.518 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.518 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.518 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.518 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.518 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.519 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.519 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:23.519 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:28.516 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:28.516 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:28.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:28.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:28.520 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:28.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:28.530 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:28.531 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:28.531 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:28.532 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:28.532 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:23:28.536 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:23:28.537 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:23:28.537 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:28.537 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:28.537 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:28.537 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:23:28.537 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:28.537 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:23:28.537 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:28.540 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:23:28.540 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:23:28.540 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:28.540 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:28.540 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:28.540 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:23:28.541 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:28.541 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:23:28.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:28.543 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:23:28.543 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:23:28.543 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:28.543 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:28.543 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:28.543 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:23:28.543 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:28.543 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:23:28.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:28.546 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:23:28.546 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:23:28.546 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:23:28.546 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:23:28.546 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:23:28.547 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:23:28.547 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:23:28.547 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:28.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:28.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:28.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:28.552 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:23:29.037 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:23:29.071 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:23:29.073 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:23:29.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:29.075 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:23:29.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:29.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:29.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:23:29.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:29.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:23:29.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:23:29.142 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:23:29.142 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:23:29.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:29.184 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:23:29.184 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:23:29.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:29.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:29.514 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:23:29.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:29.551 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:29.551 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:29.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:29.992 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:23:30.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:30.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:30.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:30.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:30.049 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:23:30.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:30.058 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:30.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:30.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:30.060 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:30.060 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:30.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:30.060 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:30.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:30.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:30.060 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:23:30.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:30.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:30.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:30.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:30.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:30.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:30.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=322 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:35.062 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:35.062 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:35.066 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:35.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:35.066 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:35.066 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:35.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:35.077 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:35.077 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:35.078 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:35.078 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:23:35.083 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:23:35.083 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:23:35.083 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:35.083 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:35.083 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:35.084 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:23:35.084 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:35.084 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:23:35.084 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:35.087 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:23:35.087 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:23:35.087 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:35.087 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:35.087 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:35.087 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:23:35.087 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:35.087 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:23:35.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:35.090 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:23:35.090 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:23:35.090 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:35.090 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:35.090 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:35.090 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:23:35.090 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:35.090 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:23:35.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:35.093 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:23:35.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:23:35.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:23:35.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:35.094 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:23:35.094 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:23:35.094 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:23:35.094 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:35.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:35.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:35.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:35.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:35.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:35.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:35.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:35.099 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:23:35.583 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:23:35.626 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:23:35.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:35.629 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:23:35.632 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:23:35.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:35.656 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:35.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:23:35.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:35.659 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:23:35.660 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:23:35.660 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:23:35.660 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:23:36.060 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:23:36.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:36.097 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:36.098 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:36.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:36.538 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:23:36.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:36.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:36.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:36.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:36.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:36.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:36.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:23:36.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:36.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:23:36.833 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:23:36.833 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:23:36.833 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:23:37.015 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:23:37.098 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:37.098 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:37.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:37.103 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:37.493 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:23:37.877 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 03:23:37.970 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:23:38.007 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 03:23:38.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:38.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:38.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:38.020 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:38.021 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:38.021 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:38.024 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:38.024 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:38.024 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:38.025 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:38.025 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:38.025 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:38.025 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:23:38.025 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:38.025 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:38.026 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:38.026 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:38.026 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:38.026 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=625 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:23:43.023 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:43.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:43.025 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:43.026 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:43.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:43.027 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:43.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:43.037 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:43.037 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:43.037 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:43.038 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:23:43.040 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:23:43.041 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:23:43.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:43.041 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:43.042 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:43.042 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:23:43.043 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:43.043 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:23:43.043 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:43.043 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:23:43.044 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:23:43.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:43.044 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:43.044 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:43.044 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:23:43.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:43.044 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:23:43.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:43.046 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:23:43.046 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:23:43.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:43.046 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:43.046 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:43.046 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:23:43.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:43.046 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:23:43.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:43.049 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:23:43.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:23:43.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:23:43.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:23:43.049 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:23:43.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:23:43.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:23:43.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:23:43.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:23:43.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:23:43.050 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:23:43.050 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:23:43.050 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:43.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:43.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:43.055 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:23:43.539 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:23:43.574 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:23:43.575 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:23:43.576 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:23:43.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:43.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:43.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:43.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:23:43.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:43.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:23:43.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:23:43.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:23:43.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:23:44.016 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:23:44.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:44.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:44.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:44.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:44.494 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:23:44.971 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:23:45.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:45.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:45.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:45.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:45.449 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:23:45.927 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:23:46.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:46.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:46.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:46.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:46.405 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:23:46.882 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:23:47.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:47.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:47.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:47.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:47.360 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:23:47.838 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:23:48.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:48.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:48.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:48.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:48.315 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:23:48.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 03:23:48.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:23:48.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:23:48.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:48.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:48.794 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:23:49.272 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:23:49.750 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:23:50.229 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:23:50.707 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:23:51.186 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:23:51.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:51.307 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:51.311 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:51.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:51.311 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:51.311 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:51.312 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:51.312 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:51.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:51.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:51.312 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:51.312 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:51.312 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:23:56.315 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:23:56.315 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:23:56.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:56.318 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:56.319 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:56.319 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:56.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:23:56.325 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:56.325 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:56.325 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:23:56.325 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:23:56.328 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:23:56.328 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:23:56.328 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:56.328 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:56.328 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:23:56.329 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:23:56.329 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:23:56.329 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:23:56.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:56.332 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:23:56.332 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:23:56.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:56.332 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:56.332 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:23:56.332 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:23:56.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:23:56.332 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:23:56.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:56.335 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:23:56.335 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:23:56.335 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:56.335 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:23:56.335 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:23:56.335 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:23:56.335 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:23:56.335 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:23:56.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:56.339 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:23:56.339 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:23:56.339 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:23:56.340 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:23:56.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:56.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:56.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:56.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:23:56.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:56.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:56.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:56.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:56.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:56.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:56.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:56.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:56.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:56.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:56.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:56.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:56.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:56.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:23:56.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:56.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:56.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:23:56.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:56.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:23:56.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:56.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:56.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:23:56.345 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:23:56.828 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:23:56.868 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:23:56.869 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:23:56.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:23:56.870 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:23:56.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:23:56.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:23:56.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:23:56.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:23:56.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:23:56.894 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:23:56.894 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:23:56.894 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:23:57.305 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:23:57.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:57.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:57.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:57.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:57.783 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:23:58.260 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:23:58.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:58.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:58.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:58.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:58.737 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:23:59.209 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:23:59.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:23:59.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:23:59.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:23:59.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:23:59.687 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:24:00.165 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:24:00.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:00.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:00.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:00.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:00.642 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:24:01.119 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:24:01.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:01.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:01.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:01.351 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:01.597 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:24:01.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 03:24:01.626 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:24:01.627 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:24:01.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:24:01.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:24:02.075 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:24:02.553 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:24:03.032 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:24:03.526 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:24:04.004 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:24:04.483 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:24:04.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:24:04.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:24:04.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:04.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:04.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:04.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:04.595 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:24:04.595 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:24:04.595 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:24:04.595 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:24:04.595 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:24:04.595 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:24:04.595 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:24:04.595 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1760 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:04.595 [WARNING] transceiver.py:257 (TRX3@172.18.201.20:5700/3) RX TRXD message (ver=1 fn=1760 tn=0 bl=148 pwr=8), but transceiver is not running => dropping...
2026-03-05 03:24:04.595 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1760 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:04.595 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1760 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:04.595 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1760 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:04.595 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1760 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:04.595 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1760 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:04.595 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1760 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:04.595 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1760 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:09.597 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:24:09.597 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:24:09.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:24:09.600 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:24:09.601 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:24:09.601 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:24:09.609 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:24:09.611 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:24:09.611 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:09.611 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:24:09.611 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:24:09.614 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:24:09.615 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:24:09.615 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:24:09.615 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:09.616 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:24:09.616 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:24:09.617 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:24:09.617 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:24:09.617 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:09.618 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:24:09.618 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:24:09.618 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:24:09.618 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:09.619 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:24:09.619 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:24:09.619 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:24:09.619 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:24:09.619 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:09.621 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:24:09.621 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:24:09.621 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:24:09.621 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:09.621 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:24:09.621 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:24:09.621 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:24:09.621 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:24:09.622 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:09.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:09.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:09.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:09.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:09.626 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:24:09.626 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:24:09.626 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:24:09.626 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:24:09.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:09.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:09.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:09.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:24:09.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:09.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:09.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:09.631 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:24:10.114 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:24:10.155 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:24:10.156 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:24:10.157 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:24:10.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:24:10.171 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:24:10.171 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:24:10.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:24:10.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:24:10.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:24:10.176 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:24:10.176 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:24:10.176 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:24:10.592 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:24:10.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:10.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:10.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:10.636 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:11.069 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:24:11.547 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:24:11.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:11.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:11.633 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:11.637 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:12.025 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:24:12.502 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:24:12.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:12.631 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:12.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:12.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:12.979 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:24:13.457 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:24:13.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:13.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:13.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:13.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:13.935 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:24:14.413 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:24:14.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:14.633 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:14.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:14.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:14.891 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:24:14.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 03:24:14.918 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:24:14.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:24:14.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:24:14.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:24:15.369 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:24:15.841 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:24:16.312 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:24:16.785 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:24:17.263 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:24:17.737 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:24:17.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:24:17.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:24:17.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:17.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:17.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:17.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:17.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:24:17.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:24:17.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:24:17.886 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:24:17.886 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:24:17.886 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:24:17.886 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:24:22.888 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:24:22.888 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:24:22.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:24:22.891 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:24:22.891 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:24:22.891 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:24:22.896 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:24:22.896 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:24:22.896 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:22.896 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:24:22.897 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:24:22.898 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:24:22.899 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:24:22.899 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:24:22.899 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:22.899 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:24:22.900 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:24:22.900 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:24:22.900 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:24:22.900 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:22.901 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:24:22.901 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:24:22.901 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:24:22.901 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:22.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:24:22.901 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:24:22.901 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:24:22.901 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:24:22.901 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:22.903 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:24:22.903 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:24:22.903 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:24:22.903 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:22.903 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:24:22.903 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:24:22.903 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:24:22.903 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:24:22.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:22.906 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:24:22.907 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:24:22.907 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:24:22.907 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:22.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:22.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:22.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:22.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:22.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:22.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:22.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:22.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:22.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:22.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:22.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:22.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:22.912 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:24:23.393 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:24:23.433 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:24:23.436 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:24:23.438 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:24:23.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:24:23.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:24:23.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:24:23.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:24:23.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:24:23.471 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:24:23.471 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:24:23.471 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:24:23.471 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:24:23.871 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:24:23.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:23.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:23.911 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:23.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:24.348 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:24:24.826 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:24:24.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:24.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:24.912 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:24.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:25.304 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:24:25.782 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:24:25.911 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:25.911 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:25.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:25.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:26.259 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:24:26.736 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:24:26.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:26.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:26.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:26.916 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:27.214 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:24:27.692 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:24:27.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:27.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:27.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:27.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:28.169 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:24:28.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 03:24:28.196 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:24:28.197 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:24:28.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:24:28.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:24:28.648 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:24:29.126 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:24:29.604 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:24:30.082 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:24:30.555 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:24:31.025 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:24:31.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:24:31.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:24:31.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:31.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:31.165 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:31.165 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:31.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:24:31.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:24:31.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:24:31.166 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:24:31.166 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:24:31.166 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:24:31.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:24:36.168 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:24:36.168 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:24:36.169 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:24:36.171 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:24:36.172 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:24:36.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:24:36.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:24:36.180 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:24:36.180 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:36.181 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:24:36.181 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:24:36.184 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:24:36.184 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:24:36.184 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:24:36.184 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:36.184 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:24:36.185 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:24:36.185 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:24:36.185 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:24:36.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:36.186 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:24:36.187 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:24:36.187 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:24:36.187 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:36.187 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:24:36.187 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:24:36.187 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:24:36.187 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:24:36.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:36.189 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:24:36.189 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:24:36.189 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:24:36.189 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:36.189 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:24:36.189 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:24:36.189 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:24:36.189 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:24:36.189 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:36.192 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:24:36.192 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:24:36.192 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:24:36.193 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:36.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:36.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:36.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:36.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:36.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:36.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:36.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:36.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:36.197 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:24:36.680 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:24:36.717 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:24:36.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:24:36.719 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:24:36.720 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:24:36.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:24:36.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:24:36.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:24:36.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:24:36.743 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:24:36.743 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:24:36.743 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:24:36.743 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:24:37.157 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:24:37.195 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:37.196 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:37.196 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:37.199 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:37.635 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:24:38.112 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:24:38.196 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:38.196 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:38.197 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:38.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:38.590 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:24:39.068 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:24:39.197 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:39.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:39.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:39.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:39.545 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:24:40.023 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:24:40.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:40.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:40.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:40.203 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:40.501 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:24:40.978 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:24:41.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:41.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:41.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:41.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:41.456 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:24:41.477 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD NOHANDOVER
2026-03-05 03:24:41.482 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:24:41.483 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:24:41.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:24:41.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:24:41.934 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:24:42.412 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:24:42.890 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:24:43.368 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:24:43.846 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:24:44.326 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:24:44.447 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:24:44.447 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:24:44.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:44.451 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:44.451 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:44.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:44.455 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:24:44.455 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:24:44.455 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:24:44.455 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:24:44.455 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:24:44.455 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:24:44.455 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:24:44.456 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1763 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:44.456 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1763 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:44.456 [WARNING] transceiver.py:257 (TRX1@172.18.201.20:5700/1) RX TRXD message (ver=1 fn=1764 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:44.456 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1763 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:44.456 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1763 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:44.456 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1763 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:44.456 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1763 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:44.456 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1764 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:44.457 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1764 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:24:49.454 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:24:49.454 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:24:49.456 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:24:49.457 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:24:49.458 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:24:49.459 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:24:49.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:24:49.468 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:24:49.468 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:49.469 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:24:49.469 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:24:49.472 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:24:49.472 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:24:49.473 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:24:49.473 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:49.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:24:49.474 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:24:49.474 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:24:49.474 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:24:49.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:49.475 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:24:49.475 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:24:49.475 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:24:49.475 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:49.475 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:24:49.475 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:24:49.475 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:24:49.475 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:24:49.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:49.477 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:24:49.477 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:24:49.477 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:24:49.477 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:24:49.477 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:24:49.478 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:24:49.478 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:24:49.478 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:24:49.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:49.480 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:24:49.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:24:49.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:24:49.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:24:49.480 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:24:49.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:24:49.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:24:49.481 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:24:49.481 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:24:49.481 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:49.481 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:49.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:24:49.486 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:24:49.970 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:24:50.008 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:24:50.009 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:24:50.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:24:50.010 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:24:50.451 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:24:50.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:50.484 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:50.486 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:50.489 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:50.931 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:24:51.412 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:24:51.485 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:51.486 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:51.488 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:51.490 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:51.893 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:24:52.374 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:24:52.487 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:52.488 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:52.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:52.490 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:52.854 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:24:53.335 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:24:53.488 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:53.488 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:53.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:53.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:53.815 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:24:54.296 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:24:54.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:24:54.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:24:54.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:24:54.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:24:54.777 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:24:55.259 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:24:55.737 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:24:56.216 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:24:56.694 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:24:57.172 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:24:57.651 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:24:58.132 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:24:58.629 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:24:59.110 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:24:59.592 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:25:00.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:00.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:00.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:00.023 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:00.024 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:00.024 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:00.024 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:00.024 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:00.024 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:25:00.024 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:25:00.024 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:25:00.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2237 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:00.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2237 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:00.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2237 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:00.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2237 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:00.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2237 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:00.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2237 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:05.026 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:25:05.026 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:25:05.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:05.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:05.029 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:05.029 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:05.037 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:05.037 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:25:05.038 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:05.038 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:25:05.038 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:25:05.041 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:25:05.041 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:25:05.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:25:05.041 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:05.041 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:25:05.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:05.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:25:05.041 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:25:05.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:05.044 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:25:05.044 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:25:05.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:25:05.044 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:05.044 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:05.044 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:25:05.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:25:05.044 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:25:05.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:05.046 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:25:05.046 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:25:05.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:25:05.046 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:05.047 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:05.047 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:25:05.047 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:25:05.047 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:25:05.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:05.050 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:25:05.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:25:05.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:25:05.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:25:05.050 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:05.051 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:25:05.051 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:25:05.051 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:25:05.052 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:25:05.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:05.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:05.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:05.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:25:05.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:05.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:05.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:05.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:05.054 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:25:05.054 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:25:05.054 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:25:10.057 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:25:10.057 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:25:10.059 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:10.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:10.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:10.062 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:10.069 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:10.071 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:25:10.071 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:10.071 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:25:10.071 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:25:10.074 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:25:10.075 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:25:10.075 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:25:10.075 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:10.076 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:10.076 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:25:10.076 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:25:10.077 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:25:10.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:10.077 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:25:10.077 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:25:10.077 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:25:10.077 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:10.078 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:10.078 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:25:10.078 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:25:10.078 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:25:10.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:10.080 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:25:10.080 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:25:10.080 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:25:10.080 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:10.080 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:10.080 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:25:10.080 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:25:10.080 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:25:10.080 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:10.083 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:25:10.083 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:25:10.084 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:25:10.084 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:10.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:10.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:10.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:10.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:10.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:10.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:10.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:10.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:10.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:10.088 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:25:10.572 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:25:10.605 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:25:10.605 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:25:10.606 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:25:10.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:25:10.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:25:10.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:25:10.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:25:10.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:25:10.608 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:25:10.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:25:10.609 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:25:10.609 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:25:11.049 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:25:11.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:11.087 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:11.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:11.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:11.527 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:25:12.004 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:25:12.087 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:12.087 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:12.088 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:12.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:12.482 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:25:12.959 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:25:13.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:13.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:13.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:13.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:13.437 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:25:13.915 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:25:14.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:14.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:14.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:14.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:14.393 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:25:14.870 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:25:15.091 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:15.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:15.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:15.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:15.348 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:25:15.825 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:25:16.304 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:25:16.781 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:25:17.259 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:25:17.737 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:25:18.215 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:25:18.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:25:18.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:25:18.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:18.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:18.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:18.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:18.628 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:18.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:18.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:18.629 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:25:18.629 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:25:18.629 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:25:18.629 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:18.629 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:18.630 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:18.630 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:18.630 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:18.630 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:18.630 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:18.630 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:18.630 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1825 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:23.631 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:25:23.631 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:25:23.631 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:23.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:23.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:23.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:23.638 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:23.639 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:25:23.639 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:23.640 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:25:23.640 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:25:23.643 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:25:23.643 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:25:23.644 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:25:23.644 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:23.645 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:23.645 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:25:23.646 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:25:23.646 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:25:23.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:23.647 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:25:23.648 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:25:23.648 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:25:23.648 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:23.648 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:23.648 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:25:23.648 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:25:23.648 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:25:23.649 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:23.652 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:25:23.652 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:25:23.652 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:25:23.652 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:23.652 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:23.652 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:25:23.652 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:25:23.652 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:25:23.652 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:23.656 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:25:23.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:25:23.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:25:23.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:25:23.656 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:25:23.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:25:23.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:25:23.657 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:25:23.657 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:25:23.657 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:23.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:23.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:25:23.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:23.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:23.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:23.660 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:23.660 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:23.660 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:25:23.660 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:25:23.660 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:25:28.665 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:25:28.666 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:25:28.666 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:28.666 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:28.666 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:28.666 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:28.673 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:28.673 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:25:28.673 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:28.674 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:25:28.674 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:25:28.675 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:25:28.676 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:25:28.676 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:25:28.676 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:28.677 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:28.677 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:25:28.677 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:25:28.677 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:25:28.678 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:28.679 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:25:28.679 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:25:28.679 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:25:28.679 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:28.679 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:28.679 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:25:28.680 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:25:28.680 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:25:28.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:28.681 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:25:28.681 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:25:28.681 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:25:28.682 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:28.682 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:28.682 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:25:28.682 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:25:28.682 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:25:28.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:28.685 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:25:28.686 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:25:28.686 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:25:28.686 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:25:28.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:28.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:28.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:28.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:25:28.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:28.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:28.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:28.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:28.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:28.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:28.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:28.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:28.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:28.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:28.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:28.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:28.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:28.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:28.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:28.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:28.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:28.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:28.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:28.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:28.690 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:25:29.175 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:25:29.226 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:25:29.228 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:25:29.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:25:29.229 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:25:29.231 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:25:29.231 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:25:29.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:25:29.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:25:29.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:25:29.232 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:25:29.232 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:25:29.232 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:25:29.652 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:25:29.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:29.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:29.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:29.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:30.130 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:25:30.608 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:25:30.691 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:30.691 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:30.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:30.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:31.085 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:25:31.563 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:25:31.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:31.692 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:31.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:31.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:32.041 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:25:32.519 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:25:32.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:32.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:32.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:32.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:32.996 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:25:33.474 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:25:33.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:33.713 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:33.713 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:33.713 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:33.952 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:25:34.430 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:25:34.907 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:25:35.385 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:25:35.862 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:25:36.340 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:25:36.818 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:25:37.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:25:37.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:25:37.274 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:37.274 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:37.274 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:37.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:37.278 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:37.278 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:37.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:37.278 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:37.278 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:25:37.278 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:25:37.278 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:25:37.279 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:37.279 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:37.279 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:37.279 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:37.279 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:37.279 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:25:42.278 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:25:42.278 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:25:42.279 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:42.281 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:42.281 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:42.281 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:42.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:42.287 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:25:42.287 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:42.287 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:25:42.288 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:25:42.290 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:25:42.291 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:25:42.291 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:25:42.291 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:42.292 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:42.292 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:25:42.292 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:25:42.292 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:25:42.292 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:42.294 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:25:42.294 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:25:42.294 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:25:42.294 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:42.294 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:42.294 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:25:42.295 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:25:42.295 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:25:42.295 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:42.296 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:25:42.296 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:25:42.296 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:25:42.296 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:42.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:42.297 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:25:42.297 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:25:42.297 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:25:42.297 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:42.299 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:25:42.299 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:25:42.300 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:25:42.300 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:25:42.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:42.300 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:42.300 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:42.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:25:42.300 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:42.301 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:25:42.301 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:25:42.301 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:25:47.304 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:25:47.304 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:25:47.306 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:47.306 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:47.307 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:47.307 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:47.314 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:47.314 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:25:47.314 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:47.315 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:25:47.315 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:25:47.316 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:25:47.317 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:25:47.317 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:25:47.317 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:47.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:47.318 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:25:47.318 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:25:47.318 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:25:47.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:47.319 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:25:47.319 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:25:47.319 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:25:47.319 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:47.319 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:47.319 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:25:47.319 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:25:47.319 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:25:47.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:47.321 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:25:47.321 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:25:47.321 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:25:47.321 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:25:47.321 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:47.321 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:25:47.321 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:25:47.321 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:25:47.321 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:25:47.324 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:25:47.324 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:25:47.324 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:47.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:47.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:25:47.329 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:25:47.812 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:25:47.852 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:25:47.855 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:25:47.857 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:25:47.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:25:47.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:25:47.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:25:47.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:25:47.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:25:47.860 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:25:47.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:25:47.860 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:25:47.860 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:25:48.290 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:25:48.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:48.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:48.328 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:48.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:48.768 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:25:49.245 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:25:49.328 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:49.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:49.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:49.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:49.723 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:25:50.201 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:25:50.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:50.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:50.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:50.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:50.679 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:25:51.157 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:25:51.330 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:51.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:51.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:51.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:51.634 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:25:52.111 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:25:52.331 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:52.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:52.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:52.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:52.589 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:25:53.066 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:25:53.543 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:25:54.021 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:25:54.499 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:25:54.977 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:25:55.453 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:25:55.907 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:25:55.907 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:25:55.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:25:55.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:25:55.912 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:25:55.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:25:55.914 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:25:55.914 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:25:55.914 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:25:55.914 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:25:55.914 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:25:55.914 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:25:55.914 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:26:00.915 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:26:00.915 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:26:00.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:00.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:00.918 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:00.919 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:00.927 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:00.927 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:26:00.927 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:00.928 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:26:00.928 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:26:00.929 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:26:00.929 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:26:00.930 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:26:00.930 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:00.930 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:00.930 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:26:00.930 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:26:00.930 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:26:00.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:00.932 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:26:00.932 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:26:00.932 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:26:00.932 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:00.932 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:00.932 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:26:00.932 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:26:00.932 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:26:00.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:00.933 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:26:00.934 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:26:00.934 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:26:00.934 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:00.934 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:00.934 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:26:00.934 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:26:00.934 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:26:00.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:00.936 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:26:00.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:26:00.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:26:00.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:26:00.936 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:26:00.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:26:00.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:26:00.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:26:00.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:26:00.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:00.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:00.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:00.937 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:26:00.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:00.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:00.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:00.937 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:00.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:00.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:00.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:00.937 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:26:00.937 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:26:00.937 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:26:00.937 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:26:00.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:00.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:00.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:00.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:00.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:00.939 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:26:00.939 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:26:00.939 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:26:05.942 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:26:05.942 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:26:05.943 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:05.945 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:05.946 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:05.946 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:05.958 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:05.960 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:26:05.960 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:05.960 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:26:05.961 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:26:05.964 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:26:05.964 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:26:05.964 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:26:05.965 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:05.965 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:05.965 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:26:05.966 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:26:05.966 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:26:05.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:05.966 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:26:05.966 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:26:05.967 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:26:05.967 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:05.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:05.967 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:26:05.967 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:26:05.967 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:26:05.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:05.968 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:26:05.969 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:26:05.969 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:26:05.969 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:05.969 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:05.969 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:26:05.969 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:26:05.969 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:26:05.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:05.971 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:26:05.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:26:05.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:26:05.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:26:05.971 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:26:05.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:26:05.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:26:05.972 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:26:05.972 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:26:05.972 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:05.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:05.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:05.977 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:26:06.458 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:26:06.500 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:26:06.502 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:26:06.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:26:06.505 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:26:06.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:26:06.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:26:06.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:26:06.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:26:06.511 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:26:06.511 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:26:06.511 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:26:06.511 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:26:06.935 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:26:06.975 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:06.975 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:06.975 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:06.978 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:07.413 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:26:07.890 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:26:07.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:07.976 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:07.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:07.979 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:08.368 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:26:08.847 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:26:08.977 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:08.977 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:08.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:08.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:09.325 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:26:09.803 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:26:09.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:09.978 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:09.979 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:09.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:10.280 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:26:10.758 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:26:10.979 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:10.979 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:10.979 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:10.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:11.236 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:26:11.714 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:26:12.192 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:26:12.670 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:26:13.147 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:26:13.625 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:26:14.103 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:26:14.552 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:26:14.552 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:26:14.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:14.554 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:14.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:14.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:14.554 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:14.554 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:14.554 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:26:14.554 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:26:14.554 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:26:14.554 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:14.554 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:19.557 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:26:19.557 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:26:19.559 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:19.560 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:19.561 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:19.562 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:19.564 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:19.565 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:26:19.565 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:19.565 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:26:19.565 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:26:19.565 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:26:19.565 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:26:19.566 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:26:19.566 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:19.566 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:19.566 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:26:19.566 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:26:19.567 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:26:19.567 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:19.567 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:26:19.567 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:26:19.567 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:26:19.567 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:19.567 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:19.567 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:26:19.568 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:26:19.568 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:26:19.568 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:19.569 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:26:19.569 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:26:19.569 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:26:19.569 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:19.569 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:19.569 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:26:19.569 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:26:19.569 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:26:19.569 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:19.571 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:26:19.571 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:26:19.571 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:26:19.571 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:26:19.572 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:26:19.572 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:26:19.572 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:19.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:19.573 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:19.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:19.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:19.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:19.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:19.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:19.574 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:19.574 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:19.574 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:26:19.574 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:26:19.574 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:26:24.577 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:26:24.577 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:26:24.579 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:24.580 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:24.581 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:24.581 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:24.587 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:24.589 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:26:24.589 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:24.589 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:26:24.590 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:26:24.593 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:26:24.593 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:26:24.594 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:26:24.594 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:24.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:24.595 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:26:24.595 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:26:24.595 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:26:24.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:24.596 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:26:24.597 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:26:24.597 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:26:24.597 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:24.597 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:24.597 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:26:24.597 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:26:24.597 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:26:24.597 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:24.599 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:26:24.599 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:26:24.599 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:26:24.599 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:24.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:24.600 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:26:24.600 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:26:24.600 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:26:24.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:24.602 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:24.603 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:26:24.603 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:26:24.603 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:26:24.603 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:24.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:24.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:24.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:24.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:24.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:24.608 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:26:25.091 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:26:25.132 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:26:25.134 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:26:25.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:26:25.135 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:26:25.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:26:25.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:26:25.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:26:25.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:26:25.139 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:26:25.139 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:26:25.139 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:26:25.140 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:26:25.568 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:26:25.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:25.607 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:25.608 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:25.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:26.046 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:26:26.524 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:26:26.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:26.623 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:26.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:26.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:27.002 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:26:27.480 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:26:27.624 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:27.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:27.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:27.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:27.958 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:26:28.435 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:26:28.624 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:28.625 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:28.625 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:28.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:28.913 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:26:29.390 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:26:29.625 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:29.626 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:29.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:29.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:29.868 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:26:30.346 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:26:30.823 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:26:31.300 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:26:31.778 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:26:32.256 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:26:32.734 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:26:33.212 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:26:33.689 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:26:34.167 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:26:34.645 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:26:35.123 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:26:35.601 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:26:36.078 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:26:36.557 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:26:37.034 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:26:37.512 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:26:37.990 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:26:38.467 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:26:38.945 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:26:39.185 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:26:39.185 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:26:39.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:39.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:39.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:39.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:39.188 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:39.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:39.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:39.188 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:26:39.188 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:26:39.188 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:26:39.188 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:44.195 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:26:44.195 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:26:44.196 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:44.196 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:44.196 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:44.196 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:44.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:44.204 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:26:44.204 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:44.204 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:26:44.204 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:26:44.205 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:26:44.205 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:26:44.205 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:26:44.205 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:44.205 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:44.205 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:26:44.205 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:26:44.205 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:26:44.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:44.207 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:26:44.207 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:26:44.207 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:26:44.207 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:44.207 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:44.207 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:26:44.207 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:26:44.207 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:26:44.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:44.208 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:26:44.208 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:26:44.208 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:26:44.208 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:44.209 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:44.209 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:26:44.209 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:26:44.209 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:26:44.209 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:26:44.211 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:26:44.211 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:26:44.211 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:44.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:44.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:44.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:44.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:44.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:44.213 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:44.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:44.213 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:44.213 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:26:44.213 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:26:44.213 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:26:49.216 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:26:49.216 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:26:49.217 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:49.220 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:49.220 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:49.220 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:49.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:49.227 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:26:49.228 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:49.228 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:26:49.228 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:26:49.229 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:26:49.229 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:26:49.229 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:26:49.229 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:49.229 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:49.229 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:26:49.230 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:26:49.230 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:26:49.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:49.231 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:26:49.232 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:26:49.232 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:26:49.232 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:49.232 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:49.232 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:26:49.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:26:49.233 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:26:49.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:49.234 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:26:49.234 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:26:49.234 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:26:49.234 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:26:49.234 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:49.234 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:26:49.234 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:26:49.234 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:26:49.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:49.236 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:26:49.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:26:49.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:26:49.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:26:49.236 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:26:49.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:26:49.237 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:26:49.237 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:26:49.237 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:49.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:49.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:26:49.242 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:26:49.724 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:26:49.766 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:26:49.768 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:26:49.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:26:49.771 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:26:49.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:26:49.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:26:49.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:26:49.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:26:49.775 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:26:49.775 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:26:49.776 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:26:49.776 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:26:50.202 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:26:50.239 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:50.240 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:50.240 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:50.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:50.679 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:26:51.157 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:26:51.240 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:51.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:51.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:51.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:51.634 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:26:52.112 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:26:52.241 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:52.242 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:52.242 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:52.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:52.589 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:26:53.067 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:26:53.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:53.243 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:53.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:53.246 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:53.544 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:26:54.022 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:26:54.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:54.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:54.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:54.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:54.499 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:26:54.977 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:26:55.455 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:26:55.933 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:26:56.410 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:26:56.888 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:26:57.365 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:26:57.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:26:57.819 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:26:57.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:26:57.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:26:57.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:26:57.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:26:57.821 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:26:57.821 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:26:57.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:26:57.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:26:57.822 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:26:57.822 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:26:57.822 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:27:02.825 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:27:02.825 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:27:02.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:02.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:02.829 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:02.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:02.837 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:02.838 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:27:02.838 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:02.839 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:27:02.839 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:27:02.843 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:27:02.843 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:27:02.844 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:27:02.844 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:02.844 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:02.845 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:27:02.845 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:27:02.845 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:27:02.846 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:02.846 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:27:02.847 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:27:02.847 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:27:02.847 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:02.847 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:02.847 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:27:02.847 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:27:02.847 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:27:02.847 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:02.849 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:27:02.849 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:27:02.849 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:27:02.849 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:02.849 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:02.849 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:27:02.849 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:27:02.849 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:27:02.849 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:02.852 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:27:02.853 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:27:02.853 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:27:02.853 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:27:02.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:02.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:02.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:02.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:27:02.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:02.854 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:27:02.855 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:27:02.855 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:27:02.855 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:07.858 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:27:07.858 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:27:07.860 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:07.861 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:07.862 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:07.862 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:07.870 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:07.871 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:27:07.871 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:07.871 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:27:07.872 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:27:07.875 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:27:07.875 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:27:07.876 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:27:07.876 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:07.876 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:07.877 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:27:07.877 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:27:07.877 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:27:07.878 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:07.878 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:27:07.878 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:27:07.878 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:27:07.878 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:07.878 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:07.879 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:27:07.879 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:27:07.879 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:27:07.879 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:07.880 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:27:07.881 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:27:07.881 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:27:07.881 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:07.881 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:07.881 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:27:07.881 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:27:07.881 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:27:07.881 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:07.883 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:27:07.884 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:27:07.884 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:27:07.884 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:27:07.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:07.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:07.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:07.889 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:27:08.371 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:27:08.406 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:27:08.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:27:08.408 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:27:08.409 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:27:08.410 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:27:08.410 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:27:08.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:27:08.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:27:08.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:27:08.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:27:08.411 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:27:08.411 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:27:08.848 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:27:08.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:08.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:08.889 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:08.891 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:09.326 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:27:09.804 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:27:09.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:09.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:09.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:09.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:10.281 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:27:10.759 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:27:10.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:10.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:10.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:10.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:11.237 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:27:11.714 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:27:11.889 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:11.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:11.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:11.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:12.192 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:27:12.669 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:27:12.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:12.890 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:12.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:12.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:13.146 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:27:13.624 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:27:14.101 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:27:14.580 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:27:15.057 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:27:15.535 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:27:16.012 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:27:16.490 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:27:16.967 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:27:17.445 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:27:17.923 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:27:18.401 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:27:18.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:27:18.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:27:18.425 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:18.426 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:18.426 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:18.426 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:18.427 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:18.427 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:18.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:18.427 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:18.427 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:27:18.427 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:27:18.427 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:27:18.427 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2251 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:27:18.427 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2251 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:27:18.428 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2251 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:27:18.428 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2251 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:27:18.428 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2251 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:27:18.428 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2251 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:27:23.427 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:27:23.427 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:27:23.427 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:23.428 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:23.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:23.429 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:23.433 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:23.434 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:27:23.434 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:23.434 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:27:23.434 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:27:23.435 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:27:23.435 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:27:23.435 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:27:23.435 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:23.436 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:23.436 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:27:23.436 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:27:23.436 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:27:23.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:23.437 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:27:23.437 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:27:23.437 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:27:23.437 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:23.437 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:23.437 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:27:23.437 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:27:23.437 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:27:23.437 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:23.439 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:27:23.439 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:27:23.439 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:27:23.439 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:23.439 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:23.439 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:27:23.439 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:27:23.439 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:27:23.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:23.442 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:27:23.442 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:27:23.442 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:27:23.443 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:27:23.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:23.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:23.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:23.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:27:23.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:23.444 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:27:23.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:27:23.444 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:27:28.447 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:27:28.447 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:27:28.449 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:28.451 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:28.451 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:28.451 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:28.459 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:28.459 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:27:28.459 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:28.460 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:27:28.460 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:27:28.462 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:27:28.462 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:27:28.463 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:27:28.463 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:28.463 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:28.463 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:27:28.464 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:27:28.464 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:27:28.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:28.464 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:27:28.465 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:27:28.465 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:27:28.465 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:28.465 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:28.465 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:27:28.465 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:27:28.465 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:27:28.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:28.467 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:27:28.467 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:27:28.467 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:27:28.467 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:28.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:28.467 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:27:28.467 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:27:28.467 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:27:28.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:27:28.470 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:27:28.470 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:27:28.470 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:27:28.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:28.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:28.475 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:27:28.957 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:27:28.998 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:27:29.001 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:27:29.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:27:29.004 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:27:29.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:27:29.007 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:27:29.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:27:29.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:27:29.009 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:27:29.009 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:27:29.009 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:27:29.010 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:27:29.434 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:27:29.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:29.473 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:29.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:29.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:29.912 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:27:30.390 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:27:30.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:30.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:30.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:30.477 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:30.867 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:27:31.345 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:27:31.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:31.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:31.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:31.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:31.823 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:27:32.301 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:27:32.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:32.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:32.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:32.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:32.779 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:27:33.257 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:27:33.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:33.477 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:33.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:33.480 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:33.736 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:27:34.214 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:27:34.692 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:27:35.170 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:27:35.647 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:27:36.125 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:27:36.603 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:27:37.080 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:27:37.558 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:27:38.035 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:27:38.513 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:27:38.990 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:27:39.467 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:27:39.945 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:27:40.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:27:40.053 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:27:40.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:40.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:40.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:40.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:40.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:40.059 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:40.059 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:40.059 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:40.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:27:40.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:27:40.060 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:27:40.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:27:40.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:27:40.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:27:40.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:27:40.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:27:40.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:27:40.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2474 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:27:45.061 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:27:45.061 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:27:45.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:45.064 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:45.065 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:45.065 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:45.072 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:45.072 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:27:45.072 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:45.072 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:27:45.072 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:27:45.073 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:27:45.073 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:27:45.073 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:27:45.073 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:45.073 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:45.074 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:27:45.074 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:27:45.074 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:27:45.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:45.075 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:27:45.075 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:27:45.075 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:27:45.075 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:45.075 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:45.075 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:27:45.076 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:27:45.076 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:27:45.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:45.077 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:27:45.077 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:27:45.077 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:27:45.077 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:45.077 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:45.077 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:27:45.077 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:27:45.077 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:27:45.078 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:45.080 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:27:45.080 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:27:45.080 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:27:45.081 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:27:45.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:45.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:45.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:45.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:27:45.082 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:27:45.082 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:27:45.082 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:50.085 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:27:50.085 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:27:50.093 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:50.094 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:50.094 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:50.094 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:50.095 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:27:50.095 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:27:50.095 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:50.095 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:27:50.096 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:27:50.097 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:27:50.097 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:27:50.098 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:27:50.098 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:50.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:27:50.098 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:27:50.098 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:27:50.098 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:27:50.099 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:50.099 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:27:50.099 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:27:50.100 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:27:50.100 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:50.100 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:27:50.100 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:27:50.100 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:27:50.100 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:27:50.100 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:50.101 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:27:50.101 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:27:50.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:27:50.102 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:27:50.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:27:50.102 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:27:50.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:27:50.102 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:27:50.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:50.104 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:27:50.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:27:50.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:27:50.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:27:50.104 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:27:50.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:27:50.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:27:50.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:27:50.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:27:50.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:50.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:27:50.105 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:27:50.105 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:27:50.105 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:50.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:50.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:27:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:27:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:50.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:50.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:27:50.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:50.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:50.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:50.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:27:50.110 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:27:50.589 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:27:50.634 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:27:50.637 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:27:50.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:27:50.639 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:27:50.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:27:50.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:27:50.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:27:50.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:27:50.643 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:27:50.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:27:50.644 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:27:50.644 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:27:51.067 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:27:51.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:51.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:51.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:51.110 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:51.545 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:27:52.022 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:27:52.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:52.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:52.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:52.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:52.500 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:27:52.977 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:27:53.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:53.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:53.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:53.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:53.455 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:27:53.932 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:27:54.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:54.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:54.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:54.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:54.409 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:27:54.887 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:27:55.111 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:27:55.111 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:27:55.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:27:55.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:27:55.364 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:27:55.842 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:27:56.320 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:27:56.797 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:27:57.275 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:27:57.753 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:27:58.231 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:27:58.708 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:27:59.186 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:27:59.664 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:28:00.141 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:28:00.619 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:28:01.097 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:28:01.574 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:28:02.052 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:28:02.529 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:28:03.006 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:28:03.484 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:28:03.961 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:28:04.439 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:28:04.916 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:28:05.394 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:28:05.871 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:28:06.349 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:28:06.827 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:28:07.304 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:28:07.781 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:28:08.259 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:28:08.736 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:28:09.213 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:28:09.692 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:28:10.169 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:28:10.648 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:28:10.691 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:28:10.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:28:10.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:10.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:10.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:10.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:10.699 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:10.699 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:10.700 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:10.700 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:10.700 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:28:10.700 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:28:10.700 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:28:10.700 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4398 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:10.701 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4398 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:10.701 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4398 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:10.701 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4398 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:10.701 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4398 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:10.701 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4398 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:10.701 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4399 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:10.701 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4399 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:10.701 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4399 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:10.701 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4399 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:10.701 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4399 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:10.701 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4399 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:10.702 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4399 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:10.702 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4399 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:15.703 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:28:15.703 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:28:15.703 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:15.703 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:15.703 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:15.703 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:15.712 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:15.714 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:28:15.714 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:15.715 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:28:15.715 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:28:15.719 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:28:15.719 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:28:15.720 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:28:15.720 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:15.720 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:15.721 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:28:15.721 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:28:15.721 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:28:15.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:15.722 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:28:15.722 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:28:15.723 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:28:15.723 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:15.723 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:15.724 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:28:15.724 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:28:15.724 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:28:15.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:15.725 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:28:15.725 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:28:15.725 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:28:15.725 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:15.725 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:15.725 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:28:15.726 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:28:15.726 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:28:15.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:15.729 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:28:15.730 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:28:15.730 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:28:15.730 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:28:15.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:15.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:15.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:15.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:28:15.730 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:15.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:15.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:15.730 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:15.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:15.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:15.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:15.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:15.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:15.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:15.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:15.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:15.731 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:15.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:15.731 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:15.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:15.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:15.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:15.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:15.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:15.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:15.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:15.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:15.732 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:15.732 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:15.732 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:15.732 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:28:15.732 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:28:15.732 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:28:20.739 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:28:20.739 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:28:20.739 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:20.739 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:20.739 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:20.739 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:20.747 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:20.749 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:28:20.749 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:20.750 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:28:20.750 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:28:20.754 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:28:20.754 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:28:20.755 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:28:20.755 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:20.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:20.756 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:28:20.757 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:28:20.757 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:28:20.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:20.758 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:28:20.758 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:28:20.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:28:20.758 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:20.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:20.759 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:28:20.759 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:28:20.759 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:28:20.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:20.761 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:28:20.761 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:28:20.761 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:28:20.761 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:20.761 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:20.761 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:28:20.761 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:28:20.761 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:28:20.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:20.765 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:28:20.765 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:28:20.765 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:28:20.766 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:28:20.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:20.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:20.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:20.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:28:20.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:20.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:20.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:20.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:20.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:20.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:20.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:20.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:20.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:20.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:20.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:20.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:20.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:20.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:20.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:20.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:20.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:20.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:20.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:20.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:20.770 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:28:21.254 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:28:21.304 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:28:21.305 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:28:21.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:28:21.307 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:28:21.735 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:28:21.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:21.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:21.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:21.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:22.216 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:28:22.696 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:28:22.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:22.772 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:22.775 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:22.778 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:23.168 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:28:23.637 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:28:23.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:23.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:23.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:23.778 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:24.106 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:28:24.576 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:28:24.775 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:24.775 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:24.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:24.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:25.054 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:28:25.533 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:28:25.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:25.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:25.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:25.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:26.010 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:28:26.486 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:28:26.967 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:28:27.448 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:28:27.926 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:28:28.405 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:28:28.886 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:28:29.366 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:28:29.838 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:28:30.315 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:28:30.795 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:28:31.287 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:28:31.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:31.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:31.318 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:31.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:31.320 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:31.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:31.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:31.320 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:28:31.320 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:28:31.320 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:28:31.320 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:31.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2252 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2252 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2252 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2252 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2252 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2252 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2252 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2252 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2253 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2253 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2253 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.320 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2253 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.321 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2253 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.321 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2253 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.321 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2253 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:31.321 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2253 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:36.321 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:28:36.321 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:28:36.322 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:36.324 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:36.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:36.325 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:36.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:36.331 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:28:36.331 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:36.331 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:28:36.331 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:28:36.333 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:28:36.333 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:28:36.334 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:28:36.334 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:36.334 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:36.334 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:28:36.334 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:28:36.334 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:28:36.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:36.336 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:28:36.336 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:28:36.336 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:28:36.336 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:36.337 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:36.337 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:28:36.337 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:28:36.337 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:28:36.337 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:36.339 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:28:36.339 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:28:36.339 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:28:36.339 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:36.339 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:36.339 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:28:36.339 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:28:36.339 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:28:36.339 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:36.342 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:28:36.343 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:28:36.343 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:28:36.343 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:28:36.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:36.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:36.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:36.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:36.344 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:28:36.344 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:28:36.344 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:28:41.348 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:28:41.348 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:28:41.349 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:41.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:41.352 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:41.352 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:41.359 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:41.360 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:28:41.360 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:41.360 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:28:41.360 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:28:41.360 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:28:41.360 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:28:41.360 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:28:41.360 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:41.360 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:41.361 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:28:41.361 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:28:41.361 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:28:41.361 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:41.361 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:28:41.361 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:28:41.361 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:28:41.361 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:41.361 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:41.361 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:28:41.361 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:28:41.361 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:28:41.361 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:41.362 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:28:41.362 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:28:41.362 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:28:41.362 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:41.362 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:41.362 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:28:41.362 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:28:41.362 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:28:41.362 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:41.363 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:28:41.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:28:41.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:28:41.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:28:41.363 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:28:41.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:28:41.364 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:28:41.364 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:28:41.364 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:41.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:41.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:41.369 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:28:41.851 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:28:41.883 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:28:41.883 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:28:41.884 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:28:41.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:28:42.330 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:28:42.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:42.367 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:42.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:42.369 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:42.810 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:28:43.279 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:28:43.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:43.368 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:43.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:43.370 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:43.747 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:28:44.226 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:28:44.369 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:44.369 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:44.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:44.371 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:44.698 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:28:45.167 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:28:45.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:45.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:45.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:45.373 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:45.636 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:28:46.110 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:28:46.372 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:46.372 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:46.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:46.373 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:46.590 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:28:47.070 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:28:47.550 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:28:48.029 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:28:48.509 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:28:48.981 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:28:49.457 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:28:49.936 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:28:50.408 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:28:50.877 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:28:51.346 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:28:51.817 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:28:52.298 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:28:52.779 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:28:53.253 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:28:53.721 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:28:53.897 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:53.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:53.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:53.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:53.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:53.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:53.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:53.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:53.900 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:28:53.900 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:28:53.900 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:28:53.900 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2692 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:53.900 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2692 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:53.900 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2692 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:53.900 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2692 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:53.900 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2692 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:53.900 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2692 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:53.900 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2692 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:28:58.901 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:28:58.901 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:28:58.904 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:58.904 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:58.904 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:58.904 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:58.911 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:58.912 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:28:58.912 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:58.913 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:28:58.913 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:28:58.917 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:28:58.917 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:28:58.917 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:28:58.917 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:58.918 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:58.918 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:28:58.918 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:28:58.918 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:28:58.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:28:58.921 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:28:58.921 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:28:58.922 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:28:58.922 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:58.922 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:58.922 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:28:58.922 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:28:58.922 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:28:58.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:28:58.925 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:28:58.925 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:28:58.925 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:28:58.925 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:28:58.926 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:58.926 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:28:58.926 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:28:58.926 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:28:58.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:28:58.930 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:28:58.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:28:58.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:28:58.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:28:58.930 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:58.931 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:28:58.931 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:28:58.931 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:28:58.932 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:28:58.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:58.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:58.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:58.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:28:58.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:58.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:58.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:58.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:58.932 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:58.932 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:58.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:58.932 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:28:58.934 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:28:58.934 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:28:58.934 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:29:03.937 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:29:03.937 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:29:03.939 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:03.940 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:03.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:03.941 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:03.949 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:03.950 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:03.950 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:03.951 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:03.951 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:29:03.954 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:29:03.954 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:29:03.954 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:03.954 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:03.955 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:03.955 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:29:03.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:03.955 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:29:03.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:03.957 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:29:03.957 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:29:03.957 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:03.957 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:03.957 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:03.957 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:29:03.957 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:03.957 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:29:03.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:03.959 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:29:03.959 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:29:03.959 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:03.959 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:03.959 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:03.959 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:29:03.959 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:03.959 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:29:03.959 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:29:03.962 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:29:03.962 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:29:03.962 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:03.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:03.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:03.967 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:29:04.451 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:29:04.490 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:29:04.492 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:29:04.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:29:04.494 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:29:04.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:29:04.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:29:04.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:29:04.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:29:04.497 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:29:04.497 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:29:04.497 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:29:04.498 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:29:04.541 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:29:04.542 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 03:29:04.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:29:04.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:29:04.929 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:29:04.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:04.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:04.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:04.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:05.407 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:29:05.886 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:29:05.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:05.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:05.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:05.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:06.364 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:29:06.842 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:29:06.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:06.967 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:06.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:06.970 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:07.320 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:29:07.798 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:29:07.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:07.968 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:07.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:07.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:08.276 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:29:08.766 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:29:08.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:08.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:08.969 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:08.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:09.244 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:29:09.723 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:29:10.201 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:29:10.678 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:29:11.157 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:29:11.634 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:29:12.112 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:29:12.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:29:12.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:29:12.546 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:29:12.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:12.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:12.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:12.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:12.549 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:12.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:12.549 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:12.549 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:29:12.549 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:29:12.549 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:29:12.549 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:17.552 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:29:17.552 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:29:17.554 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:17.555 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:17.556 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:17.556 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:17.564 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:17.566 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:17.566 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:17.567 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:17.567 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:29:17.571 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:29:17.572 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:29:17.572 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:17.572 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:17.572 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:17.572 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:29:17.572 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:17.573 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:29:17.573 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:17.575 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:29:17.575 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:29:17.575 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:17.575 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:17.575 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:17.575 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:29:17.575 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:17.576 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:29:17.576 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:17.578 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:29:17.578 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:29:17.578 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:17.578 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:17.578 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:17.578 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:29:17.578 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:17.578 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:29:17.578 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:17.581 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:29:17.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:29:17.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:29:17.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:29:17.581 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:29:17.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:29:17.582 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:29:17.582 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:29:17.582 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:17.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:17.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:17.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:29:17.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:17.584 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:29:17.584 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:29:17.584 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:29:22.587 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:29:22.587 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:29:22.589 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:22.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:22.590 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:22.590 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:22.598 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:22.600 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:22.600 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:22.600 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:22.600 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:29:22.604 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:29:22.604 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:29:22.605 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:22.605 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:22.605 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:22.605 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:29:22.606 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:22.606 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:29:22.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:22.607 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:29:22.607 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:29:22.607 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:22.607 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:22.608 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:22.608 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:29:22.608 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:22.608 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:29:22.608 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:22.609 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:29:22.609 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:29:22.609 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:22.609 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:22.609 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:22.609 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:29:22.609 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:22.609 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:29:22.610 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:22.612 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:29:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:29:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:29:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:29:22.612 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:29:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:29:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:29:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:29:22.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:29:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:22.612 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:29:22.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:29:22.613 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:29:22.613 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:29:22.613 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:22.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:22.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:22.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:22.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:22.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:22.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:22.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:22.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:22.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:22.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:22.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:22.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:22.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:22.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:22.618 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:29:23.101 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:29:23.142 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:29:23.143 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:29:23.144 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:29:23.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:29:23.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:29:23.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:29:23.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:29:23.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:29:23.146 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:29:23.146 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:29:23.146 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:29:23.146 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:29:23.191 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:29:23.192 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 03:29:23.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:29:23.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:29:23.578 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:29:23.617 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:23.617 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:23.617 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:23.621 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:24.056 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:29:24.534 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:29:24.618 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:24.618 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:24.618 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:24.622 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:25.006 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:29:25.483 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:29:25.618 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:25.619 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:25.619 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:25.622 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:25.961 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:29:26.439 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:29:26.619 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:26.619 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:26.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:26.623 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:26.917 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:29:27.396 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:29:27.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:27.620 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:27.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:27.623 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:27.874 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:29:28.351 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:29:28.830 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:29:29.308 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:29:29.786 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:29:30.264 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:29:30.742 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:29:31.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:29:31.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:29:31.196 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:29:31.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:31.200 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:31.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:31.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:31.202 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:31.202 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:31.202 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:31.202 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:31.202 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:29:31.202 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:29:31.202 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:29:31.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:29:31.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:29:31.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:29:31.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:29:31.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:29:31.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:29:31.202 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1835 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:29:36.203 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:29:36.203 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:29:36.205 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:36.206 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:36.208 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:36.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:36.226 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:36.227 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:36.227 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:36.227 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:36.227 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:29:36.230 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:29:36.230 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:29:36.231 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:36.231 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:36.231 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:36.231 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:29:36.232 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:36.232 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:29:36.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:36.232 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:29:36.233 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:29:36.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:36.233 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:36.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:36.233 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:29:36.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:36.233 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:29:36.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:36.235 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:29:36.235 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:29:36.235 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:36.235 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:36.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:36.235 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:29:36.235 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:36.235 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:29:36.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:29:36.238 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:29:36.238 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:29:36.238 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:36.238 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:36.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:29:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:36.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:36.239 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:36.240 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:29:36.240 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:29:36.240 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:29:41.243 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:29:41.243 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:29:41.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:41.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:41.247 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:41.247 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:41.255 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:41.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:41.255 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:41.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:41.255 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:29:41.257 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:29:41.258 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:29:41.258 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:41.258 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:41.258 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:41.258 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:29:41.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:41.259 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:29:41.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:41.260 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:29:41.260 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:29:41.261 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:41.261 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:41.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:41.261 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:29:41.261 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:41.261 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:29:41.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:41.263 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:29:41.263 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:29:41.263 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:41.263 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:41.263 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:41.263 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:29:41.263 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:41.263 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:29:41.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:41.265 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:29:41.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:29:41.266 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:29:41.266 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:29:41.266 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:41.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:41.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:41.271 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:29:41.754 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:29:41.799 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:29:41.801 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:29:41.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:29:41.803 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:29:41.805 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:29:41.805 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:29:41.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:29:41.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:29:41.806 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:29:41.806 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:29:41.807 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:29:41.807 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:29:41.844 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:29:41.844 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 03:29:41.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:29:41.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:29:42.232 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:29:42.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:42.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:42.270 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:42.274 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:42.710 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:29:43.183 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:29:43.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:43.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:43.271 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:43.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:43.650 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:29:44.120 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:29:44.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:44.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:44.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:44.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:44.595 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:29:45.073 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:29:45.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:45.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:45.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:45.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:45.551 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:29:46.029 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:29:46.273 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:46.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:46.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:46.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:46.506 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:29:46.984 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:29:47.462 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:29:47.940 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:29:48.418 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:29:48.896 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:29:49.374 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:29:49.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:29:49.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:29:49.849 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:29:49.851 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:49.851 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:49.851 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:49.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:49.852 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:49.852 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:49.852 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:49.852 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:49.852 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:29:49.852 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:29:49.852 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:29:54.854 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:29:54.854 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:29:54.857 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:54.857 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:54.857 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:54.857 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:54.865 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:54.865 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:54.865 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:54.865 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:54.865 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:29:54.868 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:29:54.868 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:29:54.868 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:54.869 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:54.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:54.869 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:29:54.869 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:54.869 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:29:54.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:54.875 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:29:54.875 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:29:54.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:54.875 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:54.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:54.875 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:29:54.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:54.875 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:29:54.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:54.876 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:29:54.876 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:29:54.876 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:54.876 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:54.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:54.876 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:29:54.876 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:54.876 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:29:54.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:54.879 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:54.880 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:29:54.880 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:29:54.880 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:29:54.881 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:29:54.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:54.881 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:54.881 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:54.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:29:54.881 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:54.882 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:54.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:54.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:54.882 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:54.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:54.882 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:54.883 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:29:54.883 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:29:54.883 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:29:59.886 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:29:59.886 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:29:59.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:59.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:59.890 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:59.890 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:59.899 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:29:59.900 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:59.900 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:59.901 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:29:59.901 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:29:59.904 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:29:59.905 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:29:59.905 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:59.905 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:59.905 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:29:59.905 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:29:59.906 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:29:59.906 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:29:59.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:29:59.908 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:29:59.908 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:29:59.908 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:59.908 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:59.909 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:29:59.909 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:29:59.909 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:29:59.909 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:29:59.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:29:59.911 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:29:59.911 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:29:59.911 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:59.911 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:29:59.911 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:29:59.912 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:29:59.912 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:29:59.912 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:29:59.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:29:59.915 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:29:59.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:29:59.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:29:59.915 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:29:59.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:29:59.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:29:59.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:29:59.916 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:29:59.916 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:29:59.916 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:59.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:59.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:59.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:29:59.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:59.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:59.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:29:59.921 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:30:00.405 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:30:00.450 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:30:00.453 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:30:00.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:30:00.455 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:30:00.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:30:00.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:30:00.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:30:00.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:30:00.458 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:30:00.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:30:00.459 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:30:00.459 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:30:00.495 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:30:00.496 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 03:30:00.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:30:00.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:30:00.883 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:30:00.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:00.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:00.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:00.924 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:01.358 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:30:01.827 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:30:01.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:01.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:01.921 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:01.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:02.296 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:30:02.773 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:30:02.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:02.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:02.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:02.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:03.243 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:30:03.712 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:30:03.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:03.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:03.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:03.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:04.181 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:30:04.649 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:30:04.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:04.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:04.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:04.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:05.116 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:30:05.584 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:30:06.052 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:30:06.522 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:30:06.997 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:30:07.472 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:30:07.945 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:30:08.422 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:30:08.500 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:30:08.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:30:08.500 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:30:08.503 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:08.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:08.503 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:08.503 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:08.504 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:08.504 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:08.504 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:08.504 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:08.504 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:30:08.504 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:30:08.504 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:30:08.504 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:08.504 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:13.504 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:30:13.504 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:30:13.505 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:13.505 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:13.505 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:13.506 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:13.509 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:13.509 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:30:13.509 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:13.509 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:30:13.509 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:30:13.510 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:30:13.510 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:30:13.510 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:30:13.510 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:13.510 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:13.510 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:30:13.510 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:30:13.510 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:30:13.510 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:13.511 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:30:13.511 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:30:13.511 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:30:13.511 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:13.512 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:13.512 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:30:13.512 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:30:13.512 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:30:13.512 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:13.512 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:30:13.512 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:30:13.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:30:13.512 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:13.513 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:13.513 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:30:13.513 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:30:13.513 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:30:13.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:30:13.514 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:30:13.514 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:30:13.514 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:13.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:30:13.515 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:30:13.515 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:13.515 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:18.516 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:30:18.517 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:30:18.517 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:18.517 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:18.517 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:18.518 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:18.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:18.521 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:30:18.521 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:18.521 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:30:18.521 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:30:18.522 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:30:18.522 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:30:18.522 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:30:18.522 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:18.522 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:18.522 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:30:18.522 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:30:18.522 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:30:18.522 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:18.523 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:30:18.523 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:30:18.523 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:30:18.523 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:18.523 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:18.523 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:30:18.523 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:30:18.523 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:30:18.523 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:18.524 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:30:18.524 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:30:18.524 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:30:18.524 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:18.524 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:18.524 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:30:18.524 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:30:18.524 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:30:18.524 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:18.525 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:30:18.525 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:30:18.525 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:30:18.526 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:18.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:18.530 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:30:19.002 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:30:19.039 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:30:19.039 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:30:19.040 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:30:19.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:30:19.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:30:19.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:30:19.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:30:19.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:30:19.041 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:30:19.041 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:30:19.041 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:30:19.041 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:30:19.044 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:30:19.044 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 03:30:19.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:30:19.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:30:19.471 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:30:19.527 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:19.528 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:19.528 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:19.529 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:19.943 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:30:20.419 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:30:20.528 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:20.528 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:20.529 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:20.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:20.894 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:30:21.370 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:30:21.529 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:21.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:21.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:21.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:21.842 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:30:22.313 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:30:22.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:22.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:22.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:22.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:22.783 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:30:23.254 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:30:23.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:23.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:23.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:23.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:23.724 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:30:24.201 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:30:24.678 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:30:25.153 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:30:25.627 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:30:26.104 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:30:26.582 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:30:27.055 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:30:27.524 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:30:27.993 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:30:28.474 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:30:28.949 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:30:29.421 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:30:29.893 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:30:30.363 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:30:30.836 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:30:31.305 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:30:31.776 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:30:32.246 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:30:32.719 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:30:33.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:30:33.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:30:33.049 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:30:33.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:33.054 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:33.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:33.054 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:33.057 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:33.058 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:33.058 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:33.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:33.058 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:30:33.058 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:30:33.058 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:30:33.059 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3135 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:33.059 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3135 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:33.059 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3135 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:33.059 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3135 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:33.059 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3136 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:33.059 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3136 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:33.059 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3136 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:33.059 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3136 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:33.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3136 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:33.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3136 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:33.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3136 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:33.060 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3136 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:38.056 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:30:38.056 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:30:38.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:38.059 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:38.060 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:38.060 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:38.066 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:38.067 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:30:38.067 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:38.067 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:30:38.067 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:30:38.070 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:30:38.070 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:30:38.070 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:30:38.070 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:38.070 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:38.070 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:30:38.071 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:30:38.071 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:30:38.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:38.073 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:30:38.074 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:30:38.074 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:30:38.074 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:38.074 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:38.074 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:30:38.074 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:30:38.074 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:30:38.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:38.076 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:30:38.076 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:30:38.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:30:38.076 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:38.077 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:38.077 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:30:38.077 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:30:38.077 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:30:38.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:38.080 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:30:38.080 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:30:38.080 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:30:38.081 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:30:38.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:38.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:38.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:38.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:30:38.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:38.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:38.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:38.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:38.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:38.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:38.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:38.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:38.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:38.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:38.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:38.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:38.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:38.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:38.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:38.083 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:38.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:38.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:38.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:38.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:38.083 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:38.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:38.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:38.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:38.083 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:30:38.083 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:30:38.083 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:30:43.086 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:30:43.086 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:30:43.087 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:43.089 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:43.093 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:43.093 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:43.108 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:43.109 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:30:43.109 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:43.109 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:30:43.109 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:30:43.112 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:30:43.112 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:30:43.112 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:30:43.112 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:43.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:43.112 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:30:43.113 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:30:43.113 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:30:43.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:43.115 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:30:43.115 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:30:43.115 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:30:43.115 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:43.115 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:43.115 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:30:43.115 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:30:43.115 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:30:43.115 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:43.117 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:30:43.117 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:30:43.117 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:30:43.117 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:43.117 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:43.117 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:30:43.117 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:30:43.117 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:30:43.117 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:43.119 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:30:43.120 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:30:43.120 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:30:43.120 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:43.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:43.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:43.125 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:30:43.597 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:30:43.649 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:30:43.652 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:30:43.654 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:30:43.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:30:43.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:30:43.657 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:30:43.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:30:43.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:30:43.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:30:43.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:30:43.657 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:30:43.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:30:43.686 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:30:43.687 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 03:30:43.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:30:43.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:30:44.071 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:30:44.122 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:44.123 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:44.124 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:44.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:44.540 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:30:45.016 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:30:45.123 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:45.123 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:45.124 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:45.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:45.494 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:30:45.965 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:30:46.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:46.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:46.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:46.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:46.443 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:30:46.916 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:30:47.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:47.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:47.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:47.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:47.386 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:30:47.863 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:30:48.126 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:48.126 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:48.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:48.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:48.336 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:30:48.805 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:30:49.277 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:30:49.748 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:30:50.220 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:30:50.693 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:30:51.165 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:30:51.643 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:30:51.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:30:51.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:30:51.691 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:30:51.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:51.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:51.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:51.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:51.698 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:51.699 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:51.699 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:51.699 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:30:51.699 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:30:51.699 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:30:51.699 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1849 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1849 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1849 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1849 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1849 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1849 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1849 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1849 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1850 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1850 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1850 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1850 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1850 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1850 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1850 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:51.699 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1850 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:30:56.699 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:30:56.699 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:30:56.701 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:56.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:56.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:56.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:56.708 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:56.709 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:30:56.709 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:56.709 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:30:56.709 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:30:56.713 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:30:56.713 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:30:56.714 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:30:56.714 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:56.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:56.715 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:30:56.715 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:30:56.715 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:30:56.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:30:56.716 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:30:56.716 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:30:56.717 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:30:56.717 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:56.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:56.717 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:30:56.717 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:30:56.717 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:30:56.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:30:56.719 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:30:56.719 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:30:56.719 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:30:56.719 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:30:56.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:56.719 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:30:56.719 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:30:56.719 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:30:56.720 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:30:56.722 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:30:56.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:30:56.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:30:56.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:30:56.722 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:30:56.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:30:56.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:30:56.723 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:30:56.723 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:30:56.723 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:30:56.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:56.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:56.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:56.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:56.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:30:56.725 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:30:56.725 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:30:56.725 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:31:01.727 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:31:01.727 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:31:01.728 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:01.730 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:01.731 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:01.733 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:01.742 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:01.742 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:31:01.742 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:01.742 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:31:01.742 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:31:01.743 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:31:01.743 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:31:01.744 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:31:01.744 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:01.744 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:01.744 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:31:01.744 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:31:01.744 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:31:01.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:01.745 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:31:01.745 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:31:01.745 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:31:01.745 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:01.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:01.745 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:31:01.745 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:31:01.745 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:31:01.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:01.746 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:31:01.746 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:31:01.746 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:31:01.746 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:01.746 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:01.746 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:31:01.746 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:31:01.746 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:31:01.746 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:01.747 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:31:01.748 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:31:01.748 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:31:01.748 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:01.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:01.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:01.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:01.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:01.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:01.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:01.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:01.753 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:31:02.221 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:31:02.263 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:31:02.264 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:31:02.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:31:02.264 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:31:02.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:31:02.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:31:02.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:31:02.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:31:02.265 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:31:02.265 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:31:02.265 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:31:02.265 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:31:02.697 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:31:02.749 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:02.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:02.751 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:02.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:03.175 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:31:03.652 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:31:03.750 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:03.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:03.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:03.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:04.130 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:31:04.607 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:31:04.751 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:04.751 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:04.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:04.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:05.085 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:31:05.562 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:31:05.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:05.752 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:05.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:05.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:06.039 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:31:06.516 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:31:06.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:06.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:06.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:06.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:06.994 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:31:07.467 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:31:07.944 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:31:08.421 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:31:08.898 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:31:09.375 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:31:09.853 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:31:10.331 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:31:10.808 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:31:11.283 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:31:11.761 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:31:12.238 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:31:12.316 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:31:12.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:31:12.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:12.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:12.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:12.322 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:12.325 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:12.325 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:12.325 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:12.326 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:12.326 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:31:12.326 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:31:12.326 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:31:12.326 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2264 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:12.326 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2264 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:12.327 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2264 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:12.327 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2264 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:12.327 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2264 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:12.327 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2264 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:12.327 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2265 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:12.327 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2265 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:12.327 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2265 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:12.327 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2265 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:12.327 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2265 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:12.327 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2265 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:12.327 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2265 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:12.328 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2265 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:17.325 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:31:17.325 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:31:17.326 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:17.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:17.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:17.329 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:17.336 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:17.336 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:31:17.337 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:17.337 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:31:17.337 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:31:17.339 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:31:17.340 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:31:17.340 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:31:17.340 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:17.340 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:17.340 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:31:17.340 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:31:17.340 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:31:17.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:17.342 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:31:17.342 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:31:17.343 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:31:17.343 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:17.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:17.343 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:31:17.343 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:31:17.343 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:31:17.343 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:17.345 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:31:17.345 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:31:17.345 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:31:17.345 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:17.345 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:17.345 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:31:17.345 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:31:17.345 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:31:17.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:17.348 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:31:17.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:31:17.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:31:17.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:31:17.348 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:31:17.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:31:17.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:31:17.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:31:17.349 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:31:17.349 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:31:17.349 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:31:17.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:17.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:17.351 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:31:17.351 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:31:17.351 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:31:22.354 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:31:22.354 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:31:22.356 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:22.357 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:22.358 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:22.358 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:22.366 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:22.367 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:31:22.367 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:22.367 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:31:22.367 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:31:22.369 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:31:22.369 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:31:22.369 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:31:22.369 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:22.370 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:22.370 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:31:22.370 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:31:22.370 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:31:22.370 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:22.371 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:31:22.371 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:31:22.371 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:31:22.371 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:22.371 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:22.371 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:31:22.371 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:31:22.371 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:31:22.371 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:22.373 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:31:22.373 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:31:22.373 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:31:22.373 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:22.373 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:22.373 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:31:22.373 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:31:22.373 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:31:22.373 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:22.375 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:31:22.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:31:22.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:31:22.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:31:22.375 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:31:22.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:31:22.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:31:22.376 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:31:22.376 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:31:22.376 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:22.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:22.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:22.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:22.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:22.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:22.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:22.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:22.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:22.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:22.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:22.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:22.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:22.381 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:31:22.862 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:31:22.907 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:31:22.910 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:31:22.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:31:22.912 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:31:22.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:31:22.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:31:22.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:31:22.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:31:22.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:31:22.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:31:22.917 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:31:22.917 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:31:22.953 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:31:22.953 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-05 03:31:22.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:31:22.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:31:23.340 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:31:23.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:23.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:23.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:23.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:23.816 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:31:24.290 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:31:24.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:24.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:24.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:24.383 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:24.767 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:31:25.239 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:31:25.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:25.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:25.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:25.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:25.710 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:31:26.188 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:31:26.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:26.382 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:26.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:26.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:26.667 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:31:27.139 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:31:27.382 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:27.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:27.383 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:27.386 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:27.618 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:31:28.092 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:31:28.562 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:31:29.033 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:31:29.503 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:31:29.978 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:31:30.453 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:31:30.922 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:31:31.397 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:31:31.874 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:31:32.344 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:31:32.813 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:31:33.282 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:31:33.761 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:31:33.958 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:31:33.958 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:31:33.958 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:31:33.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:33.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:33.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:33.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:33.966 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:33.966 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:33.966 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:33.966 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:33.966 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:31:33.967 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:31:33.967 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:31:33.967 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2493 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:33.967 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2493 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:33.967 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2493 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:33.967 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2493 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:33.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2493 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:33.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2493 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:33.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2494 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:33.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2494 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:33.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2494 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:33.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2494 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:33.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2494 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:33.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2494 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:33.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2494 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:33.968 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2494 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:38.966 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:31:38.966 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:31:38.967 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:38.969 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:38.970 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:38.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:38.973 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:38.973 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:31:38.973 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:38.973 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:31:38.973 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:31:38.975 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:31:38.975 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:31:38.976 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:31:38.976 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:38.976 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:38.976 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:31:38.976 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:31:38.976 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:31:38.976 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:38.978 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:31:38.978 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:31:38.978 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:31:38.978 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:38.978 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:38.978 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:31:38.978 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:31:38.978 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:31:38.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:38.980 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:31:38.980 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:31:38.980 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:31:38.980 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:38.980 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:38.980 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:31:38.980 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:31:38.980 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:31:38.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:38.984 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:31:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:31:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:31:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:31:38.984 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:31:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:31:38.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:31:38.985 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:31:38.985 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:31:38.985 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:31:38.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:38.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:38.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:38.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:31:38.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:38.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:38.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:38.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:38.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:38.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:38.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:38.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:38.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:38.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:38.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:38.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:38.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:38.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:38.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:38.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:38.987 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:38.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:38.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:38.988 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:38.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:38.988 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:38.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:38.988 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:38.988 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:31:38.988 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:31:38.988 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:31:43.990 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:31:43.991 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:31:43.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:43.994 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:43.995 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:43.995 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:44.003 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:44.003 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:31:44.003 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:44.003 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:31:44.003 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:31:44.005 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:31:44.005 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:31:44.005 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:31:44.005 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:44.005 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:44.005 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:31:44.006 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:31:44.006 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:31:44.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:44.008 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:31:44.008 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:31:44.008 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:31:44.008 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:44.008 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:44.008 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:31:44.008 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:31:44.008 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:31:44.008 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:44.010 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:31:44.010 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:31:44.010 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:31:44.010 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:44.011 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:44.011 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:31:44.011 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:31:44.011 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:31:44.011 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:44.014 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:31:44.014 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:31:44.014 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:31:44.015 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:44.015 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:44.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:44.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:44.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:44.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:44.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:44.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:44.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:44.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:44.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:44.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:44.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:44.020 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:31:44.496 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:31:44.558 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:31:44.560 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:31:44.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:31:44.563 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:31:44.965 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:31:45.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:45.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:45.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:45.026 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:45.434 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:31:45.910 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:31:46.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:46.020 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:46.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:46.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:46.388 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:31:46.861 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:31:47.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:47.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:47.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:47.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:47.330 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:31:47.800 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:31:48.020 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:48.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:48.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:48.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:48.270 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:31:48.739 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:31:49.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:49.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:49.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:49.029 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:49.208 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:31:49.677 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:31:50.146 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:31:50.616 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:31:51.087 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:31:51.556 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:31:52.025 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:31:52.495 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:31:52.971 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:31:53.439 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:31:53.908 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:31:54.378 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:31:54.575 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:54.576 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:54.576 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:54.576 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:54.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:54.580 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:54.580 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:54.580 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:54.580 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:31:54.580 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:31:54.580 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:31:54.581 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2290 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:54.581 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2290 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:54.581 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2290 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:54.581 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2290 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:54.581 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2290 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:54.581 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2290 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:31:59.577 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:31:59.577 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:31:59.583 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:59.583 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:59.583 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:59.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:59.594 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:59.595 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:31:59.595 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:59.595 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:31:59.595 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:31:59.596 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:31:59.597 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:31:59.597 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:31:59.597 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:59.597 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:59.597 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:31:59.597 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:31:59.597 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:31:59.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:31:59.598 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:31:59.598 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:31:59.598 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:31:59.598 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:59.598 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:31:59.598 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:59.598 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:31:59.598 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:31:59.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:31:59.600 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:31:59.600 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:31:59.600 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:31:59.600 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:31:59.600 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:31:59.600 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:59.600 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:31:59.600 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:31:59.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:31:59.601 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:31:59.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:31:59.602 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:31:59.602 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:31:59.602 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:31:59.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:31:59.603 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:31:59.603 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:31:59.603 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:31:59.603 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:31:59.603 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:31:59.603 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:31:59.603 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:32:04.611 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:32:04.611 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:32:04.611 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:32:04.612 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:32:04.612 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:32:04.612 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:32:04.619 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:32:04.619 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:32:04.619 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:04.619 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:32:04.620 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:32:04.623 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:32:04.623 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:32:04.623 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:32:04.623 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:04.623 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:32:04.624 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:32:04.624 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:32:04.624 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:32:04.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:04.626 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:32:04.627 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:32:04.627 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:32:04.627 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:04.627 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:32:04.627 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:32:04.627 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:32:04.627 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:32:04.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:04.629 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:32:04.630 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:32:04.630 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:32:04.630 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:04.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:32:04.630 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:32:04.630 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:32:04.630 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:32:04.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:04.634 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:04.635 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:32:04.635 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:32:04.635 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:32:04.635 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:32:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:04.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:32:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:04.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:04.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:04.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:04.640 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:32:05.116 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:32:05.165 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:32:05.166 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:32:05.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:32:05.168 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:32:05.592 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:32:05.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:05.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:05.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:05.644 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:06.069 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:32:06.547 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:32:06.639 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:06.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:06.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:06.645 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:07.025 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:32:07.503 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:32:07.640 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:07.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:07.643 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:07.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:07.974 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:32:08.445 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:32:08.641 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:08.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:08.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:08.647 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:08.916 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:32:09.389 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:32:09.642 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:09.642 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:09.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:09.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:09.866 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:32:10.339 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:32:10.808 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:32:11.283 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:32:11.751 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:32:12.221 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:32:12.692 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:32:13.163 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:32:13.633 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:32:14.104 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:32:14.572 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:32:15.041 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:32:15.510 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:32:15.979 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:32:16.448 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:32:16.919 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:32:17.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:17.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:17.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:17.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:17.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:32:17.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:32:17.183 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:32:17.183 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:32:17.183 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:32:17.183 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:32:17.184 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:32:17.184 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2711 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:17.184 [WARNING] transceiver.py:257 (TRX1@172.18.201.20:5700/1) RX TRXD message (ver=1 fn=2711 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:17.184 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2711 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:17.184 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2711 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:17.184 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2711 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:17.184 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2711 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:17.185 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2711 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:17.185 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2711 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:17.185 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2711 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:22.182 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:32:22.183 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:32:22.185 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:32:22.187 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:32:22.188 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:32:22.191 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:32:22.204 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:32:22.205 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:32:22.205 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:22.205 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:32:22.205 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:32:22.207 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:32:22.207 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:32:22.207 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:32:22.207 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:22.207 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:32:22.208 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:32:22.208 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:32:22.208 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:32:22.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:22.209 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:32:22.209 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:32:22.209 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:32:22.209 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:22.209 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:32:22.210 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:32:22.210 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:32:22.210 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:32:22.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:22.211 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:32:22.211 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:32:22.211 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:32:22.211 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:22.211 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:32:22.211 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:32:22.212 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:32:22.212 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:32:22.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:22.213 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:32:22.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:32:22.214 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:32:22.214 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:32:22.214 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:22.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:22.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:22.219 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:32:22.690 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:32:22.750 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:32:22.752 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:32:22.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:32:22.753 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:32:22.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:32:22.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:32:22.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:32:22.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:32:22.755 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:32:22.755 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:32:22.755 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:32:22.755 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:32:23.159 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:32:23.216 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:23.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:23.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:23.221 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:23.633 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:32:24.105 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:32:24.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:24.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:24.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:24.222 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:24.575 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:32:25.046 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:32:25.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:25.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:25.219 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:25.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:25.522 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:32:26.000 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:32:26.219 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:26.220 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:26.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:26.224 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:26.478 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:32:26.956 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:32:27.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:27.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:27.220 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:27.225 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:27.433 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:32:27.911 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:32:28.385 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:32:28.861 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:32:29.330 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:32:29.803 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:32:30.280 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:32:30.752 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:32:31.222 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:32:31.696 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:32:32.174 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:32:32.652 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:32:33.128 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:32:33.601 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:32:33.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:32:33.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:32:33.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:33.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:33.789 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:33.789 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:33.792 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:32:33.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:32:33.792 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:32:33.793 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:32:33.793 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:32:33.793 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:32:33.793 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:32:33.793 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2491 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:33.793 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2491 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:33.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2491 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:33.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2491 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:33.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2491 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:33.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2491 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:33.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2492 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:33.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2492 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:33.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2492 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:33.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2492 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:33.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2492 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:33.794 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2492 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:33.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2492 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:33.795 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2492 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:38.796 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:32:38.796 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:32:38.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:32:38.796 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:32:38.796 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:32:38.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:32:38.798 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:32:38.799 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:32:38.799 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:38.799 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:32:38.799 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:32:38.800 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:32:38.800 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:32:38.800 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:32:38.800 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:38.800 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:32:38.800 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:32:38.800 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:32:38.800 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:32:38.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:38.801 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:32:38.801 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:32:38.801 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:32:38.801 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:38.801 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:32:38.801 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:32:38.801 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:32:38.801 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:32:38.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:38.802 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:32:38.802 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:32:38.802 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:32:38.802 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:38.802 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:32:38.802 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:32:38.802 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:32:38.802 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:32:38.802 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:32:38.804 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:32:38.804 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:32:38.804 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:38.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:38.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:38.809 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:32:39.286 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:32:39.320 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:32:39.321 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:32:39.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:32:39.321 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:32:39.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:32:39.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:32:39.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:32:39.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:32:39.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:32:39.323 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:32:39.323 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:32:39.323 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:32:39.760 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:32:39.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:39.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:39.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:39.808 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:40.231 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:32:40.700 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:32:40.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:40.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:40.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:40.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:41.173 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:32:41.648 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:32:41.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:41.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:41.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:41.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:42.125 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:32:42.599 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:32:42.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:42.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:42.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:42.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:43.075 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:32:43.547 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:32:43.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:43.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:43.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:43.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:44.023 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:32:44.500 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:32:44.974 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:32:45.447 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:32:45.924 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:32:46.402 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:32:46.880 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:32:47.354 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:32:47.832 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:32:48.310 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:32:48.787 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:32:49.256 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:32:49.732 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:32:50.209 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:32:50.686 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:32:51.159 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:32:51.634 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:32:52.108 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:32:52.615 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:32:53.092 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:32:53.569 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:32:54.046 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:32:54.334 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:32:54.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:32:54.338 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:54.338 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:54.338 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:54.339 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:54.342 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:32:54.342 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:32:54.342 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:32:54.342 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:32:54.342 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:32:54.342 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:32:54.342 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:32:54.342 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3329 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:54.342 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3329 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:54.342 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3329 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:54.342 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3329 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:54.342 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3329 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:54.342 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3329 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:54.342 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3329 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:54.342 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3330 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:59.342 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:32:59.342 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:32:59.344 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:32:59.345 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:32:59.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:32:59.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:32:59.354 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:32:59.355 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:32:59.355 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:59.355 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:32:59.355 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:32:59.357 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:32:59.357 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:32:59.357 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:32:59.357 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:59.357 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:32:59.357 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:32:59.357 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:32:59.357 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:32:59.357 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:59.359 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:32:59.360 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:32:59.360 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:32:59.360 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:59.360 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:32:59.360 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:32:59.360 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:32:59.360 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:32:59.360 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:59.362 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:32:59.362 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:32:59.362 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:32:59.362 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:32:59.362 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:32:59.362 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:32:59.362 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:32:59.362 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:32:59.362 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:59.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:59.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:59.366 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:32:59.366 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:32:59.366 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:32:59.366 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:32:59.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:59.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:59.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:59.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:32:59.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:59.366 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:59.366 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:59.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:59.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:59.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:59.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:32:59.370 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:32:59.854 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:32:59.896 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:32:59.898 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:32:59.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:32:59.900 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:32:59.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:32:59.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:32:59.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:32:59.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:32:59.907 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:32:59.907 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:32:59.907 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:32:59.907 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:32:59.950 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:32:59.950 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:32:59.955 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:32:59.955 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:32:59.955 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:32:59.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:32:59.958 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:32:59.958 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:32:59.958 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:32:59.958 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:32:59.958 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:32:59.958 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:32:59.958 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:32:59.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:59.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:59.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:59.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:59.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:59.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:32:59.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:04.957 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:33:04.957 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:33:04.959 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:33:04.960 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:33:04.964 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:33:04.965 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:33:04.972 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:33:04.972 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:33:04.972 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:33:04.972 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:33:04.972 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:33:04.973 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:33:04.973 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:33:04.973 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:33:04.973 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:33:04.973 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:33:04.973 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:33:04.973 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:33:04.973 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:33:04.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:04.975 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:33:04.975 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:33:04.975 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:33:04.975 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:33:04.976 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:33:04.976 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:33:04.976 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:33:04.976 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:33:04.976 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:04.977 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:33:04.977 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:33:04.977 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:33:04.977 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:33:04.978 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:33:04.978 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:33:04.978 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:33:04.978 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:33:04.978 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:04.981 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:33:04.981 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:33:04.981 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:33:04.982 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:33:04.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:04.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:04.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:04.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:33:04.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:04.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:04.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:04.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:04.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:04.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:04.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:04.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:04.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:04.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:04.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:04.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:04.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:04.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:04.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:04.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:04.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:04.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:04.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:04.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:04.987 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:33:05.463 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:33:05.514 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:33:05.516 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:33:05.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:05.518 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:33:05.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:05.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:05.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:05.551 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:05.551 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:05.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:05.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:05.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:05.557 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:05.557 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:05.557 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:33:05.557 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:33:05.600 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:05.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:05.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:05.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:05.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:05.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:05.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:05.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:05.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:05.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:05.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:05.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:05.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:05.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:05.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:05.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:05.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:05.753 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:05.754 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:33:05.754 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:33:05.790 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:33:05.791 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:33:05.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:05.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:05.935 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:33:05.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:05.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:05.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:05.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:05.983 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:33:05.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:05.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:05.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:05.991 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:06.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:06.002 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:06.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:06.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:06.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:06.009 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:06.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:06.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:06.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:06.010 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:06.010 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:33:06.010 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:33:06.023 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:06.023 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:06.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:06.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:06.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:06.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:06.329 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:06.329 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:06.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:06.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:06.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:06.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:06.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:06.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:06.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:06.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:06.355 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:06.355 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:06.355 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:33:06.355 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:33:06.404 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:33:06.404 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:33:06.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:06.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:06.405 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:33:06.878 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:33:06.986 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:06.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:06.989 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:06.992 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:07.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:07.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:07.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:07.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:07.208 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:33:07.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:07.219 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:07.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:07.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:07.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:33:07.224 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:33:07.224 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:33:07.224 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:33:07.224 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:33:07.224 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:33:07.224 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:33:07.225 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=484 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:07.225 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=484 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:07.225 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=484 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:07.225 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=484 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:07.225 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=484 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:07.225 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=484 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:07.225 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=485 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:07.226 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=485 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:07.226 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=485 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:07.226 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=485 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:07.226 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=485 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:07.226 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=485 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:07.226 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=485 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:07.226 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=485 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:12.222 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:33:12.222 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:33:12.224 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:33:12.225 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:33:12.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:33:12.230 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:33:12.243 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:33:12.244 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:33:12.244 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:33:12.245 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:33:12.245 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:33:12.247 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:33:12.247 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:33:12.248 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:33:12.248 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:33:12.248 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:33:12.248 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:33:12.248 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:33:12.249 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:33:12.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:12.249 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:33:12.250 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:33:12.250 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:33:12.250 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:33:12.250 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:33:12.250 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:33:12.250 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:33:12.250 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:33:12.250 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:12.252 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:33:12.252 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:33:12.252 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:33:12.252 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:33:12.252 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:33:12.252 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:33:12.252 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:33:12.252 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:33:12.252 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:12.254 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:33:12.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:33:12.254 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:33:12.254 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:33:12.254 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:33:12.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:33:12.255 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:33:12.255 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:33:12.255 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:12.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:12.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:12.260 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:33:12.736 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:33:12.783 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:33:12.784 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:33:12.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:12.785 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:33:12.799 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:12.799 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:12.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:12.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:12.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:12.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:12.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:12.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:12.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:12.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:12.823 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:33:12.823 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:33:12.827 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:12.827 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:12.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:12.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:13.210 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:33:13.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:13.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:13.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:13.265 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:13.686 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:33:14.161 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:33:14.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:14.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:14.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:14.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:14.638 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:33:15.116 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:33:15.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:15.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:15.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:15.268 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:15.593 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:33:16.071 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:33:16.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:16.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:16.265 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:16.270 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:16.548 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:33:17.021 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:33:17.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:17.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:17.265 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:17.270 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:17.500 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:33:17.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:17.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:17.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:17.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:17.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:17.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:17.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:17.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:17.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:17.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:17.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:17.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:17.863 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:17.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:17.863 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:33:17.863 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:33:17.870 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:33:17.870 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:33:17.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:17.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:17.977 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:33:18.452 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:33:18.927 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:33:19.396 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:33:19.866 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:33:20.336 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:33:20.807 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:33:21.278 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:33:21.749 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:33:22.219 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:33:22.692 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:33:22.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:22.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:22.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:22.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:22.878 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:33:22.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:22.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:22.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:22.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:22.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:22.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:22.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:22.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:22.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:22.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:22.906 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:33:22.906 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:33:22.922 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:22.922 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:22.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:22.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:23.164 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:33:23.642 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:33:24.114 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:33:24.590 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:33:25.068 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:33:25.543 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:33:26.016 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:33:26.494 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:33:26.968 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:33:27.437 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:33:27.907 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:33:27.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:27.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:27.931 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:27.931 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:27.949 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:27.949 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:27.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:27.955 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:27.955 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:27.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:27.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:27.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:27.957 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:27.957 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:27.957 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:33:27.957 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:33:27.999 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:33:27.999 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:33:28.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:28.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:28.380 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:33:28.849 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:33:29.320 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:33:29.794 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:33:30.266 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:33:30.739 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:33:31.217 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:33:31.691 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:33:32.162 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:33:32.634 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:33:33.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:33.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:33.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:33.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:33.009 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:33:33.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:33.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:33.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:33.020 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:33.022 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:33:33.022 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:33:33.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:33:33.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:33:33.023 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:33:33.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:33:33.023 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:33:33.023 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4472 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.023 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4472 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4472 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4472 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4472 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4472 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4472 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4473 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4473 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4473 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4473 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4473 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.024 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4473 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.025 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4473 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:33.025 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4473 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:33:38.022 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:33:38.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:33:38.024 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:33:38.026 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:33:38.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:33:38.027 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:33:38.036 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:33:38.037 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:33:38.037 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:33:38.038 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:33:38.038 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:33:38.040 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:33:38.040 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:33:38.040 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:33:38.041 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:33:38.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:33:38.041 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:33:38.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:33:38.041 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:33:38.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:38.044 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:33:38.044 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:33:38.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:33:38.044 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:33:38.044 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:33:38.044 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:33:38.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:33:38.044 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:33:38.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:38.047 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:33:38.047 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:33:38.047 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:33:38.047 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:33:38.047 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:33:38.047 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:33:38.047 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:33:38.047 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:33:38.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:38.051 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:33:38.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:33:38.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:33:38.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:38.052 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:33:38.052 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:33:38.052 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:33:38.053 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:33:38.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:38.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:38.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:38.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:33:38.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:38.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:38.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:38.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:38.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:38.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:38.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:38.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:38.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:38.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:38.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:38.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:38.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:33:38.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:38.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:33:38.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:38.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:33:38.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:38.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:38.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:38.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:33:38.058 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:33:38.532 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:33:38.591 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:33:38.594 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:33:38.595 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:33:38.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:38.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:38.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:38.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:38.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:38.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:38.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:38.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:38.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:38.633 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:38.633 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:38.633 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:33:38.633 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:33:38.669 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:38.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:38.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:38.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:39.004 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:33:39.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:39.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:39.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:39.063 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:39.477 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:33:39.947 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:33:40.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:40.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:40.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:40.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:40.425 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:33:40.897 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:33:41.058 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:41.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:41.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:41.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:41.368 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:33:41.838 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:33:42.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:42.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:42.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:42.066 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:42.313 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:33:42.785 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:33:43.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:43.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:43.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:43.066 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:43.262 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:33:43.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:43.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:43.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:43.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:43.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:43.698 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:43.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:43.704 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:43.704 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:43.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:43.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:43.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:43.706 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:43.706 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:43.706 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:33:43.706 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:33:43.732 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:33:43.733 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:33:43.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:43.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:43.738 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:33:44.211 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:33:44.689 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:33:45.167 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:33:45.641 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:33:46.111 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:33:46.581 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:33:47.052 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:33:47.523 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:33:47.998 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:33:48.476 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:33:48.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:48.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:48.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:48.742 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:48.742 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:33:48.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:48.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:48.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:48.760 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:48.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:48.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:48.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:48.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:48.762 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:48.762 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:48.762 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:33:48.762 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:33:48.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:48.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:48.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:48.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:48.951 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:33:49.428 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:33:49.906 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:33:50.384 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:33:50.861 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:33:51.334 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:33:51.811 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:33:52.288 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:33:52.765 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:33:53.243 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:33:53.716 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:33:53.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:53.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:53.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:53.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:53.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:53.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:53.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:53.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:53.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:53.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:33:53.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:53.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:53.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:33:53.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:33:53.838 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:33:53.838 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:33:53.849 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:33:53.849 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:33:53.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:53.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:54.187 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:33:54.658 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:33:55.133 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:33:55.611 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:33:56.089 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:33:56.567 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:33:57.046 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:33:57.524 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:33:58.000 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:33:58.469 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:33:58.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:33:58.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:33:58.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:33:58.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:33:58.858 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:33:58.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:33:58.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:33:58.869 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:33:58.869 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:33:58.871 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:33:58.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:33:58.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:33:58.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:33:58.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:33:58.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:33:58.872 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:34:03.870 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:34:03.870 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:34:03.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:34:03.873 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:34:03.877 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:34:03.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:34:03.892 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:34:03.893 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:34:03.893 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:34:03.893 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:34:03.893 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:34:03.895 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:34:03.895 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:34:03.896 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:34:03.896 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:34:03.896 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:34:03.896 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:34:03.896 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:34:03.896 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:34:03.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:03.897 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:34:03.897 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:34:03.898 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:34:03.898 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:34:03.898 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:34:03.898 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:34:03.898 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:34:03.898 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:34:03.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:03.899 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:34:03.899 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:34:03.899 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:34:03.899 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:34:03.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:34:03.900 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:34:03.900 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:34:03.900 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:34:03.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:03.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:34:03.903 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:34:03.903 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:34:03.903 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:03.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:03.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:03.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:03.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:03.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:03.907 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:34:04.380 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:34:04.440 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:34:04.441 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:34:04.442 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:34:04.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:04.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:04.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:04.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:04.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:04.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:04.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:04.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:04.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:04.481 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:04.481 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:04.481 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:34:04.481 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:34:04.518 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:04.518 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:04.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:04.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:04.853 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:34:04.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:04.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:04.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:04.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:05.328 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:34:05.801 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:34:05.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:05.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:05.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:05.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:06.276 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:34:06.754 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:34:06.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:06.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:06.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:06.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:07.229 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:34:07.698 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:34:07.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:07.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:07.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:07.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:08.168 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:34:08.638 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:34:08.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:08.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:08.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:08.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:09.112 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:34:09.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:09.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:09.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:09.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:09.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:09.545 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:09.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:09.551 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:09.551 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:09.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:09.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:09.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:09.553 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:09.553 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:09.553 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:34:09.553 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:34:09.578 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:34:09.578 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:34:09.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:09.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:09.589 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:34:10.063 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:34:10.542 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:34:11.014 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:34:11.484 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:34:11.955 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:34:12.426 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:34:12.897 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:34:13.367 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:34:13.841 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:34:14.311 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:34:14.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:14.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:14.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:14.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:14.586 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:34:14.601 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:14.601 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:14.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:14.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:14.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:14.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:14.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:14.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:14.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:14.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:14.609 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:34:14.609 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:34:14.635 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:14.635 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:14.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:14.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:14.780 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:34:15.258 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:34:15.735 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:34:16.213 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:34:16.691 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:34:17.169 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:34:17.647 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:34:18.121 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:34:18.599 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:34:19.076 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:34:19.555 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:34:19.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:19.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:19.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:19.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:19.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:19.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:19.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:19.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:19.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:19.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:19.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:19.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:19.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:19.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:19.668 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:34:19.668 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:34:19.692 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:34:19.693 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:34:19.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:19.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:20.026 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:34:20.497 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:34:20.973 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:34:21.449 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:34:21.923 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:34:22.393 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:34:22.868 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:34:23.347 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:34:23.820 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:34:24.298 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:34:24.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:24.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:24.702 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:24.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:24.703 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:34:24.713 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:24.713 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:24.714 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:24.714 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:24.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:34:24.717 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:34:24.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:34:24.718 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:34:24.718 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:34:24.718 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:34:24.718 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:34:24.718 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4478 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.718 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4478 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4478 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4478 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4478 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4478 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4478 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4479 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4479 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4479 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4479 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4479 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4479 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.719 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4479 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:24.720 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4479 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:29.716 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:34:29.716 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:34:29.718 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:34:29.720 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:34:29.720 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:34:29.720 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:34:29.728 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:34:29.729 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:34:29.729 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:34:29.729 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:34:29.729 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:34:29.729 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:34:29.729 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:34:29.729 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:34:29.730 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:34:29.730 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:34:29.730 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:34:29.730 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:34:29.730 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:34:29.730 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:29.733 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:34:29.734 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:34:29.734 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:34:29.734 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:34:29.734 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:34:29.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:34:29.734 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:34:29.734 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:34:29.734 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:29.737 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:34:29.737 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:34:29.737 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:34:29.737 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:34:29.738 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:34:29.738 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:34:29.738 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:34:29.738 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:34:29.738 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:29.741 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:34:29.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:34:29.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:34:29.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:34:29.741 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:34:29.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:34:29.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:34:29.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:34:29.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:34:29.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:29.741 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:34:29.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:34:29.742 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:34:29.742 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:29.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:29.747 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:34:30.216 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:34:30.274 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:34:30.276 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:34:30.277 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:34:30.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:30.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:30.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:30.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:30.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:30.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:30.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:30.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:30.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:30.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:30.313 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:30.313 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:34:30.313 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:34:30.355 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:30.356 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:30.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:30.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:30.688 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:34:30.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:30.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:30.747 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:30.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:31.165 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:34:31.643 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:34:31.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:31.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:31.747 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:31.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:32.122 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:34:32.598 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:34:32.747 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:32.747 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:32.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:32.751 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:33.074 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:34:33.552 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:34:33.747 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:33.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:33.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:33.752 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:34.029 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:34:34.503 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:34:34.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:34.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:34.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:34.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:34.973 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:34:35.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:35.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:35.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:35.364 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:35.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:35.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:35.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:35.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:35.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:35.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:35.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:35.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:35.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:35.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:35.393 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:34:35.393 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:34:35.442 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:34:35.442 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:34:35.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:35.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:35.443 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:34:35.913 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:34:36.387 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:34:36.865 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:34:37.336 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:34:37.809 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:34:38.282 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:34:38.752 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:34:39.221 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:34:39.691 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:34:40.161 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:34:40.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:40.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:40.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:40.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:40.453 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:34:40.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:40.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:40.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:40.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:40.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:40.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:40.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:40.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:40.481 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:40.481 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:40.481 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:34:40.481 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:34:40.485 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:40.485 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:40.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:40.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:40.633 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:34:41.111 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:34:41.584 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:34:42.054 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:34:42.527 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:34:43.005 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:34:43.482 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:34:43.957 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:34:44.435 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:34:44.912 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:34:45.390 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:34:45.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:45.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:45.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:45.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:45.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:45.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:45.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:45.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:45.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:45.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:45.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:45.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:45.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:45.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:45.517 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:34:45.517 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:34:45.525 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:34:45.525 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:34:45.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:45.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:45.862 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:34:46.335 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:34:46.814 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:34:47.290 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:34:47.767 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:34:48.245 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:34:48.722 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:34:49.199 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:34:49.674 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:34:50.146 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:34:50.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:50.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:50.532 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:50.532 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:50.532 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:34:50.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:50.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:50.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:50.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:50.557 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:34:50.557 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:34:50.557 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:34:50.557 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:34:50.557 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:34:50.557 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:34:50.557 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:34:50.558 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4476 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.558 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4476 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.558 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4476 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.558 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4476 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.558 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4476 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.558 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4476 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.558 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4476 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.558 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4476 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.558 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4477 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.559 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4477 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.559 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4477 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.559 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4477 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.559 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4477 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.559 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4477 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.559 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4477 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:50.559 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4477 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:55.556 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:34:55.557 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:34:55.558 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:34:55.559 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:34:55.559 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:34:55.560 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:34:55.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:34:55.566 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:34:55.566 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:34:55.566 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:34:55.566 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:34:55.568 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:34:55.568 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:34:55.568 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:34:55.568 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:34:55.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:34:55.568 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:34:55.568 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:34:55.568 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:34:55.568 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:55.570 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:34:55.570 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:34:55.570 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:34:55.570 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:34:55.570 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:34:55.570 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:34:55.570 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:34:55.570 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:34:55.570 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:55.572 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:34:55.572 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:34:55.572 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:34:55.572 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:34:55.572 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:34:55.572 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:34:55.572 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:34:55.572 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:34:55.572 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:55.574 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:34:55.574 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:34:55.574 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:34:55.575 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:55.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:34:55.579 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:34:56.056 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:34:56.099 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:34:56.100 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:34:56.102 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:34:56.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:56.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:56.128 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:56.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:56.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:56.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:56.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:56.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:56.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:56.146 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:56.146 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:56.146 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:34:56.146 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:34:56.193 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:56.193 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:56.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:56.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:56.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:56.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:56.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:56.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:56.454 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:56.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:56.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:56.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:56.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:56.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:56.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:56.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:56.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:56.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:56.463 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:34:56.463 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:34:56.473 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:34:56.473 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:34:56.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:56.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:56.528 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:34:56.576 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:56.576 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:56.578 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:56.580 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:56.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:56.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:56.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:56.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:56.858 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:34:56.875 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:56.875 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:56.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:56.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:56.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:56.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:56.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:56.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:56.882 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:56.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:56.882 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:34:56.882 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:34:56.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:56.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:56.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:56.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:56.999 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:34:57.477 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:34:57.578 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:57.578 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:57.578 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:57.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:57.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:57.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:57.638 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:57.638 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:57.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:57.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:57.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:57.661 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:57.661 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:57.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:34:57.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:57.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:57.663 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:34:57.663 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:34:57.663 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:34:57.663 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:34:57.713 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:34:57.713 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:34:57.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:57.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:57.949 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:34:58.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:34:58.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:34:58.272 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:34:58.272 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:34:58.272 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:34:58.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:34:58.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:34:58.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:34:58.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:34:58.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:34:58.286 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:34:58.286 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:34:58.286 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:34:58.287 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:34:58.287 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:34:58.287 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:34:58.287 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=584 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.287 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=584 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.287 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=584 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.288 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=584 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.288 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=584 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.288 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=584 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.288 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=584 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.288 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=585 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.288 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=585 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.288 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=585 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.288 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=585 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.288 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=585 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.288 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=585 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.288 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=585 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:34:58.288 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=585 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:35:03.286 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:35:03.286 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:35:03.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:35:03.289 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:35:03.289 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:35:03.289 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:35:03.296 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:35:03.298 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:35:03.298 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:35:03.299 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:35:03.299 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:35:03.302 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:35:03.303 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:35:03.303 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:35:03.303 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:35:03.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:35:03.303 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:35:03.304 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:35:03.304 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:35:03.304 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:35:03.307 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:35:03.307 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:35:03.308 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:35:03.308 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:35:03.308 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:35:03.308 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:35:03.308 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:35:03.308 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:35:03.308 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:35:03.311 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:35:03.311 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:35:03.311 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:35:03.311 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:35:03.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:35:03.312 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:35:03.312 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:35:03.312 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:35:03.312 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:35:03.316 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:35:03.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:35:03.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:35:03.316 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:35:03.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:35:03.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:35:03.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:35:03.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:35:03.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:35:03.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:35:03.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:35:03.317 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:35:03.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:35:03.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:35:03.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:35:03.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:35:03.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:35:03.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:35:03.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:35:03.317 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:35:03.317 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:35:03.317 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:35:03.317 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:35:03.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:35:03.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:35:03.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:35:03.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:35:03.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:35:03.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:35:03.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:35:03.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:35:03.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:35:03.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:35:03.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:35:03.322 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:35:03.791 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:35:03.855 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:35:03.857 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:35:03.858 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:35:03.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:35:03.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:35:03.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:35:03.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:35:03.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:35:03.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:35:03.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:35:03.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:35:03.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:35:03.905 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:35:03.905 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:35:03.905 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:35:03.905 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:35:03.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:35:03.928 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:35:03.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:35:03.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:35:04.260 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:35:04.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:35:04.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:35:04.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:35:04.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:35:04.738 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:35:05.215 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:35:05.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:35:05.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:35:05.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:35:05.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:35:05.693 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:35:06.171 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:35:06.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:35:06.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:35:06.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:35:06.328 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:35:06.648 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:35:07.126 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:35:07.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:35:07.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:35:07.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:35:07.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:35:07.604 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:35:08.082 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:35:08.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:35:08.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:35:08.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:35:08.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:35:08.557 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:35:09.027 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:35:09.502 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:35:09.980 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:35:10.458 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:35:10.935 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:35:11.413 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:35:11.887 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:35:12.364 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:35:12.837 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:35:13.312 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:35:13.790 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:35:14.264 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:35:14.742 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:35:15.219 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:35:15.697 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:35:16.175 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:35:16.652 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:35:17.130 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:35:17.602 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:35:18.079 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:35:18.553 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:35:19.025 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:35:19.494 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:35:19.971 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:35:20.449 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:35:20.926 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:35:21.404 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:35:21.882 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:35:22.359 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:35:22.836 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:35:23.307 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:35:23.779 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:35:23.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:35:23.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:35:23.936 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:35:23.936 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:35:23.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:35:23.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:35:23.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:35:23.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:35:23.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:35:23.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:35:23.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:35:23.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:35:23.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:35:23.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:35:23.961 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:35:23.961 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:35:24.012 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:35:24.013 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:35:24.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:35:24.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:35:24.251 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:35:24.721 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:35:25.200 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:35:25.678 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:35:26.157 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:35:26.635 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:35:27.113 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:35:27.591 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:35:28.070 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:35:28.548 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:35:29.027 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:35:29.505 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:35:29.975 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 03:35:30.444 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 03:35:30.914 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 03:35:31.385 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 03:35:31.855 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 03:35:32.327 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 03:35:32.797 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 03:35:33.268 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 03:35:33.739 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 03:35:34.210 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 03:35:34.680 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 03:35:35.151 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 03:35:35.625 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 03:35:36.094 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 03:35:36.564 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 03:35:37.034 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 03:35:37.505 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 03:35:37.982 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 03:35:38.453 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 03:35:38.929 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 03:35:39.406 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 03:35:39.885 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 03:35:40.356 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 03:35:40.830 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 03:35:41.300 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 03:35:41.769 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 03:35:42.242 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 03:35:42.715 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 03:35:43.185 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 03:35:43.654 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 03:35:44.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:35:44.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:35:44.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:35:44.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:35:44.027 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:35:44.043 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:35:44.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:35:44.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:35:44.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:35:44.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:35:44.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:35:44.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:35:44.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:35:44.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:35:44.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:35:44.051 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:35:44.051 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:35:44.073 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:35:44.073 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:35:44.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:35:44.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:35:44.124 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 03:35:44.596 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 03:35:45.070 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 03:35:45.542 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 03:35:46.018 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 03:35:46.495 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 03:35:46.973 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 03:35:47.450 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 03:35:47.927 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 03:35:48.404 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 03:35:48.882 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 03:35:49.360 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 03:35:49.833 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 03:35:50.309 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 03:35:50.787 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 03:35:51.259 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 03:35:51.733 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 03:35:52.208 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 03:35:52.681 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 03:35:53.158 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 03:35:53.631 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 03:35:54.109 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 03:35:54.587 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 03:35:55.064 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 03:35:55.541 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 03:35:56.018 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 03:35:56.492 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 03:35:56.962 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 03:35:57.431 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 03:35:57.909 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 03:35:58.387 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 03:35:58.863 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 03:35:59.335 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 03:35:59.810 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 03:36:00.288 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 03:36:00.765 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 03:36:01.243 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 03:36:01.721 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 03:36:02.199 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 03:36:02.676 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 03:36:03.154 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 03:36:03.632 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-05 03:36:04.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:04.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:04.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:04.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:04.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:04.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:04.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:04.108 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-05 03:36:04.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:04.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:04.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:04.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:04.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:04.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:04.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:04.112 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:04.112 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:04.153 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:36:04.153 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:36:04.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:04.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:04.582 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-05 03:36:05.061 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-05 03:36:05.535 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-05 03:36:06.014 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-05 03:36:06.492 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-05 03:36:06.969 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-05 03:36:07.440 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-05 03:36:07.913 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-05 03:36:08.383 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-05 03:36:08.853 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-05 03:36:09.324 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-05 03:36:09.794 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-05 03:36:10.265 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-05 03:36:10.736 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-05 03:36:11.207 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-05 03:36:11.678 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-05 03:36:12.155 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-05 03:36:12.625 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-05 03:36:13.097 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-05 03:36:13.571 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-05 03:36:14.043 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-05 03:36:14.519 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-05 03:36:14.992 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-05 03:36:15.471 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-05 03:36:15.948 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-05 03:36:16.420 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-05 03:36:16.900 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-05 03:36:17.379 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-05 03:36:17.855 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-05 03:36:18.332 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-05 03:36:18.809 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-05 03:36:19.285 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-05 03:36:19.762 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-05 03:36:20.231 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-05 03:36:20.705 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-05 03:36:21.178 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-05 03:36:21.650 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-05 03:36:22.128 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-05 03:36:22.597 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-05 03:36:23.066 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-05 03:36:23.536 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-05 03:36:24.014 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-05 03:36:24.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:24.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:24.159 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:24.159 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:24.159 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:36:24.163 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:36:24.163 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:36:24.163 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:36:24.163 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:36:24.164 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:36:24.165 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:36:24.165 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:36:24.165 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:36:24.165 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:36:24.165 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:36:24.165 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:36:29.165 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:36:29.165 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:36:29.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:36:29.168 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:36:29.172 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:36:29.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:36:29.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:36:29.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:36:29.184 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:36:29.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:36:29.184 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:36:29.186 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:36:29.186 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:36:29.186 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:36:29.186 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:36:29.186 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:36:29.186 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:36:29.186 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:36:29.186 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:36:29.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:36:29.187 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:36:29.187 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:36:29.187 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:36:29.187 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:36:29.187 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:36:29.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:36:29.188 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:36:29.188 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:36:29.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:36:29.189 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:36:29.189 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:36:29.189 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:36:29.189 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:36:29.189 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:36:29.189 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:36:29.189 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:36:29.189 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:36:29.189 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:36:29.191 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:36:29.191 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:36:29.191 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:29.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:29.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:36:29.192 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:36:29.192 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:36:29.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:36:29.192 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:36:29.192 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:36:29.192 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:36:34.199 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:36:34.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:36:34.200 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:36:34.200 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:36:34.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:36:34.200 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:36:34.207 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:36:34.207 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:36:34.207 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:36:34.207 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:36:34.207 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:36:34.207 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:36:34.208 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:36:34.208 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:36:34.208 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:36:34.208 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:36:34.208 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:36:34.208 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:36:34.208 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:36:34.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:36:34.208 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:36:34.208 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:36:34.208 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:36:34.208 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:36:34.208 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:36:34.209 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:36:34.209 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:36:34.209 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:36:34.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:36:34.209 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:36:34.209 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:36:34.209 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:36:34.209 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:36:34.209 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:36:34.209 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:36:34.210 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:36:34.210 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:36:34.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:36:34.213 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:36:34.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:36:34.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:36:34.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:36:34.213 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:36:34.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:36:34.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:36:34.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:36:34.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:36:34.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:36:34.214 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:36:34.214 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:36:34.214 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:34.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:34.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:34.219 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:36:34.697 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:36:34.752 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:36:34.754 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:36:34.755 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:36:34.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:34.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:34.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:34.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:34.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:34.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:34.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:34.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:34.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:34.797 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:34.797 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:34.797 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:34.797 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:34.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:34.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:34.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:34.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:35.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:35.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:35.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:35.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:35.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:35.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:35.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:35.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:35.053 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:35.053 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:35.069 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:35.069 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:35.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.173 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:36:35.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:36:35.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:36:35.222 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:36:35.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:36:35.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:35.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:35.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:35.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:35.299 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:35.299 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:35.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:35.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.301 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:35.301 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:35.301 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:35.301 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:35.308 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:35.309 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:35.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.309 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:35.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:35.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:35.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:35.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:35.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:35.550 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:35.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:35.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:35.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:35.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.553 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:35.553 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:35.553 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:35.553 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:35.594 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:36:35.594 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:36:35.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.646 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:36:35.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:35.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:35.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:35.900 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:36:35.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:35.918 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:35.918 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:35.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:35.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.920 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:35.920 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:35.920 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:35.920 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:35.922 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:36:35.922 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:36:35.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:35.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:36.116 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:36:36.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:36:36.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:36.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:36:36.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:36.222 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:36:36.224 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:36.224 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:36.225 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:36:36.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:36:36.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:36.240 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:36.240 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:36.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:36.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:36.241 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:36.241 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:36.241 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:36.241 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:36.249 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:36:36.249 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:36:36.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:36.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:36.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:36.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:36.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:36.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:36.547 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:36:36.563 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:36.563 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:36.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:36.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:36.569 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:36.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:36.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:36.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:36.571 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:36.571 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:36.571 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:36.571 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:36.583 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:36.583 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:36.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:36.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:36.589 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:36:37.059 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:36:37.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:36:37.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:36:37.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:36:37.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:36:37.534 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:36:38.012 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:36:38.221 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:36:38.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:36:38.225 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:36:38.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:36:38.486 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:36:38.955 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:36:39.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:39.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:39.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:39.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:39.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:39.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:39.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:39.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:39.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:39.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:39.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:39.132 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:39.133 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:39.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:39.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:39.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:39.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:39.221 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:36:39.222 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:36:39.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:36:39.230 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:36:39.428 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:36:39.902 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:36:40.374 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:36:40.851 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:36:41.329 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:36:41.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:41.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:41.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:41.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:41.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:41.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:41.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:41.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:41.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:41.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:41.741 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:41.741 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:41.741 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:41.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:41.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:41.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:41.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:41.805 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:36:42.283 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:36:42.761 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:36:43.238 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:36:43.716 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:36:44.188 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:36:44.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:44.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:44.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:44.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:44.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:44.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:44.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:44.373 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:44.373 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:44.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:44.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:44.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:44.375 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:44.375 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:44.375 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:44.375 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:44.422 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:36:44.422 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:36:44.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:44.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:44.659 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:36:45.137 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:36:45.615 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:36:46.090 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:36:46.563 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:36:47.040 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:36:47.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:47.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:47.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:47.127 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:47.127 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:36:47.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:47.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:47.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:47.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:47.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:47.146 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:47.146 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:47.146 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:47.146 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:47.179 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:36:47.179 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:36:47.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:47.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:47.516 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:36:47.992 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:36:48.468 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:36:48.942 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:36:49.420 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:36:49.892 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:36:49.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:49.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:49.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:49.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:49.979 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:36:49.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:49.996 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:49.996 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:49.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:49.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:49.998 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:49.998 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:49.998 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:49.998 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:50.027 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:36:50.027 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:36:50.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:50.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:50.362 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:36:50.832 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:36:51.306 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:36:51.775 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:36:52.245 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:36:52.716 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:36:52.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:52.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:52.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:52.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:52.801 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:36:52.814 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:36:52.814 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:36:52.814 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:36:52.814 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:36:52.818 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:36:52.818 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:36:52.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:36:52.818 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:36:52.818 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:36:52.818 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:36:52.819 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:36:52.819 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4001 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:52.819 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4001 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:52.819 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4001 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:52.819 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4001 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:52.819 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4001 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:52.820 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4001 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:52.820 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4002 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:52.820 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4002 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:52.820 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4002 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:52.820 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4002 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:52.820 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4002 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:52.820 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4002 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:52.820 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4002 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:52.820 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4002 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:36:57.817 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:36:57.818 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:36:57.821 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:36:57.821 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:36:57.821 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:36:57.821 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:36:57.836 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:36:57.837 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:36:57.837 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:36:57.837 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:36:57.838 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:36:57.840 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:36:57.841 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:36:57.841 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:36:57.841 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:36:57.841 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:36:57.841 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:36:57.841 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:36:57.841 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:36:57.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:36:57.843 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:36:57.843 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:36:57.843 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:36:57.843 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:36:57.844 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:36:57.844 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:36:57.844 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:36:57.844 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:36:57.844 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:36:57.846 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:36:57.846 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:36:57.846 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:36:57.846 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:36:57.846 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:36:57.846 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:36:57.846 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:36:57.846 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:36:57.846 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:36:57.848 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:36:57.849 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:36:57.849 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:36:57.849 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:36:57.849 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:57.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:57.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:36:57.854 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:36:58.329 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:36:58.383 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:36:58.384 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:36:58.385 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:36:58.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:58.396 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:58.396 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:58.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:58.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:36:58.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:36:58.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:36:58.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:36:58.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:58.412 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:58.412 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:58.412 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:36:58.412 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:36:58.420 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:36:58.420 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:36:58.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:58.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:36:58.798 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:36:58.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:36:58.852 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:36:58.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:36:58.856 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:36:59.277 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:36:59.754 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:36:59.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:36:59.853 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:36:59.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:36:59.857 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:00.232 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:37:00.710 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:37:00.853 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:00.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:00.854 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:00.858 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:01.188 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:37:01.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:01.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:01.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:01.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:01.563 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:01.563 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:01.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:01.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:01.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:01.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:01.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:01.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:01.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:01.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:01.572 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:37:01.572 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:37:01.607 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:37:01.608 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:37:01.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:01.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:01.664 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:37:01.854 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:01.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:01.854 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:01.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:02.133 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:37:02.601 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:37:02.855 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:02.855 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:02.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:02.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:03.069 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:37:03.539 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:37:04.010 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:37:04.489 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:37:04.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:04.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:04.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:04.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:04.790 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:37:04.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:04.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:04.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:04.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:04.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:04.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:04.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:04.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:04.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:04.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:04.817 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:37:04.817 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:37:04.863 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:04.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:04.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:04.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:04.967 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:37:05.445 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:37:05.922 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:37:06.400 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:37:06.878 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:37:07.357 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:37:07.835 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:37:08.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:08.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:08.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:08.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:08.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:08.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:08.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:08.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:08.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:08.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:08.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:08.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:08.216 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:08.216 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:08.216 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:37:08.216 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:37:08.254 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:37:08.254 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:37:08.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:08.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:08.312 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:37:08.786 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:37:09.256 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:37:09.728 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:37:10.201 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:37:10.676 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:37:11.148 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:37:11.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:11.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:11.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:11.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:11.470 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:37:11.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:11.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:11.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:11.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:11.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:37:11.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:37:11.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:37:11.485 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:37:11.485 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:37:11.485 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:37:11.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:37:11.486 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2931 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:11.486 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2931 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:11.486 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2931 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:11.486 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2931 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:11.486 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2931 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:11.486 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2931 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:11.487 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=2931 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:16.487 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:37:16.488 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:37:16.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:37:16.488 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:37:16.488 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:37:16.488 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:37:16.497 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:37:16.498 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:37:16.499 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:37:16.499 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:37:16.499 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:37:16.503 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:37:16.503 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:37:16.503 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:37:16.503 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:37:16.503 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:37:16.503 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:37:16.504 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:37:16.504 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:37:16.504 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:16.506 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:37:16.507 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:37:16.507 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:37:16.507 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:37:16.507 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:37:16.507 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:37:16.507 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:37:16.507 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:37:16.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:16.509 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:37:16.510 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:37:16.510 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:37:16.510 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:37:16.510 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:37:16.510 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:37:16.510 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:37:16.510 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:37:16.510 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:16.513 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:37:16.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:37:16.513 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:37:16.513 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:37:16.513 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:37:16.513 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:37:16.514 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:37:16.514 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:37:16.514 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:37:16.514 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:16.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:16.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:16.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:16.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:16.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:16.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:16.519 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:37:16.995 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:37:17.049 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:37:17.051 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:37:17.052 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:37:17.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:17.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:17.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:17.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:17.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:17.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:17.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:17.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:17.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:17.081 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:17.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:17.081 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:37:17.081 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:37:17.084 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:17.084 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:17.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:17.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:17.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:17.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:17.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:17.414 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:17.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:17.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:17.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:17.438 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:17.438 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:17.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:17.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:17.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:17.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:17.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:17.440 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:37:17.440 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:37:17.465 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:37:17.465 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:37:17.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:17.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:17.471 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:37:17.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:17.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:17.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:17.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:17.940 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:37:17.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:17.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:17.954 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:17.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:17.954 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:37:17.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:17.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:17.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:17.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:17.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:17.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:17.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:17.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:17.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:17.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:17.980 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:37:17.980 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:37:18.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:18.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:18.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:18.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:18.415 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:37:18.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:18.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:18.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:18.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:18.892 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:37:19.366 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:37:19.518 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:19.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:19.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:19.526 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:19.843 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:37:20.316 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:37:20.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:20.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:20.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:20.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:20.793 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:37:20.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:20.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:20.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:20.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:20.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:20.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:20.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:20.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:20.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:20.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:20.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:20.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:20.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:20.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:20.984 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:37:20.984 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:37:21.028 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:37:21.028 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:37:21.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:21.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:21.264 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:37:21.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:21.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:21.523 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:21.528 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:21.737 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:37:22.206 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:37:22.678 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:37:23.149 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:37:23.619 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:37:23.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:23.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:23.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:23.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:23.940 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:37:23.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:23.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:23.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:23.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:23.956 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:37:23.956 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:37:23.956 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:37:23.956 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:37:23.957 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:37:23.957 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:37:23.957 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:37:23.957 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.957 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1605 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1605 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1605 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1605 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1605 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.958 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1605 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.959 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1605 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:23.959 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1605 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:28.954 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:37:28.954 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:37:28.955 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:37:28.956 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:37:28.957 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:37:28.958 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:37:28.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:37:28.968 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:37:28.968 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:37:28.969 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:37:28.969 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:37:28.971 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:37:28.971 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:37:28.971 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:37:28.971 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:37:28.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:37:28.971 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:37:28.971 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:37:28.971 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:37:28.971 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:28.973 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:37:28.973 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:37:28.973 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:37:28.973 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:37:28.973 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:37:28.973 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:37:28.973 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:37:28.973 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:37:28.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:28.974 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:37:28.975 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:37:28.975 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:37:28.975 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:37:28.975 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:37:28.975 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:37:28.975 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:37:28.975 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:37:28.975 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:37:28.977 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:37:28.977 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:37:28.977 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:37:28.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:28.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:37:28.982 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:37:29.458 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:37:29.502 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:37:29.504 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:37:29.506 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:37:29.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:29.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:29.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:29.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:29.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:29.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:29.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:29.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:29.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:29.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:29.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:29.540 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:37:29.540 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:37:29.548 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:29.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:29.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:29.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:29.928 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:37:29.980 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:29.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:29.980 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:29.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:30.397 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:37:30.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:30.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:30.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:30.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:30.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:30.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:30.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:30.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:30.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:30.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:30.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:30.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:30.861 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:30.861 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:30.861 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:37:30.861 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:37:30.862 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:37:30.862 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:37:30.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:30.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:30.868 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:37:30.980 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:30.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:30.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:30.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:31.338 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:37:31.808 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:37:31.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:31.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:31.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:31.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:32.279 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:37:32.750 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:37:32.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:32.982 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:32.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:32.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:32.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:32.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:32.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:32.995 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:32.995 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:37:33.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:33.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:33.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:33.017 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:33.017 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:33.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:33.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:33.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:33.019 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:33.019 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:33.019 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:37:33.019 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:37:33.027 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:33.027 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:33.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:33.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:33.221 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:37:33.692 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:37:33.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:33.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:33.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:33.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:34.163 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:37:34.633 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:37:35.104 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:37:35.575 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:37:36.046 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:37:36.516 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:37:36.987 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:37:37.460 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:37:37.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:37.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:37.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:37.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:37.937 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:37:37.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:37.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:37.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:37.947 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:37.947 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:37.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:37:37.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:37:37.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:37.949 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:37:37.949 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:37:37.949 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:37:37.949 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:37:37.982 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:37:37.982 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:37:37.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:37.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:37:38.407 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:37:38.885 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:37:39.363 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:37:39.841 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:37:40.320 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:37:40.795 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:37:41.264 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:37:41.738 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:37:42.217 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:37:42.693 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:37:43.168 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:37:43.642 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:37:44.111 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:37:44.584 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:37:45.060 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:37:45.535 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:37:46.013 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:37:46.482 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:37:46.953 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:37:47.425 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:37:47.901 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:37:48.373 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:37:48.848 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:37:49.323 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:37:49.801 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:37:50.274 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:37:50.746 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:37:51.223 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:37:51.700 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:37:52.178 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:37:52.656 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:37:53.129 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:37:53.599 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:37:54.070 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:37:54.540 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:37:55.011 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:37:55.482 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 03:37:55.952 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 03:37:56.423 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 03:37:56.894 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 03:37:57.369 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 03:37:57.843 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 03:37:57.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:37:57.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:37:57.944 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:37:57.948 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:37:57.948 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:37:57.948 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:37:57.948 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:37:57.952 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:37:57.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:37:57.952 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:37:57.952 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:37:57.952 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:37:57.952 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:37:57.952 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:37:57.953 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6247 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.953 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6247 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.953 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6247 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.953 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6247 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.953 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6247 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.953 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6247 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.953 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6247 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.953 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6248 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.954 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6248 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.954 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6248 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.954 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6248 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.954 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6248 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.954 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6248 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.954 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6248 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:37:57.954 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6248 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:38:02.951 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:38:02.951 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:38:02.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:38:02.954 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:38:02.957 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:38:02.958 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:38:02.973 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:38:02.974 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:38:02.974 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:38:02.975 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:38:02.975 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:38:02.977 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:38:02.977 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:38:02.977 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:38:02.977 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:38:02.978 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:38:02.978 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:38:02.978 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:38:02.978 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:38:02.978 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:38:02.980 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:38:02.980 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:38:02.980 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:38:02.980 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:38:02.981 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:38:02.981 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:38:02.981 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:38:02.981 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:38:02.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:38:02.984 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:38:02.984 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:38:02.984 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:38:02.984 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:38:02.984 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:38:02.984 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:38:02.984 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:38:02.984 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:38:02.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:38:02.990 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:38:02.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:38:02.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:38:02.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:38:02.991 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:38:02.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:38:02.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:38:02.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:38:02.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:38:02.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:02.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:02.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:02.991 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:38:02.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:02.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:02.991 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:38:02.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:02.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:02.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:02.992 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:38:02.992 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:38:02.992 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:38:02.992 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:38:02.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:02.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:02.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:02.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:38:02.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:02.997 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:38:03.471 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:38:03.529 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:38:03.531 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:38:03.533 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:38:03.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:03.555 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:03.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:03.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:03.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:03.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:03.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:03.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:03.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:03.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:38:03.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:38:03.576 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:38:03.576 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:38:03.608 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:38:03.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:38:03.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:03.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:03.945 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:38:03.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:38:03.997 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:38:04.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:38:04.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:38:04.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:04.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:04.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:04.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:04.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:04.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:04.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:04.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:04.257 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:04.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:04.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:04.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:04.258 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:38:04.258 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:38:04.258 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:38:04.258 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:38:04.266 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:38:04.266 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:38:04.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:04.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:04.415 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:38:04.885 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:38:04.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:38:04.998 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:38:05.000 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:38:05.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:38:05.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:05.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:05.191 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:05.191 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:05.191 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:38:05.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:05.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:05.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:05.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:05.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:05.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:05.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:05.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:05.216 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:38:05.216 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:38:05.216 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:38:05.216 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:38:05.257 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:38:05.257 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:38:05.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:05.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:05.356 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:38:05.831 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:38:05.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:38:05.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:38:06.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:38:06.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:38:06.308 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:38:06.786 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:38:06.999 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:38:07.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:38:07.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:38:07.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:38:07.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:07.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:07.182 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:07.182 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:07.200 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:07.200 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:07.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:07.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:07.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:07.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:07.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:07.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:07.209 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:38:07.209 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:38:07.209 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:38:07.209 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:38:07.257 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:38:07.257 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:38:07.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:07.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:07.259 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:38:07.728 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:38:08.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:38:08.000 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:38:08.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:38:08.008 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:38:08.202 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:38:08.675 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:38:09.150 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:38:09.629 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:38:10.107 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:38:10.581 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:38:11.059 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:38:11.538 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:38:12.015 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:38:12.494 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:38:12.972 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:38:13.450 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:38:13.929 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:38:14.408 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:38:14.886 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:38:15.360 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:38:15.838 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:38:16.316 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:38:16.792 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:38:17.271 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:38:17.745 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:38:18.214 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:38:18.684 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:38:19.157 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:38:19.627 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:38:20.097 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:38:20.567 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:38:21.040 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:38:21.514 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:38:21.990 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:38:22.467 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:38:22.939 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:38:23.415 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:38:23.888 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:38:24.363 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:38:24.841 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:38:25.319 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:38:25.791 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:38:26.269 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:38:26.747 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:38:27.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:27.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:27.204 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:38:27.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:38:27.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:38:27.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:38:27.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:38:27.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:38:27.211 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:38:27.211 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:38:27.211 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:38:27.211 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:38:27.211 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:38:27.211 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:38:27.211 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5202 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:38:27.211 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5202 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:38:27.211 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5202 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:38:27.211 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5202 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:38:27.211 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5202 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:38:27.211 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=5202 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:38:32.211 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:38:32.211 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:38:32.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:38:32.214 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:38:32.216 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:38:32.218 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:38:32.233 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:38:32.233 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:38:32.234 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:38:32.234 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:38:32.234 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:38:32.236 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:38:32.236 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:38:32.236 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:38:32.236 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:38:32.237 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:38:32.237 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:38:32.237 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:38:32.237 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:38:32.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:38:32.239 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:38:32.239 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:38:32.239 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:38:32.239 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:38:32.239 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:38:32.239 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:38:32.240 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:38:32.240 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:38:32.240 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:38:32.241 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:38:32.242 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:38:32.242 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:38:32.242 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:38:32.242 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:38:32.242 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:38:32.242 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:38:32.242 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:38:32.242 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:38:32.245 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:38:32.245 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:38:32.245 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:38:32.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:32.246 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:38:32.247 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:38:32.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:32.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:32.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:38:32.250 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:38:32.719 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:38:32.783 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:38:32.785 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:38:32.786 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:38:32.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:32.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:32.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:32.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:32.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:32.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:32.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:32.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:32.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:32.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:38:32.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:38:32.837 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:38:32.837 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:38:32.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:38:32.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:38:32.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:32.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:33.192 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:38:33.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:38:33.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:38:33.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:38:33.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:38:33.667 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:38:34.141 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:38:34.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:38:34.250 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:38:34.253 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:38:34.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:38:34.615 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:38:35.093 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:38:35.250 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:38:35.251 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:38:35.254 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:38:35.258 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:38:35.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:35.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:35.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:35.297 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:35.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:35.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:35.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:35.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:35.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:35.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:35.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:35.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:35.325 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:38:35.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:38:35.325 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:38:35.325 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:38:35.374 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:38:35.374 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:38:35.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:35.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:35.564 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:38:36.035 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:38:36.251 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:38:36.251 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:38:36.254 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:38:36.258 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:38:36.506 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:38:36.977 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:38:37.252 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:38:37.252 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:38:37.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:38:37.258 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:38:37.448 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:38:37.918 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:38:38.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:38.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:38.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:38.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:38.059 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:38:38.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:38.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:38.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:38.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:38.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:38.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:38.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:38.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:38.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:38:38.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:38:38.087 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:38:38.087 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:38:38.099 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:38:38.099 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:38:38.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:38.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:38.390 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:38:38.863 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:38:39.341 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:38:39.817 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:38:40.290 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:38:40.768 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:38:41.243 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:38:41.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:41.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:41.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:41.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:41.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:41.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:41.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:41.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:38:41.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:38:41.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:38:41.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:38:41.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:41.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:38:41.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:38:41.425 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:38:41.425 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:38:41.475 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:38:41.475 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:38:41.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:41.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:38:41.712 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:38:42.181 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:38:42.654 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:38:43.123 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:38:43.593 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:38:44.064 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:38:44.536 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:38:45.011 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:38:45.490 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:38:45.962 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:38:46.441 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:38:46.919 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:38:47.395 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:38:47.872 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:38:48.344 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:38:48.822 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:38:49.297 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:38:49.773 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:38:50.246 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:38:50.719 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:38:51.188 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:38:51.665 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:38:52.143 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:38:52.621 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:38:53.098 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:38:53.569 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:38:54.045 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:38:54.518 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:38:54.987 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:38:55.458 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:38:55.929 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:38:56.399 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:38:56.870 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:38:57.341 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:38:57.812 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:38:58.282 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:38:58.758 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 03:38:59.229 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 03:38:59.698 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 03:39:00.167 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 03:39:00.637 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 03:39:01.108 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 03:39:01.420 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:01.420 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:01.420 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:39:01.425 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:39:01.425 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:39:01.425 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:39:01.425 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:39:01.425 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:39:01.425 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:39:01.425 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:39:01.425 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:39:01.425 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:39:01.425 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:39:01.425 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:39:01.425 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6293 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:39:01.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6293 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:39:01.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6293 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:39:01.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6293 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:39:01.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6293 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:39:01.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6293 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:39:01.426 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=6293 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:39:06.428 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:39:06.428 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:39:06.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:39:06.434 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:39:06.435 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:39:06.435 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:39:06.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:39:06.443 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:39:06.443 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:39:06.443 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:39:06.443 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:39:06.446 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:39:06.446 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:39:06.447 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:39:06.447 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:39:06.447 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:39:06.447 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:39:06.448 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:39:06.448 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:39:06.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:39:06.449 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:39:06.449 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:39:06.449 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:39:06.449 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:39:06.449 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:39:06.449 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:39:06.449 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:39:06.449 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:39:06.450 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:39:06.451 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:39:06.451 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:39:06.451 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:39:06.451 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:39:06.451 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:39:06.452 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:39:06.452 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:39:06.452 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:39:06.452 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:39:06.454 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:39:06.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:39:06.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:39:06.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:39:06.454 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:39:06.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:39:06.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:39:06.455 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:39:06.455 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:39:06.455 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:06.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:06.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:06.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:06.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:06.456 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:06.456 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:06.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:06.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:06.456 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:06.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:06.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:06.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:06.460 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:39:06.942 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:39:06.977 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:39:06.980 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:39:06.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:39:06.983 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:39:07.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:07.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:07.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:39:07.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:07.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:07.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:39:07.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:39:07.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:07.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:39:07.043 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:39:07.043 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:39:07.043 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:39:07.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:39:07.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:39:07.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:07.082 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:07.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:07.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:39:07.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:07.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:07.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:07.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:07.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:39:07.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:07.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:07.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:39:07.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:39:07.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:07.329 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:39:07.329 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:39:07.329 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:39:07.329 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:39:07.362 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:39:07.362 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:39:07.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:07.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:07.418 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:39:07.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:39:07.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:39:07.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:39:07.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:39:07.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:07.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:39:07.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:07.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:07.703 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:39:07.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:07.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:07.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:39:07.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:07.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:07.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:39:07.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:39:07.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:07.729 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:39:07.729 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:39:07.729 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:39:07.729 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:39:07.738 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:39:07.738 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:39:07.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:07.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:07.887 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:39:08.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:08.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:39:08.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:08.274 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:08.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:08.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:08.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:39:08.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:08.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:08.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:39:08.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:39:08.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:08.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:39:08.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:39:08.288 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:39:08.288 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:39:08.300 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:39:08.300 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:39:08.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:08.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:08.360 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:39:08.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:39:08.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:39:08.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:39:08.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:39:08.831 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:39:08.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:39:08.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:08.918 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:08.918 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:08.918 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:39:08.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:39:08.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:39:08.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:39:08.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:39:08.929 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:39:08.929 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:39:08.929 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:39:08.929 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:39:08.929 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:39:08.929 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:39:08.929 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:39:13.931 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:39:13.931 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:39:13.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:39:13.934 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:39:13.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:39:13.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:39:13.948 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:39:13.948 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:39:13.948 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:39:13.949 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:39:13.949 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:39:13.951 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:39:13.951 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:39:13.951 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:39:13.951 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:39:13.951 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:39:13.951 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:39:13.951 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:39:13.951 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:39:13.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:39:13.953 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:39:13.953 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:39:13.953 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:39:13.953 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:39:13.953 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:39:13.953 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:39:13.953 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:39:13.953 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:39:13.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:39:13.955 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:39:13.955 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:39:13.955 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:39:13.955 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:39:13.955 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:39:13.955 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:39:13.955 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:39:13.955 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:39:13.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:39:13.957 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:39:13.957 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:39:13.957 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:13.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:13.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:13.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:13.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:13.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:13.958 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:39:13.958 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:39:13.958 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:39:13.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:13.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:13.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:13.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:13.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:39:13.962 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:39:14.434 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:39:14.478 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:39:14.478 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:39:14.479 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:39:14.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:39:14.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:14.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:14.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:39:14.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:14.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:14.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:39:14.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:39:14.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:14.530 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:39:14.530 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:39:14.531 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:39:14.531 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:39:14.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:39:14.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:39:14.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:14.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:14.906 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:39:14.959 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:39:14.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:39:14.960 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:39:14.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:39:15.382 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:39:15.855 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:39:15.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:39:15.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:39:15.960 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:39:15.963 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:39:16.330 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:39:16.802 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:39:16.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:39:16.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:39:16.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:39:16.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:39:17.273 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:39:17.749 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:39:17.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:39:17.962 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:39:17.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:39:17.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:39:18.221 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:39:18.693 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:39:18.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:39:18.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:39:18.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:39:18.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:39:19.165 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:39:19.643 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:39:20.121 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:39:20.598 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:39:21.076 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:39:21.554 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:39:22.032 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:39:22.509 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:39:22.986 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:39:23.464 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:39:23.941 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:39:24.418 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:39:24.896 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:39:25.368 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:39:25.839 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:39:26.310 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:39:26.780 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:39:27.251 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:39:27.722 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:39:28.193 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:39:28.663 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:39:29.134 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:39:29.605 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:39:30.076 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:39:30.546 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:39:31.017 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:39:31.488 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:39:31.959 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:39:32.430 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:39:32.900 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:39:33.371 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:39:33.847 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:39:34.325 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:39:34.802 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:39:35.280 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:39:35.758 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:39:36.236 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:39:36.715 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:39:37.189 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:39:37.667 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:39:38.145 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:39:38.619 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:39:39.096 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:39:39.568 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:39:40.046 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:39:40.519 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 03:39:40.990 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 03:39:41.461 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 03:39:41.935 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 03:39:42.407 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 03:39:42.879 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 03:39:43.351 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 03:39:43.824 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 03:39:44.297 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 03:39:44.768 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 03:39:45.238 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 03:39:45.709 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 03:39:46.184 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 03:39:46.656 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 03:39:47.127 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 03:39:47.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:39:47.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:47.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:47.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:47.582 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:47.582 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:47.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:39:47.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:39:47.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:39:47.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:39:47.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:39:47.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:47.590 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:39:47.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:39:47.590 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:39:47.590 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:39:47.593 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:39:47.593 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:39:47.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:47.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:39:47.598 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 03:39:48.068 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 03:39:48.539 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 03:39:49.011 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 03:39:49.482 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 03:39:49.952 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 03:39:50.423 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 03:39:50.893 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 03:39:51.365 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 03:39:51.835 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 03:39:52.312 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 03:39:52.790 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 03:39:53.268 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 03:39:53.746 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 03:39:54.224 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 03:39:54.703 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 03:39:55.180 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 03:39:55.649 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 03:39:56.119 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 03:39:56.588 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 03:39:57.062 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 03:39:57.537 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 03:39:58.015 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 03:39:58.490 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 03:39:58.960 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 03:39:59.436 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 03:39:59.907 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 03:40:00.381 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 03:40:00.850 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 03:40:01.319 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 03:40:01.789 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 03:40:02.261 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-05 03:40:02.736 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-05 03:40:03.205 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-05 03:40:03.674 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-05 03:40:04.144 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-05 03:40:04.615 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-05 03:40:05.089 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-05 03:40:05.561 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-05 03:40:06.030 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-05 03:40:06.500 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-05 03:40:06.970 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-05 03:40:07.439 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-05 03:40:07.908 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-05 03:40:08.377 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-05 03:40:08.853 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-05 03:40:09.331 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-05 03:40:09.810 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-05 03:40:10.288 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-05 03:40:10.765 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-05 03:40:11.242 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-05 03:40:11.722 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-05 03:40:12.199 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-05 03:40:12.668 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-05 03:40:13.141 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-05 03:40:13.613 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-05 03:40:14.082 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-05 03:40:14.558 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-05 03:40:15.030 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-05 03:40:15.501 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-05 03:40:15.976 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-05 03:40:16.454 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-05 03:40:16.932 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-05 03:40:17.410 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-05 03:40:17.888 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-05 03:40:18.367 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-05 03:40:18.845 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-05 03:40:19.323 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-05 03:40:19.793 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-05 03:40:20.272 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-05 03:40:20.744 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-05 03:40:21.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:40:21.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:40:21.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:40:21.127 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:40:21.127 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:40:21.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:40:21.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:40:21.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:40:21.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:40:21.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:40:21.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:40:21.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:40:21.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:40:21.146 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:40:21.146 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:40:21.146 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:40:21.146 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:40:21.160 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:40:21.160 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:40:21.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:40:21.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:40:21.215 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-05 03:40:21.691 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-05 03:40:22.168 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-05 03:40:22.645 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-05 03:40:23.123 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-05 03:40:23.599 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-05 03:40:24.075 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-05 03:40:24.553 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-05 03:40:25.031 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-05 03:40:25.509 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-05 03:40:25.986 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-05 03:40:26.464 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-05 03:40:26.941 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-05 03:40:27.416 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-05 03:40:27.893 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-05 03:40:28.371 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-05 03:40:28.848 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-05 03:40:29.325 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-05 03:40:29.803 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-05 03:40:30.281 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-05 03:40:30.759 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-05 03:40:31.237 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-05 03:40:31.715 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-05 03:40:32.193 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-05 03:40:32.671 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-05 03:40:33.148 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-05 03:40:33.626 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-05 03:40:34.103 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-05 03:40:34.580 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-05 03:40:35.058 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-05 03:40:35.537 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-05 03:40:36.014 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-05 03:40:36.491 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-05 03:40:36.969 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-05 03:40:37.446 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-05 03:40:37.924 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-05 03:40:38.401 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-05 03:40:38.875 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-05 03:40:39.349 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-05 03:40:39.820 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-05 03:40:40.298 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-05 03:40:40.776 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-05 03:40:41.254 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-05 03:40:41.732 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-05 03:40:42.210 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-05 03:40:42.687 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-05 03:40:43.164 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-05 03:40:43.641 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-05 03:40:44.119 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-05 03:40:44.597 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-05 03:40:45.072 [DEBUG] clck_gen.py:113 IND CLOCK 19584
2026-03-05 03:40:45.548 [DEBUG] clck_gen.py:113 IND CLOCK 19686
2026-03-05 03:40:46.026 [DEBUG] clck_gen.py:113 IND CLOCK 19788
2026-03-05 03:40:46.503 [DEBUG] clck_gen.py:113 IND CLOCK 19890
2026-03-05 03:40:46.981 [DEBUG] clck_gen.py:113 IND CLOCK 19992
2026-03-05 03:40:47.455 [DEBUG] clck_gen.py:113 IND CLOCK 20094
2026-03-05 03:40:47.929 [DEBUG] clck_gen.py:113 IND CLOCK 20196
2026-03-05 03:40:48.405 [DEBUG] clck_gen.py:113 IND CLOCK 20298
2026-03-05 03:40:48.882 [DEBUG] clck_gen.py:113 IND CLOCK 20400
2026-03-05 03:40:49.361 [DEBUG] clck_gen.py:113 IND CLOCK 20502
2026-03-05 03:40:49.838 [DEBUG] clck_gen.py:113 IND CLOCK 20604
2026-03-05 03:40:50.315 [DEBUG] clck_gen.py:113 IND CLOCK 20706
2026-03-05 03:40:50.792 [DEBUG] clck_gen.py:113 IND CLOCK 20808
2026-03-05 03:40:51.270 [DEBUG] clck_gen.py:113 IND CLOCK 20910
2026-03-05 03:40:51.747 [DEBUG] clck_gen.py:113 IND CLOCK 21012
2026-03-05 03:40:52.225 [DEBUG] clck_gen.py:113 IND CLOCK 21114
2026-03-05 03:40:52.702 [DEBUG] clck_gen.py:113 IND CLOCK 21216
2026-03-05 03:40:53.180 [DEBUG] clck_gen.py:113 IND CLOCK 21318
2026-03-05 03:40:53.657 [DEBUG] clck_gen.py:113 IND CLOCK 21420
2026-03-05 03:40:54.132 [DEBUG] clck_gen.py:113 IND CLOCK 21522
2026-03-05 03:40:54.609 [DEBUG] clck_gen.py:113 IND CLOCK 21624
2026-03-05 03:40:55.087 [DEBUG] clck_gen.py:113 IND CLOCK 21726
2026-03-05 03:40:55.564 [DEBUG] clck_gen.py:113 IND CLOCK 21828
2026-03-05 03:40:56.042 [DEBUG] clck_gen.py:113 IND CLOCK 21930
2026-03-05 03:40:56.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:40:56.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:40:56.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:40:56.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:40:56.482 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:40:56.482 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:40:56.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:40:56.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:40:56.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:40:56.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:40:56.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:40:56.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:40:56.490 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:40:56.490 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:40:56.490 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:40:56.490 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:40:56.511 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:40:56.511 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:40:56.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:40:56.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:40:56.519 [DEBUG] clck_gen.py:113 IND CLOCK 22032
2026-03-05 03:40:56.997 [DEBUG] clck_gen.py:113 IND CLOCK 22134
2026-03-05 03:40:57.474 [DEBUG] clck_gen.py:113 IND CLOCK 22236
2026-03-05 03:40:57.953 [DEBUG] clck_gen.py:113 IND CLOCK 22338
2026-03-05 03:40:58.431 [DEBUG] clck_gen.py:113 IND CLOCK 22440
2026-03-05 03:40:58.910 [DEBUG] clck_gen.py:113 IND CLOCK 22542
2026-03-05 03:40:59.388 [DEBUG] clck_gen.py:113 IND CLOCK 22644
2026-03-05 03:40:59.866 [DEBUG] clck_gen.py:113 IND CLOCK 22746
2026-03-05 03:41:00.343 [DEBUG] clck_gen.py:113 IND CLOCK 22848
2026-03-05 03:41:00.818 [DEBUG] clck_gen.py:113 IND CLOCK 22950
2026-03-05 03:41:01.289 [DEBUG] clck_gen.py:113 IND CLOCK 23052
2026-03-05 03:41:01.762 [DEBUG] clck_gen.py:113 IND CLOCK 23154
2026-03-05 03:41:02.234 [DEBUG] clck_gen.py:113 IND CLOCK 23256
2026-03-05 03:41:02.703 [DEBUG] clck_gen.py:113 IND CLOCK 23358
2026-03-05 03:41:03.174 [DEBUG] clck_gen.py:113 IND CLOCK 23460
2026-03-05 03:41:03.645 [DEBUG] clck_gen.py:113 IND CLOCK 23562
2026-03-05 03:41:04.116 [DEBUG] clck_gen.py:113 IND CLOCK 23664
2026-03-05 03:41:04.586 [DEBUG] clck_gen.py:113 IND CLOCK 23766
2026-03-05 03:41:05.057 [DEBUG] clck_gen.py:113 IND CLOCK 23868
2026-03-05 03:41:05.528 [DEBUG] clck_gen.py:113 IND CLOCK 23970
2026-03-05 03:41:05.999 [DEBUG] clck_gen.py:113 IND CLOCK 24072
2026-03-05 03:41:06.470 [DEBUG] clck_gen.py:113 IND CLOCK 24174
2026-03-05 03:41:06.940 [DEBUG] clck_gen.py:113 IND CLOCK 24276
2026-03-05 03:41:07.411 [DEBUG] clck_gen.py:113 IND CLOCK 24378
2026-03-05 03:41:07.881 [DEBUG] clck_gen.py:113 IND CLOCK 24480
2026-03-05 03:41:08.352 [DEBUG] clck_gen.py:113 IND CLOCK 24582
2026-03-05 03:41:08.824 [DEBUG] clck_gen.py:113 IND CLOCK 24684
2026-03-05 03:41:09.296 [DEBUG] clck_gen.py:113 IND CLOCK 24786
2026-03-05 03:41:09.765 [DEBUG] clck_gen.py:113 IND CLOCK 24888
2026-03-05 03:41:10.235 [DEBUG] clck_gen.py:113 IND CLOCK 24990
2026-03-05 03:41:10.706 [DEBUG] clck_gen.py:113 IND CLOCK 25092
2026-03-05 03:41:11.177 [DEBUG] clck_gen.py:113 IND CLOCK 25194
2026-03-05 03:41:11.651 [DEBUG] clck_gen.py:113 IND CLOCK 25296
2026-03-05 03:41:12.129 [DEBUG] clck_gen.py:113 IND CLOCK 25398
2026-03-05 03:41:12.601 [DEBUG] clck_gen.py:113 IND CLOCK 25500
2026-03-05 03:41:13.078 [DEBUG] clck_gen.py:113 IND CLOCK 25602
2026-03-05 03:41:13.555 [DEBUG] clck_gen.py:113 IND CLOCK 25704
2026-03-05 03:41:14.032 [DEBUG] clck_gen.py:113 IND CLOCK 25806
2026-03-05 03:41:14.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:14.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:14.319 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:41:14.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:14.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:14.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:14.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:14.326 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:41:14.326 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:41:14.326 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:41:14.326 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:41:14.326 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:41:14.326 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:41:14.326 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:41:14.326 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=25871 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:41:14.326 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=25871 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:41:14.326 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=25871 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:41:14.326 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=25871 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:41:14.326 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=25871 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:41:14.326 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=25871 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:41:14.326 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=25871 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:41:19.327 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:41:19.327 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:41:19.329 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:41:19.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:41:19.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:41:19.330 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:41:19.333 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:41:19.334 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:41:19.334 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:41:19.334 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:41:19.334 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:41:19.337 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:41:19.337 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:41:19.338 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:41:19.338 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:41:19.338 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:41:19.338 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:41:19.338 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:41:19.338 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:41:19.338 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:19.339 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:41:19.339 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:41:19.339 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:41:19.339 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:41:19.340 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:41:19.340 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:41:19.340 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:41:19.340 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:41:19.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:19.341 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:41:19.341 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:41:19.341 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:41:19.341 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:41:19.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:41:19.341 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:41:19.341 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:41:19.341 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:41:19.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:19.343 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:41:19.344 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:41:19.344 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:41:19.344 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:41:19.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:19.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:19.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:19.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:41:19.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:19.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:19.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:19.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:41:19.345 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:41:19.345 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:41:19.345 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:41:24.347 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:41:24.348 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:41:24.349 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:41:24.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:41:24.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:41:24.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:41:24.371 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:41:24.372 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:41:24.372 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:41:24.373 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:41:24.373 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:41:24.377 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:41:24.377 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:41:24.377 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:41:24.377 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:41:24.377 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:41:24.377 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:41:24.378 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:41:24.378 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:41:24.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:24.380 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:41:24.380 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:41:24.381 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:41:24.381 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:41:24.381 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:41:24.381 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:41:24.381 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:41:24.381 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:41:24.381 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:24.383 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:41:24.383 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:41:24.383 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:41:24.383 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:41:24.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:41:24.383 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:41:24.384 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:41:24.384 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:41:24.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:24.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:24.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:24.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:24.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:24.388 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:41:24.388 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:41:24.388 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:41:24.388 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:41:24.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:24.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:24.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:24.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:41:24.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:24.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:24.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:24.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:24.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:24.393 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:41:24.868 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:41:24.926 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:41:24.928 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:41:24.930 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:41:24.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:41:24.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:24.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:24.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:41:24.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:24.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:24.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:41:24.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:41:24.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:24.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:41:24.979 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:41:24.979 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:41:24.979 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:41:25.005 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:41:25.005 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:41:25.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:25.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:25.341 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:41:25.392 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:25.392 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:25.394 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:25.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:25.815 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:41:26.293 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:41:26.393 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:26.393 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:26.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:26.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:26.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:26.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:41:26.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:26.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:26.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:26.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:26.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:41:26.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:26.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:26.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:41:26.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:41:26.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:26.490 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:41:26.490 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:41:26.490 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:41:26.490 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:41:26.530 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:41:26.530 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:41:26.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:26.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:26.765 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:41:27.236 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:41:27.393 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:27.393 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:27.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:27.400 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:27.706 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:41:28.178 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:41:28.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:28.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:28.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:28.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:28.653 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:41:28.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:28.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:41:28.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:28.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:28.809 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:41:28.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:28.828 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:28.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:41:28.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:28.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:28.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:41:28.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:41:28.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:28.836 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:41:28.836 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:41:28.836 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:41:28.836 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:41:28.887 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:41:28.887 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:41:28.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:28.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:29.125 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:41:29.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:29.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:29.397 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:29.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:29.601 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:41:30.079 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:41:30.557 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:41:31.034 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:41:31.512 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:41:31.989 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:41:32.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:32.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:41:32.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:32.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:32.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:32.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:32.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:41:32.410 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:32.410 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:32.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:41:32.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:41:32.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:32.412 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:41:32.412 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:41:32.412 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:41:32.412 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:41:32.460 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:41:32.460 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:41:32.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:32.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:32.466 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:41:32.935 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:41:33.408 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:41:33.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:33.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:33.493 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:41:33.497 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:33.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:33.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:33.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:33.498 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:41:33.498 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:41:33.498 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:41:33.498 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:41:33.498 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:41:33.498 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:41:33.498 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:41:38.498 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:41:38.498 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:41:38.500 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:41:38.501 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:41:38.505 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:41:38.506 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:41:38.513 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:41:38.513 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:41:38.513 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:41:38.513 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:41:38.513 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:41:38.514 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:41:38.514 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:41:38.514 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:41:38.515 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:41:38.515 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:41:38.515 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:41:38.515 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:41:38.515 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:41:38.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:38.518 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:41:38.518 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:41:38.518 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:41:38.518 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:41:38.518 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:41:38.518 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:41:38.518 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:41:38.518 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:41:38.519 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:38.521 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:41:38.521 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:41:38.521 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:41:38.521 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:41:38.521 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:41:38.521 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:41:38.521 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:41:38.521 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:41:38.521 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:38.524 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:41:38.524 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:38.525 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:41:38.525 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:41:38.525 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:41:38.526 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:41:38.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:38.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:38.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:38.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:41:38.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:38.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:38.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:38.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:38.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:38.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:38.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:38.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:38.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:38.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:38.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:38.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:38.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:41:38.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:41:38.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:41:38.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:38.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:38.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:38.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:38.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:41:38.530 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:41:39.003 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:41:39.066 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:41:39.068 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:41:39.070 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:41:39.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:41:39.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:39.087 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:39.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:41:39.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:39.102 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:39.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:41:39.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:41:39.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:39.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:41:39.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:41:39.105 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:41:39.105 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:41:39.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:41:39.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:41:39.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:39.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:39.480 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:41:39.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:39.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:39.531 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:39.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:39.956 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:41:40.428 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:41:40.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:40.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:40.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:40.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:40.902 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:41:41.377 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:41:41.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:41.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:41.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:41.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:41.854 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:41:42.332 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:41:42.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:42.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:42.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:42.537 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:42.808 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:41:43.282 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:41:43.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:41:43.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:41:43.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:41:43.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:41:43.760 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:41:44.238 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:41:44.716 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:41:45.194 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:41:45.672 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:41:46.150 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:41:46.626 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:41:47.104 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:41:47.582 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:41:48.059 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:41:48.536 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:41:49.011 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:41:49.484 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:41:49.953 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:41:50.430 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:41:50.903 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:41:51.378 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:41:51.856 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:41:52.334 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:41:52.811 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:41:53.289 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:41:53.765 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:41:54.243 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:41:54.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:54.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:41:54.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:54.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:54.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:54.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:54.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:41:54.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:41:54.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:41:54.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:41:54.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:41:54.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:54.569 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:41:54.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:41:54.569 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:41:54.569 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:41:54.616 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:41:54.616 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:41:54.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:54.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:41:54.718 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:41:55.187 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:41:55.665 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:41:56.137 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:41:56.608 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:41:57.078 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:41:57.549 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:41:58.020 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:41:58.491 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:41:58.962 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:41:59.432 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:41:59.903 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:42:00.377 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:42:00.855 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:42:01.333 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:42:01.812 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:42:02.291 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:42:02.768 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:42:03.247 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:42:03.720 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:42:04.190 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:42:04.661 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:42:05.139 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 03:42:05.618 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 03:42:06.095 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 03:42:06.573 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 03:42:07.051 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 03:42:07.521 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 03:42:07.990 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 03:42:08.458 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 03:42:08.928 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 03:42:09.400 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 03:42:09.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:09.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:42:09.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:09.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:09.751 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:42:09.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:09.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:09.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:42:09.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:09.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:09.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:42:09.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:42:09.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:09.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:42:09.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:42:09.778 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:42:09.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:42:09.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:42:09.816 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:42:09.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:09.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:09.874 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 03:42:10.348 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 03:42:10.822 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 03:42:11.300 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 03:42:11.773 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 03:42:12.243 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 03:42:12.714 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 03:42:13.186 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 03:42:13.664 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 03:42:14.142 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 03:42:14.619 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 03:42:15.096 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 03:42:15.573 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 03:42:16.050 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 03:42:16.528 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 03:42:17.005 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 03:42:17.483 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 03:42:17.961 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 03:42:18.433 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 03:42:18.911 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-05 03:42:19.388 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-05 03:42:19.862 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-05 03:42:20.341 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-05 03:42:20.818 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-05 03:42:21.290 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-05 03:42:21.763 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-05 03:42:22.241 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-05 03:42:22.719 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-05 03:42:23.193 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-05 03:42:23.670 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-05 03:42:24.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:24.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:42:24.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:24.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:24.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:24.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:24.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:42:24.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:24.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:24.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:42:24.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:42:24.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:24.138 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:42:24.138 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:42:24.138 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:42:24.138 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:42:24.144 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-05 03:42:24.186 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:42:24.187 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:42:24.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:24.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:24.615 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-05 03:42:25.092 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-05 03:42:25.568 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-05 03:42:26.042 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-05 03:42:26.511 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-05 03:42:26.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:26.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:26.903 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:42:26.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:42:26.906 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:42:26.906 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:42:26.906 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:42:26.906 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:42:26.906 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:42:26.906 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:42:26.906 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:42:26.907 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:42:26.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:42:26.907 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:42:26.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=10390 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:42:26.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=10390 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:42:26.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=10390 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:42:26.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=10390 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:42:26.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=10390 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:42:26.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=10390 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:42:26.907 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=10390 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:42:31.908 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:42:31.908 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:42:31.909 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:42:31.910 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:42:31.910 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:42:31.910 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:42:31.920 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:42:31.920 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:42:31.920 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:42:31.921 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:42:31.921 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:42:31.922 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:42:31.922 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:42:31.922 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:42:31.922 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:42:31.922 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:42:31.923 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:42:31.923 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:42:31.923 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:42:31.923 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:42:31.924 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:42:31.924 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:42:31.924 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:42:31.924 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:42:31.924 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:42:31.924 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:42:31.924 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:42:31.924 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:42:31.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:42:31.926 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:42:31.926 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:42:31.926 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:42:31.926 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:42:31.926 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:42:31.926 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:42:31.926 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:42:31.926 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:42:31.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:42:31.928 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:42:31.928 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:42:31.928 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:42:31.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:42:31.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:42:31.933 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:42:32.402 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:42:32.464 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:42:32.467 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:42:32.469 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:42:32.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:42:32.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:32.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:32.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:42:32.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:32.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:32.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:42:32.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:42:32.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:32.522 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:42:32.523 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:42:32.523 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:42:32.523 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:42:32.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:42:32.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:42:32.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:32.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:32.872 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:42:32.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:42:32.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:42:32.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:42:32.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:42:33.342 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:42:33.818 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:42:33.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:42:33.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:42:33.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:42:33.933 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:42:34.296 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:42:34.774 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:42:34.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:42:34.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:42:34.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:42:34.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:42:35.252 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:42:35.729 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:42:35.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:42:35.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:42:35.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:42:35.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:42:36.202 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:42:36.678 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:42:36.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:42:36.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:42:36.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:42:36.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:42:37.156 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:42:37.633 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:42:38.112 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:42:38.585 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:42:39.062 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:42:39.535 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:42:40.009 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:42:40.483 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:42:40.957 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:42:41.434 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:42:41.911 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:42:42.384 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:42:42.862 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:42:43.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:43.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:42:43.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:43.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:43.089 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:43.089 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:43.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:42:43.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:43.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:43.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:42:43.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:42:43.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:43.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:42:43.097 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:42:43.097 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:42:43.097 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:42:43.143 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:42:43.143 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:42:43.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:43.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:43.335 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:42:43.805 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:42:44.277 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:42:44.747 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:42:45.217 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:42:45.687 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:42:46.158 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:42:46.629 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:42:47.103 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:42:47.582 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:42:48.059 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:42:48.536 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:42:49.014 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:42:49.492 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:42:49.971 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:42:50.449 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:42:50.927 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:42:51.405 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:42:51.875 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:42:52.344 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:42:52.814 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:42:53.286 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:42:53.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:53.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:42:53.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:53.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:53.455 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:42:53.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:53.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:53.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:42:53.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:42:53.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:42:53.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:42:53.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:42:53.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:53.480 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:42:53.480 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:42:53.480 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:42:53.480 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:42:53.518 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:42:53.518 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:42:53.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:53.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:42:53.760 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:42:54.232 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:42:54.704 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:42:55.178 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-05 03:42:55.650 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-05 03:42:56.121 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-05 03:42:56.591 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-05 03:42:57.062 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-05 03:42:57.533 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-05 03:42:58.009 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-05 03:42:58.481 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-05 03:42:58.952 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-05 03:42:59.426 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-05 03:42:59.899 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-05 03:43:00.371 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-05 03:43:00.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:00.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:00.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:00.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:00.428 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:00.428 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:00.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:00.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:00.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:00.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:00.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:00.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:00.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:00.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:00.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:43:00.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:43:00.460 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:43:00.460 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:43:00.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:00.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:00.841 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-05 03:43:01.314 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-05 03:43:01.784 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-05 03:43:02.255 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-05 03:43:02.724 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-05 03:43:03.195 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-05 03:43:03.666 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-05 03:43:04.137 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-05 03:43:04.607 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-05 03:43:05.080 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-05 03:43:05.551 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-05 03:43:06.020 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-05 03:43:06.490 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-05 03:43:06.961 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-05 03:43:07.432 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-05 03:43:07.903 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-05 03:43:08.373 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-05 03:43:08.844 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-05 03:43:09.315 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-05 03:43:09.786 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-05 03:43:10.257 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-05 03:43:10.734 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-05 03:43:11.206 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-05 03:43:11.677 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-05 03:43:11.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:11.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:11.769 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:11.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:11.769 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:43:11.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:11.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:11.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:11.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:11.787 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:43:11.787 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:43:11.787 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:43:11.788 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:43:11.788 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:43:11.788 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:43:11.788 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:43:11.788 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=8594 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:11.788 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=8594 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:11.789 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=8594 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:11.789 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=8594 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:11.789 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=8594 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:11.789 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=8594 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:16.785 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:43:16.786 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:43:16.787 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:43:16.788 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:43:16.789 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:43:16.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:43:16.792 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:43:16.793 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:43:16.793 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:43:16.794 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:43:16.794 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:43:16.796 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:43:16.796 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:43:16.797 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:43:16.797 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:43:16.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:43:16.797 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:43:16.797 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:43:16.797 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:43:16.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:16.800 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:43:16.800 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:43:16.800 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:43:16.800 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:43:16.800 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:43:16.800 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:43:16.801 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:43:16.801 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:43:16.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:16.803 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:43:16.803 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:43:16.803 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:43:16.803 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:43:16.803 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:43:16.803 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:43:16.803 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:43:16.803 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:43:16.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:16.806 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:43:16.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:43:16.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:43:16.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:43:16.806 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:43:16.807 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:43:16.807 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:43:16.807 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:43:16.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:16.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:16.812 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:43:17.286 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:43:17.341 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:43:17.344 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:43:17.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:17.345 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:43:17.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:17.364 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:17.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:17.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:17.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:17.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:17.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:17.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:17.389 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:17.390 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:17.390 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:43:17.390 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:43:17.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:17.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:17.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:17.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:17.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:17.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:17.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:17.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:17.761 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:43:17.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:17.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:17.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:17.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:17.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:17.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:17.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:17.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:17.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:17.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:17.774 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:43:17.774 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:43:17.802 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:43:17.802 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:43:17.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:17.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:17.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:17.811 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:17.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:17.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:18.231 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:43:18.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:18.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:18.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:18.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:18.287 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:43:18.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:18.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:18.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:18.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:18.312 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:18.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:18.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:18.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:18.314 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:18.314 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:18.314 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:43:18.314 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:43:18.316 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:18.316 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:18.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:18.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:18.701 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:43:18.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:18.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:18.814 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:18.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:19.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:19.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:19.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:19.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:19.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:19.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:19.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:19.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:19.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:19.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:19.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:19.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:19.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:19.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:19.121 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:43:19.121 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:43:19.169 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:43:19.169 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:43:19.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:19.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:19.172 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:43:19.641 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:43:19.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:19.814 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:19.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:19.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:20.112 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:43:20.583 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:43:20.814 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:20.814 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:20.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:20.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:21.053 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:43:21.524 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:43:21.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:21.816 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:21.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:21.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:21.995 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:43:22.466 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:43:22.937 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:43:23.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:23.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:23.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:23.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:23.198 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:43:23.209 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:23.210 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:23.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:23.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:23.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:43:23.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:43:23.213 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:43:23.213 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:43:23.213 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:43:23.213 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:43:23.213 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:43:23.213 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1387 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.213 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1387 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.213 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1387 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.213 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1387 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.213 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1387 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.214 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1387 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.214 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1387 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.214 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1388 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.214 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1388 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.214 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1388 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.214 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1388 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.214 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1388 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.214 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1388 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.214 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1388 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:23.214 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=1388 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:28.214 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:43:28.214 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:43:28.217 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:43:28.218 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:43:28.218 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:43:28.218 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:43:28.228 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:43:28.229 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:43:28.229 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:43:28.229 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:43:28.229 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:43:28.231 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:43:28.231 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:43:28.231 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:43:28.231 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:43:28.232 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:43:28.232 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:43:28.232 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:43:28.232 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:43:28.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:28.233 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:43:28.233 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:43:28.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:43:28.233 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:43:28.233 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:43:28.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:43:28.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:43:28.233 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:43:28.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:28.235 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:43:28.235 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:43:28.235 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:43:28.235 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:43:28.235 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:43:28.235 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:43:28.235 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:43:28.235 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:43:28.235 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:43:28.237 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:43:28.237 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:43:28.237 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:28.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:28.242 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:43:28.721 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:43:28.759 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:43:28.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:28.762 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:43:28.763 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:43:28.778 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:28.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:28.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:28.800 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:28.800 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:28.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:28.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:28.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:28.807 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:28.807 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:28.808 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:43:28.808 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:43:28.812 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:28.813 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:28.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:28.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:29.199 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:43:29.240 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:29.240 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:29.240 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:29.242 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:29.672 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:43:30.145 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:43:30.241 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:30.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:30.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:30.242 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:30.623 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:43:31.100 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:43:31.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:31.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:31.242 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:31.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:31.578 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:43:32.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:32.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:32.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:32.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:32.050 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:43:32.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:32.053 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:32.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:32.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:32.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:32.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:32.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:32.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:32.061 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:32.061 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:32.061 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:43:32.061 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:43:32.095 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:43:32.095 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:43:32.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:32.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:32.242 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:32.242 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:32.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:32.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:32.521 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:43:32.991 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:43:33.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:33.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:33.243 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:33.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:33.462 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:43:33.933 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:43:34.404 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:43:34.874 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:43:35.345 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:43:35.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:35.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:35.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:35.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:35.436 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:43:35.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:35.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:35.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:35.461 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:35.461 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:35.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:35.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:35.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:35.463 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:35.463 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:35.463 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:43:35.463 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:43:35.480 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:35.481 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:35.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:35.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:35.816 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:43:36.287 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:43:36.758 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:43:37.228 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:43:37.699 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:43:38.170 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:43:38.641 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:43:39.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:39.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:39.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:39.035 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:39.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:39.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:39.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:39.055 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:39.055 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:39.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:39.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:39.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:39.057 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:39.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:39.057 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:43:39.057 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:43:39.111 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:43:39.111 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:43:39.112 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:43:39.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:39.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:39.582 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:43:40.055 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:43:40.524 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:43:40.994 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:43:41.465 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:43:41.936 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:43:42.413 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:43:42.888 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:43:43.360 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:43:43.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:43.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:43.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:43.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:43.445 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:43:43.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:43.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:43.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:43.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:43.461 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:43:43.461 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:43:43.461 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:43:43.461 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:43:43.461 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:43:43.461 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:43:43.461 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:43:43.461 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3287 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:43.461 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3287 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:43.461 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3287 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:43.461 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3287 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:43.461 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3287 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:43.461 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3287 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:43.461 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3287 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:43.462 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3288 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:43.462 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3288 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:43:48.461 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:43:48.461 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:43:48.463 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:43:48.464 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:43:48.465 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:43:48.465 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:43:48.480 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:43:48.481 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:43:48.481 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:43:48.482 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:43:48.482 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:43:48.485 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:43:48.485 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:43:48.486 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:43:48.486 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:43:48.486 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:43:48.486 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:43:48.487 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:43:48.487 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:43:48.487 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:48.488 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:43:48.488 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:43:48.488 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:43:48.488 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:43:48.489 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:43:48.489 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:43:48.489 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:43:48.489 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:43:48.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:48.490 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:43:48.490 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:43:48.490 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:43:48.490 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:43:48.490 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:43:48.490 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:43:48.490 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:43:48.490 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:43:48.490 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:48.493 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:43:48.493 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:43:48.493 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:43:48.494 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:43:48.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:48.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:48.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:48.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:43:48.498 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:43:48.981 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:43:49.025 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:43:49.027 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:43:49.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:49.029 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:43:49.050 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:49.050 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:49.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:49.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:49.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:49.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:49.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:49.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:49.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:49.085 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:49.085 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:43:49.085 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:43:49.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:49.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:49.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:49.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:49.458 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:43:49.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:49.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:49.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:49.500 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:49.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:49.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:49.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:49.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:49.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:49.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:49.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:49.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:49.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:49.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:49.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:49.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:49.536 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:49.536 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:49.536 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:43:49.536 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:43:49.548 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:43:49.548 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:43:49.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:49.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:49.930 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:43:50.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:50.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:50.108 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:50.108 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:50.108 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:43:50.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:50.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:50.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:50.126 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:50.126 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:50.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:50.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:50.128 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:50.128 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:50.128 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:50.128 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:43:50.128 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:43:50.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:50.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:50.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:50.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:50.404 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:43:50.497 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:50.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:50.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:50.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:50.882 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:43:51.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:51.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:51.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:51.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:51.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:51.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:51.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:51.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:43:51.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:43:51.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:43:51.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:43:51.304 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:51.304 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:43:51.304 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:43:51.304 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:43:51.304 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:43:51.352 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:43:51.352 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:43:51.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:51.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:43:51.355 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:43:51.498 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:51.498 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:51.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:51.502 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:51.830 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:43:52.309 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:43:52.499 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:52.499 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:52.499 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:52.502 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:52.785 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:43:53.254 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:43:53.499 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:43:53.500 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:43:53.500 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:43:53.503 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:43:53.726 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:43:54.203 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:43:54.674 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:43:55.145 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:43:55.620 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:43:56.097 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:43:56.569 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:43:57.042 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:43:57.516 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:43:57.994 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:43:58.471 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:43:58.945 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:43:59.415 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:43:59.886 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:44:00.360 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:44:00.837 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:44:01.306 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:44:01.775 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:44:02.246 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:44:02.717 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:44:03.189 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:44:03.659 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:44:04.129 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:44:04.600 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-05 03:44:05.070 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-05 03:44:05.542 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-05 03:44:06.013 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-05 03:44:06.484 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-05 03:44:06.962 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-05 03:44:07.439 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-05 03:44:07.918 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-05 03:44:08.393 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-05 03:44:08.862 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-05 03:44:09.332 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-05 03:44:09.802 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-05 03:44:10.276 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-05 03:44:10.755 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-05 03:44:11.232 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-05 03:44:11.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:11.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:11.301 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:44:11.304 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:11.304 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:11.304 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:11.304 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:11.305 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:44:11.305 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:44:11.305 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:44:11.305 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:44:11.305 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:44:11.305 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:44:11.305 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:44:11.305 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4913 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:11.305 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4913 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:11.305 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4913 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:11.305 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=4913 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:16.308 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:44:16.308 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:44:16.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:44:16.311 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:44:16.312 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:44:16.315 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:44:16.328 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:44:16.328 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:44:16.328 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:44:16.328 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:44:16.329 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:44:16.331 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:44:16.331 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:44:16.331 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:44:16.331 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:44:16.331 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:44:16.331 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:44:16.331 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:44:16.331 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:44:16.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:16.333 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:44:16.333 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:44:16.333 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:44:16.333 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:44:16.333 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:44:16.333 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:44:16.333 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:44:16.333 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:44:16.334 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:16.335 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:44:16.335 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:44:16.335 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:44:16.335 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:44:16.335 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:44:16.335 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:44:16.335 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:44:16.336 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:44:16.336 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:16.340 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:44:16.340 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:44:16.340 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:44:16.341 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:16.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:16.345 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:44:16.818 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:44:16.880 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:44:16.882 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:44:16.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:16.885 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:44:16.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:16.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:16.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:16.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:16.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:16.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:16.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:16.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:16.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:44:16.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:44:16.935 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:44:16.935 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:44:16.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:44:16.957 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:44:16.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:16.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:17.291 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:44:17.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:17.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:17.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:17.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:17.762 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:44:18.236 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:44:18.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:18.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:18.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:18.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:18.708 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:44:19.183 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:44:19.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:19.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:19.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:19.351 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:19.655 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:44:19.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:19.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:19.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:19.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:19.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:19.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:19.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:19.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:19.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:19.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:19.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:19.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:19.839 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:44:19.839 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:44:19.839 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:44:19.839 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:44:19.889 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:44:19.890 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:44:19.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:19.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:20.128 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:44:20.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:20.347 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:20.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:20.351 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:20.599 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:44:21.068 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:44:21.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:21.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:21.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:21.352 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:21.541 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:44:22.011 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:44:22.484 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:44:22.962 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:44:23.433 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:44:23.904 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:44:24.375 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:44:24.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:24.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:24.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:24.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:24.402 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:44:24.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:24.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:24.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:24.428 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:24.428 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:24.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:24.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:24.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:24.430 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:44:24.430 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:44:24.430 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:44:24.430 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:44:24.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:44:24.466 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:44:24.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:24.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:24.851 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:44:25.325 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:44:25.802 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:44:26.279 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:44:26.756 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:44:27.234 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:44:27.711 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:44:28.189 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:44:28.666 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:44:29.139 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:44:29.618 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:44:30.096 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:44:30.572 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:44:31.049 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:44:31.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:31.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:31.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:31.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:31.228 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:31.229 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:31.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:31.236 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:31.236 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:31.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:31.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:31.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:31.237 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:44:31.238 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:44:31.238 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:44:31.238 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:44:31.283 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:44:31.284 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:44:31.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:31.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:31.518 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:44:31.992 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:44:32.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:32.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:32.077 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:44:32.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:32.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:32.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:32.080 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:32.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:44:32.083 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:44:32.083 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:44:32.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:44:32.083 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:44:32.083 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:44:32.083 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:44:32.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3387 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:32.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3387 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:32.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3387 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:32.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3387 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:32.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3387 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:32.083 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3387 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:37.087 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:44:37.087 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:44:37.087 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:44:37.088 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:44:37.088 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:44:37.088 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:44:37.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:44:37.103 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:44:37.103 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:44:37.103 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:44:37.103 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:44:37.105 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:44:37.105 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:44:37.106 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:44:37.106 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:44:37.106 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:44:37.106 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:44:37.106 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:44:37.106 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:44:37.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:37.108 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:44:37.108 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:44:37.108 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:44:37.108 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:44:37.108 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:44:37.109 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:44:37.109 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:44:37.109 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:44:37.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:37.110 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:44:37.110 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:44:37.111 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:44:37.111 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:44:37.111 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:44:37.111 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:44:37.111 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:44:37.111 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:44:37.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:37.113 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:44:37.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:44:37.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:44:37.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:44:37.113 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:44:37.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:44:37.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:44:37.114 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:44:37.114 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:44:37.114 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:37.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:37.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:37.119 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:44:37.592 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:44:37.650 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:44:37.653 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:44:37.655 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:44:37.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:37.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:37.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:37.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:37.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:37.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:37.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:37.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:37.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:37.707 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:44:37.707 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:44:37.707 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:44:37.707 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:44:37.730 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:44:37.730 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:44:37.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:37.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:38.065 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:44:38.118 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:38.118 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:38.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:38.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:38.540 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:44:39.017 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:44:39.118 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:39.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:39.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:39.124 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:39.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:39.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:39.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:39.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:39.490 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:44:39.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:39.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:39.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:39.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:39.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:39.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:39.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:39.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:39.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:44:39.514 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:44:39.514 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:44:39.514 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:44:39.531 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:44:39.531 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-05 03:44:39.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:39.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:39.960 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:44:40.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:40.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:40.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:40.125 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:40.430 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:44:40.904 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:44:41.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:41.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:41.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:41.126 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:41.379 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:44:41.852 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:44:42.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:42.121 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:42.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:42.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:42.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:42.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:42.255 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:42.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:42.255 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:44:42.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:42.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:42.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:42.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:42.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:42.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:42.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:42.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:42.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:44:42.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:44:42.282 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:44:42.282 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:44:42.321 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:44:42.322 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:44:42.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:44:42.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:42.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:42.799 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:44:43.277 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:44:43.755 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:44:44.232 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:44:44.704 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:44:45.180 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:44:45.657 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:44:46.134 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:44:46.608 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:44:46.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:46.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:46.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:46.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:46.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:46.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:46.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:46.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:46.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:46.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:44:46.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:46.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:46.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:44:46.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:44:46.793 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:44:46.793 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:44:46.839 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.201.22:6700) Recv SETFH cmd
2026-03-05 03:44:46.840 [INFO] transceiver.py:201 (MS@172.18.201.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-05 03:44:46.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:46.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:44:47.081 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:44:47.556 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:44:48.033 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:44:48.508 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:44:48.980 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:44:49.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:44:49.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:44:49.067 [INFO] transceiver.py:205 (MS@172.18.201.22:6700) Frequency hopping disabled
2026-03-05 03:44:49.068 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:49.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:49.068 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:49.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:49.069 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:44:49.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:44:49.070 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:44:49.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:44:49.070 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:44:49.070 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:44:49.070 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:44:54.070 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:44:54.071 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:44:54.072 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:44:54.074 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:44:54.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:44:54.078 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:44:54.092 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:44:54.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:44:54.093 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:44:54.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:44:54.093 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:44:54.096 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:44:54.096 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:44:54.096 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:44:54.096 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:44:54.096 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:44:54.096 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:44:54.096 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:44:54.096 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:44:54.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:54.098 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:44:54.099 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:44:54.099 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:44:54.099 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:44:54.099 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:44:54.099 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:44:54.099 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:44:54.099 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:44:54.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:54.101 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:44:54.101 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:44:54.101 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:44:54.101 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:44:54.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:44:54.102 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:44:54.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:44:54.102 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:44:54.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:44:54.106 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:44:54.106 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:44:54.106 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:54.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:54.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:44:54.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:44:54.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:44:54.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:54.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:54.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:54.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:54.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:44:54.110 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:44:54.581 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:44:54.628 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:44:54.628 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:44:54.629 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:44:54.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:54.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:54.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:54.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:54.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:54.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:54.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:55.050 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:44:55.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:55.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:55.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:55.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:55.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:55.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:55.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:55.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:55.520 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:44:55.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:55.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:55.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:55.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:55.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:55.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:44:55.957 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:44:55.957 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:44:55.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:44:55.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:44:55.961 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:44:55.961 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:44:55.961 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:44:55.961 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:44:55.961 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:44:55.961 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:44:55.961 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:44:55.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.962 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=403 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.963 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.963 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.963 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.963 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.963 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.963 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.963 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:44:55.963 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:00.960 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:00.960 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:00.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:00.963 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:00.965 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:00.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:00.980 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:00.982 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:00.982 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:00.982 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:00.983 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:45:00.985 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:45:00.985 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:45:00.985 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:00.985 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:00.985 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:00.985 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:45:00.985 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:00.985 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:45:00.985 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:00.987 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:45:00.987 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:45:00.987 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:00.987 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:00.987 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:00.987 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:45:00.987 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:00.988 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:45:00.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:00.989 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:45:00.989 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:45:00.989 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:00.989 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:00.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:00.989 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:45:00.989 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:00.989 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:45:00.989 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:00.991 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:45:00.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:45:00.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:45:00.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:45:00.992 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:45:00.992 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:45:00.992 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:45:00.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:00.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:00.997 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:45:01.467 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:45:01.521 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:45:01.522 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:45:01.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:01.523 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:45:01.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:01.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:01.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:01.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:01.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:01.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:01.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:01.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:01.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:01.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:01.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:01.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:01.937 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:45:01.995 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:01.995 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:01.995 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:01.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:02.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.406 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:45:02.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:02.858 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:02.858 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:02.858 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:02.858 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:02.859 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:02.859 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:02.859 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:02.859 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:02.859 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:02.859 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:02.859 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:45:07.862 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:07.862 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:07.864 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:07.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:07.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:07.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:07.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:07.873 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:07.873 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:07.873 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:07.873 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:45:07.876 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:45:07.876 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:45:07.876 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:07.876 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:07.876 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:07.876 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:45:07.876 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:07.876 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:45:07.876 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:07.878 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:45:07.878 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:45:07.878 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:07.878 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:07.878 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:07.879 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:45:07.879 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:07.879 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:45:07.879 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:07.881 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:45:07.881 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:45:07.882 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:07.882 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:07.882 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:07.882 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:45:07.882 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:07.882 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:45:07.882 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:07.886 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:45:07.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:45:07.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:45:07.886 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:45:07.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:45:07.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:45:07.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:45:07.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:45:07.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:45:07.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:07.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:45:07.887 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:45:07.887 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:45:07.887 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:07.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:07.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:07.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:07.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:07.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:07.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:07.892 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:45:08.361 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:45:08.408 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:45:08.408 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:45:08.409 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:45:08.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:08.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:08.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:08.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:08.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:08.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:08.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:08.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:08.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:08.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:08.831 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:45:08.890 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:08.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:08.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:08.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:09.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.303 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:45:09.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:09.735 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:09.735 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:09.735 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:09.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:09.736 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:09.736 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:09.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:09.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:09.736 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:09.736 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:09.736 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:45:14.738 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:14.738 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:14.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:14.741 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:14.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:14.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:14.759 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:14.760 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:14.760 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:14.760 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:14.760 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:45:14.763 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:45:14.763 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:45:14.763 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:14.763 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:14.764 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:14.764 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:45:14.764 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:14.764 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:45:14.764 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:14.766 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:45:14.766 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:45:14.766 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:14.766 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:14.766 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:14.767 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:45:14.767 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:14.767 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:45:14.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:14.768 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:45:14.769 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:45:14.769 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:14.769 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:14.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:14.769 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:45:14.769 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:14.769 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:45:14.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:14.772 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:45:14.772 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:45:14.772 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:45:14.773 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:14.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:14.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:14.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:14.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:14.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:14.777 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:45:15.252 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:45:15.288 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:45:15.288 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:45:15.289 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:45:15.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:15.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:15.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:15.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:15.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:15.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:15.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:15.720 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:45:15.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:15.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:15.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:15.779 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:15.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:15.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:15.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:15.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:16.189 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:45:16.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:16.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:16.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:16.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:16.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:16.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:16.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:16.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:16.602 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:16.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:16.605 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:16.605 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:16.605 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:16.605 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:16.606 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:16.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:16.606 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:45:16.606 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:16.606 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:16.606 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:16.607 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:16.607 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:16.607 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=398 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:21.602 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:21.603 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:21.604 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:21.605 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:21.607 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:21.607 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:21.619 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:21.620 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:21.620 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:21.621 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:21.621 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:45:21.623 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:45:21.623 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:45:21.623 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:21.623 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:21.623 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:21.623 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:45:21.624 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:21.624 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:45:21.624 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:21.626 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:45:21.626 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:45:21.626 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:21.626 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:21.626 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:21.626 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:45:21.626 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:21.626 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:45:21.626 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:21.628 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:45:21.628 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:45:21.628 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:21.628 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:21.628 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:21.628 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:45:21.628 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:21.628 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:45:21.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:21.631 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:45:21.631 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:45:21.631 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:45:21.632 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:21.632 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:21.636 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:45:22.106 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:45:22.161 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:45:22.163 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:45:22.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:22.165 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:45:22.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:22.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:22.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:22.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:22.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:22.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:22.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:22.576 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:45:22.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:22.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:22.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:22.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:22.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:22.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:22.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:22.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:23.049 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:45:23.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:23.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:23.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:23.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:23.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:23.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:23.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:23.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:23.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:23.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:23.509 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:23.510 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:23.510 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:23.510 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:23.510 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:23.510 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:23.510 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:45:28.509 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:28.510 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:28.511 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:28.512 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:28.513 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:28.513 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:28.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:28.521 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:28.521 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:28.522 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:28.522 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:45:28.524 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:45:28.524 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:45:28.524 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:28.524 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:28.524 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:28.524 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:45:28.524 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:28.524 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:45:28.524 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:28.526 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:45:28.526 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:45:28.526 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:28.526 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:28.526 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:28.527 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:45:28.527 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:28.527 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:45:28.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:28.528 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:45:28.528 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:45:28.528 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:28.528 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:28.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:28.528 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:45:28.529 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:28.529 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:45:28.529 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:28.532 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:45:28.532 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:45:28.532 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:45:28.532 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:28.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:28.537 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:45:29.006 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:45:29.070 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:45:29.072 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:45:29.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.075 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:45:29.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:29.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.475 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:45:29.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:29.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:29.537 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:29.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:29.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:29.946 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:45:30.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:30.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:30.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:30.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:30.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:30.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:30.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:30.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:30.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:30.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:30.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:30.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:30.415 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:45:30.420 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:30.420 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:30.421 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:30.421 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:30.422 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:30.423 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:30.423 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:30.423 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:30.423 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:30.423 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:30.423 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:45:30.423 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=411 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:30.423 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=411 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:30.423 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=411 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:30.423 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=411 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:30.423 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=411 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:30.423 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=411 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:35.424 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:35.424 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:35.425 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:35.430 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:35.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:35.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:35.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:35.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:35.444 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:35.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:35.444 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:45:35.446 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:45:35.446 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:45:35.446 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:35.446 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:35.446 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:35.446 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:45:35.446 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:35.446 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:45:35.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:35.448 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:45:35.448 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:45:35.448 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:35.448 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:35.448 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:45:35.448 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:35.448 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:35.448 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:45:35.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:35.449 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:45:35.449 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:45:35.449 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:35.449 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:35.449 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:45:35.450 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:35.450 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:35.450 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:45:35.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:35.451 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:45:35.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:45:35.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:45:35.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:45:35.451 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:45:35.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:45:35.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:45:35.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:45:35.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:45:35.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:35.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:35.451 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:45:35.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:45:35.452 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:45:35.452 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:45:35.452 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:35.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:35.456 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:45:35.939 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:45:35.987 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:45:35.990 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:45:35.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:35.990 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:45:36.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:36.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.415 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:45:36.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:36.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:36.455 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:36.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:36.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.890 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:45:36.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:36.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:37.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:37.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:37.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:37.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:37.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:37.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:37.338 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:37.338 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:37.338 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:37.339 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:37.341 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:37.341 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:37.341 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:37.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:37.341 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:37.341 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:37.341 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:45:37.341 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=405 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:37.341 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=405 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:37.341 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=405 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:37.341 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:37.341 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:37.341 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:37.341 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:37.341 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:37.341 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:37.341 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:37.341 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=406 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:42.341 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:42.341 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:42.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:42.344 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:42.346 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:42.346 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:42.360 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:42.362 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:42.362 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:42.362 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:42.362 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:45:42.366 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:45:42.366 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:45:42.367 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:42.367 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:42.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:42.367 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:45:42.367 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:42.367 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:45:42.367 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:42.369 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:45:42.369 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:45:42.369 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:42.369 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:42.370 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:42.370 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:45:42.370 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:42.370 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:45:42.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:42.372 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:45:42.372 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:45:42.372 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:42.372 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:42.372 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:42.372 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:45:42.372 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:42.372 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:45:42.372 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:45:42.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:45:42.376 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:45:42.376 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:45:42.376 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:42.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:42.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:42.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:42.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:42.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:42.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:42.381 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:45:42.852 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:45:42.918 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:45:42.920 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:45:42.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.922 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:45:42.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:42.993 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:42.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:42.993 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:42.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:42.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:42.994 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:42.994 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:42.994 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:42.994 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:42.994 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:45:42.994 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:47.996 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:47.997 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:47.998 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:47.999 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:47.999 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:48.000 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:48.006 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:48.007 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:48.007 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:48.007 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:48.007 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:45:48.011 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:45:48.011 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:45:48.012 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:48.012 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:48.012 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:48.012 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:45:48.012 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:48.012 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:45:48.012 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:48.013 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:45:48.013 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:45:48.013 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:48.013 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:48.013 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:45:48.014 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:48.014 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:48.014 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:45:48.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:48.015 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:45:48.015 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:45:48.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:48.015 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:48.015 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:45:48.015 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:48.015 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:48.015 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:45:48.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:48.018 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:45:48.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:45:48.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:45:48.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:45:48.018 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:45:48.019 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:45:48.019 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:45:48.019 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:45:48.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:48.020 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:48.024 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:45:48.501 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:45:48.558 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:45:48.559 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:45:48.560 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:45:48.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:48.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:48.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:48.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:48.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:48.673 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:48.673 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:48.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:48.674 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:48.674 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:48.674 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:48.674 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:45:53.677 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:53.677 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:53.678 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:53.680 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:53.681 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:53.684 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:53.694 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:53.695 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:53.695 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:53.695 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:53.695 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:45:53.698 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:45:53.698 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:45:53.698 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:53.698 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:53.698 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:53.698 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:45:53.698 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:53.698 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:45:53.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:53.699 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:45:53.700 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:45:53.700 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:53.700 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:53.700 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:53.700 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:45:53.700 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:53.700 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:45:53.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:53.701 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:45:53.701 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:45:53.701 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:53.701 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:53.701 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:53.701 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:45:53.701 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:53.701 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:45:53.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:53.703 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:45:53.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:45:53.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:45:53.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:45:53.703 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:45:53.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:45:53.703 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:45:53.703 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:45:53.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:45:53.703 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:45:53.704 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:45:53.704 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:45:53.704 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:53.704 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:53.705 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:53.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:53.705 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:53.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:53.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:53.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:53.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:53.709 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:45:54.182 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:45:54.231 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:45:54.232 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:45:54.234 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:45:54.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:54.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:54.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:54.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:54.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:54.341 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:54.341 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:54.341 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:54.341 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:54.341 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:54.341 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:45:54.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:59.345 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:59.345 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:59.347 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:59.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:59.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:59.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:59.356 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:59.356 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:59.356 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:59.356 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:45:59.357 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:45:59.358 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:45:59.358 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:45:59.358 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:59.358 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:59.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:59.359 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:45:59.359 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:45:59.359 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:45:59.359 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:59.360 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:45:59.360 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:45:59.360 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:59.360 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:59.360 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:59.360 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:45:59.360 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:45:59.360 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:45:59.360 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:59.361 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:45:59.361 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:45:59.361 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:59.362 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:45:59.362 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:59.362 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:45:59.362 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:45:59.362 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:45:59.362 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:59.363 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:45:59.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:45:59.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:45:59.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:45:59.363 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:45:59.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:45:59.364 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:45:59.364 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:45:59.364 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:59.364 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:59.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:45:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:45:59.365 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:45:59.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:59.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:59.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:59.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:59.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:45:59.369 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:45:59.849 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:45:59.880 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:45:59.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.881 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:45:59.882 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:45:59.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:45:59.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:45:59.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:45:59.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:45:59.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:45:59.965 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:45:59.965 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:45:59.965 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:45:59.965 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:45:59.965 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:45:59.965 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:45:59.965 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:45:59.965 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:59.965 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:59.965 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:59.965 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:59.965 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:45:59.965 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=129 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:04.966 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:04.967 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:04.968 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:04.970 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:04.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:04.974 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:04.986 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:04.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:04.986 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:04.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:04.986 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:46:04.989 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:46:04.989 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:46:04.989 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:04.989 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:04.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:04.989 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:46:04.989 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:04.989 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:46:04.989 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:04.992 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:46:04.992 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:46:04.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:04.992 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:04.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:04.992 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:46:04.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:04.992 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:46:04.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:04.994 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:46:04.994 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:46:04.994 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:04.994 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:04.994 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:04.994 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:46:04.994 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:04.994 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:46:04.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:04.997 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:46:04.997 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:46:04.997 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:46:04.998 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:04.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:04.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:04.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:04.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:04.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:04.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:05.002 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:46:05.473 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:46:05.517 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:46:05.518 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:46:05.518 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:46:05.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:05.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:05.576 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:05.576 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:05.576 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:05.576 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:05.577 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:05.577 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:05.577 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:05.577 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:05.577 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:05.577 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:05.578 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:46:10.580 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:10.580 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:10.581 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:10.583 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:10.583 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:10.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:10.590 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:10.591 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:10.591 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:10.591 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:10.591 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:46:10.593 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:46:10.594 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:46:10.594 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:10.594 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:10.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:10.594 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:46:10.594 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:10.594 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:46:10.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:10.596 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:46:10.596 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:46:10.596 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:10.596 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:10.597 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:46:10.597 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:10.597 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:10.597 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:46:10.597 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:10.599 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:46:10.599 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:46:10.599 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:10.599 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:10.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:10.599 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:46:10.599 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:10.599 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:46:10.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:46:10.602 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:46:10.602 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:46:10.602 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:46:10.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:10.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:10.607 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:46:11.084 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:46:11.135 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:46:11.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.138 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:46:11.139 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:46:11.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:11.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:11.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:11.242 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:11.242 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:11.242 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:11.243 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:11.243 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:11.243 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:11.243 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:11.243 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:11.243 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:11.243 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:46:11.243 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=138 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:11.243 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=138 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:11.243 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=138 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:11.243 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=138 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:11.243 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=138 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:16.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:16.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:16.247 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:16.249 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:16.249 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:16.249 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:16.258 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:16.259 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:16.259 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:16.260 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:16.260 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:46:16.263 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:46:16.264 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:46:16.264 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:16.264 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:16.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:16.265 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:46:16.266 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:16.266 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:46:16.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:16.267 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:46:16.268 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:46:16.268 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:16.268 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:16.268 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:16.268 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:46:16.269 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:16.269 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:46:16.269 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:16.271 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:46:16.271 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:46:16.272 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:16.272 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:16.272 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:16.272 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:46:16.272 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:16.272 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:46:16.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:16.276 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:46:16.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:46:16.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:46:16.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:16.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:16.278 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:46:16.278 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:46:16.278 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:46:16.278 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:46:16.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:16.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:16.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:16.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:46:16.278 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:16.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:16.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:16.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:16.283 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:46:16.758 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:46:16.807 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:46:16.808 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:46:16.810 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:46:16.810 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:16.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:16.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:16.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:16.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:16.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:16.911 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:16.911 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:16.911 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:16.911 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:16.911 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:16.911 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:16.911 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:46:21.913 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:21.914 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:21.918 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:21.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:21.918 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:21.918 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:21.929 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:21.931 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:21.931 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:21.931 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:21.931 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:46:21.935 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:46:21.935 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:46:21.935 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:21.936 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:21.936 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:21.936 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:46:21.936 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:21.936 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:46:21.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:21.939 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:46:21.939 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:46:21.939 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:21.939 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:21.939 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:21.940 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:46:21.940 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:21.940 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:46:21.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:21.942 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:46:21.942 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:46:21.942 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:21.942 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:21.942 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:21.943 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:46:21.943 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:21.943 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:46:21.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:21.946 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:46:21.947 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:46:21.947 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:46:21.947 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:21.947 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:21.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:21.952 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:46:22.425 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:46:22.490 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:46:22.492 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:46:22.494 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:46:22.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:22.496 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:46:22.496 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:46:22.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:46:22.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:22.497 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:46:22.497 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:46:22.497 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:46:22.497 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:46:22.894 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:46:22.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:22.951 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:22.952 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:22.959 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:23.368 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:46:23.844 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:46:23.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:23.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:23.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:23.960 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:24.322 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:46:24.798 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:46:24.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:24.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:24.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:24.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:25.275 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:46:25.753 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:46:25.930 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:46:25.930 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:46:25.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:25.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:25.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:25.935 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:25.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:25.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:25.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:25.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:25.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:25.938 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:46:25.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=857 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=857 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=857 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=857 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=857 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=857 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=857 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=857 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=858 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=858 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=858 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=858 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=858 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:25.938 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=858 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:30.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:30.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:30.939 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:30.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:30.942 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:30.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:30.952 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:30.952 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:30.952 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:30.952 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:30.952 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:46:30.954 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:46:30.954 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:46:30.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:30.955 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:30.955 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:30.955 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:46:30.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:30.955 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:46:30.955 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:30.957 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:46:30.957 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:46:30.957 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:30.957 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:30.957 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:30.957 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:46:30.957 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:30.957 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:46:30.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:30.959 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:46:30.959 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:46:30.959 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:30.959 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:30.959 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:30.959 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:46:30.959 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:30.959 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:46:30.959 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:30.961 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:46:30.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:46:30.961 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:46:30.961 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:46:30.961 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:46:30.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:46:30.962 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:46:30.962 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:46:30.962 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:30.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:30.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:30.967 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:46:31.443 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:46:31.494 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:46:31.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:31.496 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:46:31.497 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:46:31.521 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:46:31.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:46:31.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:46:31.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:31.524 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:46:31.524 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:46:31.525 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:46:31.525 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:46:31.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 03:46:31.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:46:31.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:46:31.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:31.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:31.916 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:46:31.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:31.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:31.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:31.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:32.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:32.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:46:32.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:46:32.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:46:32.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:32.037 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:46:32.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:46:32.038 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:46:32.038 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:46:32.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:32.054 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:46:32.054 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:46:32.062 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:32.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:32.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:32.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:32.066 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:32.066 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:32.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:32.066 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:32.066 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:32.066 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:46:32.067 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:32.067 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=238 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:32.067 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=238 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:32.067 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=238 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:32.067 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=238 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:32.068 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=238 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:32.068 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=238 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:32.068 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=238 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:32.068 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=239 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:32.068 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=239 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:37.066 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:37.066 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:37.068 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:37.069 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:37.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:37.070 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:37.079 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:37.081 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:37.081 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:37.081 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:37.082 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:46:37.086 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:46:37.086 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:46:37.086 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:37.086 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:37.087 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:37.087 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:46:37.087 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:37.087 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:46:37.087 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:37.089 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:46:37.089 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:46:37.089 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:37.089 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:37.089 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:37.090 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:46:37.090 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:37.090 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:46:37.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:37.092 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:46:37.092 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:46:37.092 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:37.092 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:37.092 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:37.092 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:46:37.092 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:37.092 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:46:37.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:37.095 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:46:37.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:46:37.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:46:37.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:46:37.095 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:46:37.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:46:37.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:46:37.096 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:46:37.096 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:46:37.096 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:37.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:37.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:37.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:37.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:37.101 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:46:37.580 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:46:37.614 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:46:37.615 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:46:37.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:37.618 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:46:37.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:46:37.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:46:37.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:46:37.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:37.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:46:37.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:46:37.630 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:46:37.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:46:37.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 03:46:37.673 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:46:37.673 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:46:37.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:37.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:37.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:37.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:37.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:46:37.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:46:37.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:46:37.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:37.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:46:37.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:46:37.794 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:46:37.795 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:46:38.055 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:46:38.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:38.100 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:38.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:38.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:38.532 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:46:39.010 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:46:39.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:39.102 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:39.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:39.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:39.488 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:46:39.965 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-05 03:46:40.102 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:40.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:40.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:40.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:40.442 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-05 03:46:40.920 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-05 03:46:41.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:41.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:41.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:41.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:41.398 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-05 03:46:41.874 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-05 03:46:42.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:42.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:42.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:42.110 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:42.351 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-05 03:46:42.824 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-05 03:46:43.297 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-05 03:46:43.775 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-05 03:46:44.252 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-05 03:46:44.730 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-05 03:46:45.208 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-05 03:46:45.685 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-05 03:46:46.163 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-05 03:46:46.641 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-05 03:46:47.119 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-05 03:46:47.597 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-05 03:46:48.075 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-05 03:46:48.552 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-05 03:46:49.030 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-05 03:46:49.508 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-05 03:46:49.985 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-05 03:46:50.463 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-05 03:46:50.941 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-05 03:46:51.418 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-05 03:46:51.895 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-05 03:46:52.370 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-05 03:46:52.848 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-05 03:46:53.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:53.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:46:53.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:46:53.145 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=3432 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.145 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=3432 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:46:53.145 [WARNING] transceiver.py:257 (MS@172.18.201.22:6700) RX TRXD message (fn=3432 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:53.151 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:46:53.151 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:46:53.151 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:46:53.151 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:46:53.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:53.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:46:53.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:46:53.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:53.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:53.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:53.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:53.189 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:53.189 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:53.189 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:53.189 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:53.190 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:53.190 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:53.190 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:46:53.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3441 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3441 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.190 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3441 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3441 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3441 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3441 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3442 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3442 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3442 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3442 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3442 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3442 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3442 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:53.191 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=3442 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:58.188 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:58.188 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:58.190 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:58.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:58.193 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:58.195 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:58.208 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:58.208 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:58.208 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:58.209 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:46:58.209 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:46:58.211 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:46:58.211 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:46:58.211 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:58.211 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:58.211 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:58.211 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:46:58.211 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:46:58.211 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:46:58.211 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:58.213 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:46:58.213 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:46:58.213 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:58.213 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:58.213 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:58.213 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:46:58.213 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:46:58.213 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:46:58.213 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:58.215 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:46:58.215 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:46:58.215 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:58.215 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:46:58.215 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:58.215 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:46:58.215 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:46:58.215 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:46:58.215 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:58.218 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:46:58.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:46:58.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:46:58.218 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:46:58.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:46:58.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:46:58.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:46:58.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:46:58.219 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:46:58.219 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:46:58.219 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:46:58.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:58.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:46:58.224 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:46:58.693 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:46:58.761 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:46:58.763 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:46:58.765 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:46:58.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:58.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:46:58.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:46:58.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:46:58.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:58.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:46:58.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:46:58.791 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:46:58.791 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:46:58.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 03:46:58.839 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:46:58.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:46:58.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:58.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:58.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:59.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 03:46:59.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:59.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:46:59.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:46:59.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:46:59.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:46:59.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:46:59.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:46:59.148 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:46:59.148 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:46:59.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:46:59.165 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:46:59.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:46:59.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:46:59.174 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:46:59.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:46:59.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:46:59.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:46:59.177 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:46:59.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:46:59.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:46:59.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:46:59.177 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:46:59.177 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:46:59.177 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:46:59.177 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=208 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:59.177 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=208 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:59.177 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=208 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:59.177 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=208 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:59.177 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=208 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:46:59.177 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=208 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:47:04.183 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:47:04.183 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:47:04.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:47:04.184 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:47:04.184 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:47:04.184 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:47:04.198 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:47:04.200 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:47:04.200 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:47:04.200 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:47:04.200 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:47:04.204 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:47:04.205 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:47:04.205 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:47:04.205 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:47:04.205 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:47:04.205 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:47:04.206 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:47:04.206 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:47:04.206 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:47:04.209 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:47:04.209 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:47:04.209 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:47:04.209 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:47:04.210 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:47:04.210 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:47:04.210 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:47:04.210 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:47:04.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:47:04.213 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:47:04.213 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:47:04.213 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:47:04.213 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:47:04.213 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:47:04.213 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:47:04.213 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:47:04.213 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:47:04.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:47:04.223 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:47:04.224 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:47:04.224 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:47:04.224 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:04.224 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:04.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:04.229 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-05 03:47:04.706 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-05 03:47:04.766 [DEBUG] fake_trx.py:278 (BTS@172.18.201.20:5700) Recv FAKE_TOA cmd
2026-03-05 03:47:04.767 [DEBUG] fake_trx.py:297 (BTS@172.18.201.20:5700) Recv FAKE_RSSI cmd
2026-03-05 03:47:04.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:47:04.770 [DEBUG] fake_trx.py:322 (BTS@172.18.201.20:5700) Recv FAKE_CI cmd
2026-03-05 03:47:04.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:47:04.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:47:04.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:47:04.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:47:04.789 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:47:04.789 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:47:04.789 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:47:04.789 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:47:04.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD HANDOVER
2026-03-05 03:47:04.801 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:47:04.801 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:47:04.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:47:04.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:47:05.183 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-05 03:47:05.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:47:05.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:47:05.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:47:05.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:47:05.660 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-05 03:47:06.137 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-05 03:47:06.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:47:06.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:47:06.231 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:47:06.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:47:06.614 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-05 03:47:06.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:47:06.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:47:06.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:47:06.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD ECHO
2026-03-05 03:47:06.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.201.22:6700) Ignore CMD SETSLOT
2026-03-05 03:47:06.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.201.22:6700) Recv RXTUNE cmd
2026-03-05 03:47:06.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.201.22:6700) Recv TXTUNE cmd
2026-03-05 03:47:06.828 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.201.22:6700) Recv POWERON CMD
2026-03-05 03:47:06.828 [INFO] ctrl_if_trx.py:109 (MS@172.18.201.22:6700) Starting transceiver...
2026-03-05 03:47:06.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD NOHANDOVER
2026-03-05 03:47:06.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.201.22:6700) Recv POWEROFF cmd
2026-03-05 03:47:06.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.201.22:6700) Stopping transceiver...
2026-03-05 03:47:06.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:47:06.858 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:47:06.858 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:47:06.858 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:47:06.862 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:47:06.862 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:47:06.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:47:06.862 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:47:06.862 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:47:06.862 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:47:06.863 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:47:06.863 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:47:06.863 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:47:06.863 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:47:06.863 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:47:06.863 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:47:06.863 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:47:06.864 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:47:06.864 [WARNING] transceiver.py:257 (BTS@172.18.201.20:5700) RX TRXD message (ver=1 fn=565 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-05 03:47:11.858 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:47:11.858 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:47:11.858 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:47:11.859 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:47:11.859 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:47:11.859 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:47:11.861 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:47:11.862 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:47:11.862 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:47:11.862 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:47:11.862 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:47:11.862 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:47:11.862 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:47:11.862 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:47:11.862 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:47:11.862 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:47:11.862 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:47:11.862 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:47:11.862 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:47:11.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:47:11.863 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:47:11.863 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:47:11.863 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:47:11.863 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:47:11.863 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:47:11.863 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:47:11.863 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:47:11.863 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:47:11.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:47:11.864 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:47:11.864 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:47:11.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:47:11.864 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:47:11.864 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:47:11.864 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:47:11.864 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:47:11.864 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:47:11.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:47:11.865 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:47:11.865 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:47:11.865 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:11.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:11.866 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:47:11.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:11.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:11.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:11.866 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:47:11.866 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:47:11.866 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:47:11.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:11.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:11.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:16.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:47:16.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:47:16.868 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:47:16.868 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:47:16.868 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:47:16.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:47:16.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:47:16.872 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:47:16.872 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.201.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:47:16.872 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.201.20:5700) Recv SETFORMAT cmd
2026-03-05 03:47:16.872 [INFO] ctrl_if_trx.py:201 (BTS@172.18.201.20:5700) TRXD header version 1 -> 1
2026-03-05 03:47:16.872 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.201.20:5700/1) Recv RXTUNE cmd
2026-03-05 03:47:16.872 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.201.20:5700/1) Recv TXTUNE cmd
2026-03-05 03:47:16.872 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:47:16.873 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.201.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:47:16.873 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:47:16.873 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.201.20:5700/1) Recv NOMTXPOWER cmd
2026-03-05 03:47:16.873 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.201.20:5700/1) Recv SETFORMAT cmd
2026-03-05 03:47:16.873 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.201.20:5700/1) TRXD header version 1 -> 1
2026-03-05 03:47:16.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.201.20:5700/1) Recv SETPOWER cmd
2026-03-05 03:47:16.873 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.201.20:5700/2) Recv RXTUNE cmd
2026-03-05 03:47:16.873 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.201.20:5700/2) Recv TXTUNE cmd
2026-03-05 03:47:16.873 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:47:16.873 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.201.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:47:16.873 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:47:16.873 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.201.20:5700/2) Recv NOMTXPOWER cmd
2026-03-05 03:47:16.873 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.201.20:5700/2) Recv SETFORMAT cmd
2026-03-05 03:47:16.873 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.201.20:5700/2) TRXD header version 1 -> 1
2026-03-05 03:47:16.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.201.20:5700/2) Recv SETPOWER cmd
2026-03-05 03:47:16.874 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.201.20:5700/3) Recv RXTUNE cmd
2026-03-05 03:47:16.874 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.201.20:5700/3) Recv TXTUNE cmd
2026-03-05 03:47:16.874 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:47:16.874 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.201.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-05 03:47:16.874 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd
2026-03-05 03:47:16.874 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.201.20:5700/3) Recv NOMTXPOWER cmd
2026-03-05 03:47:16.874 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.201.20:5700/3) Recv SETFORMAT cmd
2026-03-05 03:47:16.874 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.201.20:5700/3) TRXD header version 1 -> 1
2026-03-05 03:47:16.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.201.20:5700/3) Recv SETPOWER cmd
2026-03-05 03:47:16.875 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.201.20:5700) Recv RXTUNE cmd
2026-03-05 03:47:16.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETTSC
2026-03-05 03:47:16.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETTSC
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETTSC
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.201.20:5700) Recv TXTUNE cmd
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETRXGAIN
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETRXGAIN
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETRXGAIN
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETTSC
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.201.20:5700) Recv NOMTXPOWER cmd
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.201.20:5700) Recv SETPOWER cmd
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.201.20:5700) Recv POWERON CMD
2026-03-05 03:47:16.876 [INFO] ctrl_if_trx.py:109 (BTS@172.18.201.20:5700) Starting transceiver...
2026-03-05 03:47:16.876 [INFO] transceiver.py:243 Starting clock generator
2026-03-05 03:47:16.876 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:16.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETRXGAIN
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.201.20:5700/1) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.201.20:5700/1) Recv RFMUTE cmd
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.201.20:5700/2) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.201.20:5700) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.201.20:5700/3) Ignore CMD SETSLOT
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.201.20:5700) Recv RFMUTE cmd
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.201.20:5700/2) Recv RFMUTE cmd
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.201.20:5700) Recv POWEROFF cmd
2026-03-05 03:47:16.877 [INFO] ctrl_if_trx.py:117 (BTS@172.18.201.20:5700) Stopping transceiver...
2026-03-05 03:47:16.877 [INFO] transceiver.py:246 Stopping clock generator
2026-03-05 03:47:16.877 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.201.20:5700/3) Recv RFMUTE cmd